projects/linux·blob master · refs

2742 lines · 84.5 KiB

1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include <drm/amdgpu_drm.h>
30
31#include "amdgpu.h"
32#include "amdgpu_atombios.h"
33#include "amdgpu_ih.h"
34#include "amdgpu_uvd.h"
35#include "amdgpu_vce.h"
36#include "atom.h"
37#include "amd_pcie.h"
38#include "amdgpu_video_codecs.h"
39
40#include "si_dpm.h"
41#include "sid.h"
42#include "si_ih.h"
43#include "gfx_v6_0.h"
44#include "gmc_v6_0.h"
45#include "si_dma.h"
46#include "dce_v6_0.h"
47#include "si.h"
48#include "uvd_v3_1.h"
49#include "vce_v1_0.h"
50
51#include "uvd/uvd_4_0_d.h"
52
53#include "smu/smu_6_0_d.h"
54#include "smu/smu_6_0_sh_mask.h"
55
56#include "gca/gfx_6_0_d.h"
57#include "gca/gfx_6_0_sh_mask.h"
58
59#include "oss/oss_1_0_d.h"
60#include "oss/oss_1_0_sh_mask.h"
61
62#include "gmc/gmc_6_0_d.h"
63#include"gmc/gmc_6_0_sh_mask.h"
64
65#include "dce/dce_6_0_d.h"
66#include "dce/dce_6_0_sh_mask.h"
67
68#include "bif/bif_3_0_d.h"
69#include "bif/bif_3_0_sh_mask.h"
70#include "si_enums.h"
71
72#include "amdgpu_dm.h"
73#include "amdgpu_vkms.h"
74
75static const u32 tahiti_golden_registers[] =
76{
77 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
78 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
79 mmDB_DEBUG, 0xffffffff, 0x00000000,
80 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
81 mmDB_DEBUG3, 0x0002021c, 0x00020200,
82 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
83 0x340c, 0x000000c0, 0x00800040,
84 0x360c, 0x000000c0, 0x00800040,
85 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
86 mmFBC_MISC, 0x00200000, 0x50100000,
87 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
88 mmMC_ARB_WTM_CNTL_RD, 0x00000003, 0x000007ff,
89 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
90 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
91 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
92 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
93 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
94 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a,
95 0x000c, 0xffffffff, 0x0040,
96 0x000d, 0x00000040, 0x00004040,
97 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
98 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000,
99 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000,
100 mmSX_DEBUG_1, 0x0000007f, 0x00000020,
101 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
102 mmTCP_ADDR_CONFIG, 0x00000200, 0x000002fb,
103 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
104 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
105 mmVGT_FIFO_DEPTHS, 0xffffffff, 0x000fff40,
106 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
107 mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8,
108 mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
109 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
110 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
111 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
112 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
113};
114
115static const u32 tahiti_golden_registers2[] =
116{
117 mmMCIF_MEM_CONTROL, 0x00000001, 0x00000001,
118};
119
120static const u32 tahiti_golden_rlc_registers[] =
121{
122 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
123 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005,
124 0x311f, 0xffffffff, 0x10104040,
125 0x3122, 0xffffffff, 0x0100000a,
126 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
127 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
128 mmUVD_CGC_GATE, 0x00000008, 0x00000000,
129};
130
131static const u32 pitcairn_golden_registers[] =
132{
133 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
134 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
135 mmDB_DEBUG, 0xffffffff, 0x00000000,
136 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
137 mmDB_DEBUG3, 0x0002021c, 0x00020200,
138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 0x340c, 0x000300c0, 0x00800040,
140 0x360c, 0x000300c0, 0x00800040,
141 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
142 mmFBC_MISC, 0x00200000, 0x50100000,
143 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
144 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
145 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
146 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
147 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
148 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
149 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
150 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a,
151 0x000c, 0xffffffff, 0x0040,
152 0x000d, 0x00000040, 0x00004040,
153 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
154 mmSX_DEBUG_1, 0x0000007f, 0x00000020,
155 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
156 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
157 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
158 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
159 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
160 mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
161 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
162 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
163 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
164 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
165};
166
167static const u32 pitcairn_golden_rlc_registers[] =
168{
169 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
170 mmRLC_LB_PARAMS, 0xffffffff, 0x00601004,
171 0x311f, 0xffffffff, 0x10102020,
172 0x3122, 0xffffffff, 0x01000020,
173 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
174 mmRLC_LB_CNTL, 0xffffffff, 0x800000a4,
175};
176
177static const u32 verde_pg_init[] =
178{
179 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x40000,
180 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x200010ff,
181 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
182 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
183 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
184 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
185 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
186 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x7007,
187 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x300010ff,
188 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
189 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
190 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
191 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
192 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
193 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x400000,
194 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x100010ff,
195 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
196 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
197 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
198 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
199 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
200 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x120200,
201 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x500010ff,
202 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
203 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
204 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
205 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
206 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
207 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x1e1e16,
208 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x600010ff,
209 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
210 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
211 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
212 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
213 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
214 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x171f1e,
215 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x700010ff,
216 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
217 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
218 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
219 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
220 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
221 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0,
222 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x9ff,
223 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x0,
224 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10000800,
225 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf,
226 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf,
227 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4,
228 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1000051e,
229 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff,
230 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff,
231 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x8,
232 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x80500,
233 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x12,
234 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x9050c,
235 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1d,
236 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xb052c,
237 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2a,
238 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1053e,
239 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2d,
240 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10546,
241 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x30,
242 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xa054e,
243 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3c,
244 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1055f,
245 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3f,
246 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10567,
247 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x42,
248 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1056f,
249 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x45,
250 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10572,
251 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x48,
252 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20575,
253 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4c,
254 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x190801,
255 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x67,
256 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1082a,
257 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x6a,
258 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1b082d,
259 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x87,
260 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x310851,
261 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xba,
262 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x891,
263 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbc,
264 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x893,
265 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbe,
266 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20895,
267 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc2,
268 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20899,
269 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc6,
270 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2089d,
271 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xca,
272 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a1,
273 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xcc,
274 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a3,
275 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xce,
276 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x308a5,
277 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xd3,
278 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x6d08cd,
279 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x142,
280 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2000095a,
281 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1,
282 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x144,
283 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x301f095b,
284 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x165,
285 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc094d,
286 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x173,
287 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf096d,
288 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x184,
289 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x15097f,
290 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x19b,
291 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc0998,
292 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1a9,
293 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x409a7,
294 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1af,
295 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xcdc,
296 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1b1,
297 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x800,
298 mmGMCON_RENG_EXECUTE, 0xffffffff, 0x6c9b2000,
299 mmGMCON_MISC2, 0xfc00, 0x2000,
300 mmGMCON_MISC3, 0xffffffff, 0xfc0,
301 mmMC_PMG_AUTO_CFG, 0x00000100, 0x100,
302};
303
304static const u32 verde_golden_rlc_registers[] =
305{
306 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002,
307 mmRLC_LB_PARAMS, 0xffffffff, 0x033f1005,
308 0x311f, 0xffffffff, 0x10808020,
309 0x3122, 0xffffffff, 0x00800008,
310 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000,
311 mmRLC_LB_CNTL, 0xffffffff, 0x80010014,
312};
313
314static const u32 verde_golden_registers[] =
315{
316 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
317 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
318 mmDB_DEBUG, 0xffffffff, 0x00000000,
319 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
320 mmDB_DEBUG3, 0x0002021c, 0x00020200,
321 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
322 0x340c, 0x000300c0, 0x00800040,
323 0x360c, 0x000300c0, 0x00800040,
324 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
325 mmFBC_MISC, 0x00200000, 0x50100000,
326 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
327 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
328 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
329 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
330 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
331 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
332 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
333 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x0000124a,
334 0x000c, 0xffffffff, 0x0040,
335 0x000d, 0x00000040, 0x00004040,
336 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
337 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000,
338 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000,
339 mmSX_DEBUG_1, 0x0000007f, 0x00000020,
340 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
341 mmTCP_ADDR_CONFIG, 0x000003ff, 0x00000003,
342 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
343 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001032,
344 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
345 mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
346 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
347 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
348 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
349 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
350};
351
352static const u32 oland_golden_registers[] =
353{
354 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
355 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
356 mmDB_DEBUG, 0xffffffff, 0x00000000,
357 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
358 mmDB_DEBUG3, 0x0002021c, 0x00020200,
359 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
360 0x340c, 0x000300c0, 0x00800040,
361 0x360c, 0x000300c0, 0x00800040,
362 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
363 mmFBC_MISC, 0x00200000, 0x50100000,
364 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011,
365 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
366 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
367 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
368 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
369 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
370 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
371 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000082,
372 0x000c, 0xffffffff, 0x0040,
373 0x000d, 0x00000040, 0x00004040,
374 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000,
375 mmSX_DEBUG_1, 0x0000007f, 0x00000020,
376 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
377 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
378 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
379 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
380 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
381 mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
382 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
383 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
384 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
385 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
386
387};
388
389static const u32 oland_golden_rlc_registers[] =
390{
391 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002,
392 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005,
393 0x311f, 0xffffffff, 0x10104040,
394 0x3122, 0xffffffff, 0x0100000a,
395 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
396 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
397};
398
399static const u32 hainan_golden_registers[] =
400{
401 0x17bc, 0x00000030, 0x00000011,
402 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
403 mmDB_DEBUG, 0xffffffff, 0x00000000,
404 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
405 mmDB_DEBUG3, 0x0002021c, 0x00020200,
406 0x031e, 0x00000080, 0x00000000,
407 0x3430, 0xff000fff, 0x00000100,
408 0x340c, 0x000300c0, 0x00800040,
409 0x3630, 0xff000fff, 0x00000100,
410 0x360c, 0x000300c0, 0x00800040,
411 0x16ec, 0x000000f0, 0x00000070,
412 0x16f0, 0x00200000, 0x50100000,
413 0x1c0c, 0x31000311, 0x00000011,
414 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2,
415 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000,
416 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007,
417 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff,
418 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
419 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000,
420 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000000,
421 0x000c, 0xffffffff, 0x0040,
422 0x000d, 0x00000040, 0x00004040,
423 mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000,
424 mmSX_DEBUG_1, 0x0000007f, 0x00000020,
425 mmTA_CNTL_AUX, 0x00010000, 0x00010000,
426 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
427 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
428 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
429 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010,
430 mmVM_L2_CG, 0x000c0fc0, 0x000c0400,
431 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff,
432 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
433 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
434 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
435};
436
437static const u32 hainan_golden_registers2[] =
438{
439 mmGB_ADDR_CONFIG, 0xffffffff, 0x2011003,
440};
441
442static const u32 tahiti_mgcg_cgcg_init[] =
443{
444 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
445 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
446 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
447 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
451 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
452 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
453 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
454 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
455 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
456 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
458 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
459 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
460 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
461 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
462 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
463 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
464 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
465 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
466 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
467 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
468 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
469 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
470 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
471 0x2458, 0xffffffff, 0x00010000,
472 0x2459, 0xffffffff, 0x00030002,
473 0x245a, 0xffffffff, 0x00040007,
474 0x245b, 0xffffffff, 0x00060005,
475 0x245c, 0xffffffff, 0x00090008,
476 0x245d, 0xffffffff, 0x00020001,
477 0x245e, 0xffffffff, 0x00040003,
478 0x245f, 0xffffffff, 0x00000007,
479 0x2460, 0xffffffff, 0x00060005,
480 0x2461, 0xffffffff, 0x00090008,
481 0x2462, 0xffffffff, 0x00030002,
482 0x2463, 0xffffffff, 0x00050004,
483 0x2464, 0xffffffff, 0x00000008,
484 0x2465, 0xffffffff, 0x00070006,
485 0x2466, 0xffffffff, 0x000a0009,
486 0x2467, 0xffffffff, 0x00040003,
487 0x2468, 0xffffffff, 0x00060005,
488 0x2469, 0xffffffff, 0x00000009,
489 0x246a, 0xffffffff, 0x00080007,
490 0x246b, 0xffffffff, 0x000b000a,
491 0x246c, 0xffffffff, 0x00050004,
492 0x246d, 0xffffffff, 0x00070006,
493 0x246e, 0xffffffff, 0x0008000b,
494 0x246f, 0xffffffff, 0x000a0009,
495 0x2470, 0xffffffff, 0x000d000c,
496 0x2471, 0xffffffff, 0x00060005,
497 0x2472, 0xffffffff, 0x00080007,
498 0x2473, 0xffffffff, 0x0000000b,
499 0x2474, 0xffffffff, 0x000a0009,
500 0x2475, 0xffffffff, 0x000d000c,
501 0x2476, 0xffffffff, 0x00070006,
502 0x2477, 0xffffffff, 0x00090008,
503 0x2478, 0xffffffff, 0x0000000c,
504 0x2479, 0xffffffff, 0x000b000a,
505 0x247a, 0xffffffff, 0x000e000d,
506 0x247b, 0xffffffff, 0x00080007,
507 0x247c, 0xffffffff, 0x000a0009,
508 0x247d, 0xffffffff, 0x0000000d,
509 0x247e, 0xffffffff, 0x000c000b,
510 0x247f, 0xffffffff, 0x000f000e,
511 0x2480, 0xffffffff, 0x00090008,
512 0x2481, 0xffffffff, 0x000b000a,
513 0x2482, 0xffffffff, 0x000c000f,
514 0x2483, 0xffffffff, 0x000e000d,
515 0x2484, 0xffffffff, 0x00110010,
516 0x2485, 0xffffffff, 0x000a0009,
517 0x2486, 0xffffffff, 0x000c000b,
518 0x2487, 0xffffffff, 0x0000000f,
519 0x2488, 0xffffffff, 0x000e000d,
520 0x2489, 0xffffffff, 0x00110010,
521 0x248a, 0xffffffff, 0x000b000a,
522 0x248b, 0xffffffff, 0x000d000c,
523 0x248c, 0xffffffff, 0x00000010,
524 0x248d, 0xffffffff, 0x000f000e,
525 0x248e, 0xffffffff, 0x00120011,
526 0x248f, 0xffffffff, 0x000c000b,
527 0x2490, 0xffffffff, 0x000e000d,
528 0x2491, 0xffffffff, 0x00000011,
529 0x2492, 0xffffffff, 0x0010000f,
530 0x2493, 0xffffffff, 0x00130012,
531 0x2494, 0xffffffff, 0x000d000c,
532 0x2495, 0xffffffff, 0x000f000e,
533 0x2496, 0xffffffff, 0x00100013,
534 0x2497, 0xffffffff, 0x00120011,
535 0x2498, 0xffffffff, 0x00150014,
536 0x2499, 0xffffffff, 0x000e000d,
537 0x249a, 0xffffffff, 0x0010000f,
538 0x249b, 0xffffffff, 0x00000013,
539 0x249c, 0xffffffff, 0x00120011,
540 0x249d, 0xffffffff, 0x00150014,
541 0x249e, 0xffffffff, 0x000f000e,
542 0x249f, 0xffffffff, 0x00110010,
543 0x24a0, 0xffffffff, 0x00000014,
544 0x24a1, 0xffffffff, 0x00130012,
545 0x24a2, 0xffffffff, 0x00160015,
546 0x24a3, 0xffffffff, 0x0010000f,
547 0x24a4, 0xffffffff, 0x00120011,
548 0x24a5, 0xffffffff, 0x00000015,
549 0x24a6, 0xffffffff, 0x00140013,
550 0x24a7, 0xffffffff, 0x00170016,
551 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
552 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
553 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
554 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
555 0x000c, 0xffffffff, 0x0000001c,
556 0x000d, 0x000f0000, 0x000f0000,
557 0x0583, 0xffffffff, 0x00000100,
558 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
559 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
560 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
561 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
562 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
563 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
564 0x157a, 0x00000001, 0x00000001,
565 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
566 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
567 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
568 0x3430, 0xfffffff0, 0x00000100,
569 0x3630, 0xfffffff0, 0x00000100,
570};
571static const u32 pitcairn_mgcg_cgcg_init[] =
572{
573 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
574 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
575 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
576 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
577 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
578 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
579 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
580 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
581 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
582 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
583 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
584 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
585 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
586 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
587 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
588 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
589 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
590 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
591 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
592 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
593 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
594 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
595 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
596 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
597 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
598 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
599 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
600 0x2458, 0xffffffff, 0x00010000,
601 0x2459, 0xffffffff, 0x00030002,
602 0x245a, 0xffffffff, 0x00040007,
603 0x245b, 0xffffffff, 0x00060005,
604 0x245c, 0xffffffff, 0x00090008,
605 0x245d, 0xffffffff, 0x00020001,
606 0x245e, 0xffffffff, 0x00040003,
607 0x245f, 0xffffffff, 0x00000007,
608 0x2460, 0xffffffff, 0x00060005,
609 0x2461, 0xffffffff, 0x00090008,
610 0x2462, 0xffffffff, 0x00030002,
611 0x2463, 0xffffffff, 0x00050004,
612 0x2464, 0xffffffff, 0x00000008,
613 0x2465, 0xffffffff, 0x00070006,
614 0x2466, 0xffffffff, 0x000a0009,
615 0x2467, 0xffffffff, 0x00040003,
616 0x2468, 0xffffffff, 0x00060005,
617 0x2469, 0xffffffff, 0x00000009,
618 0x246a, 0xffffffff, 0x00080007,
619 0x246b, 0xffffffff, 0x000b000a,
620 0x246c, 0xffffffff, 0x00050004,
621 0x246d, 0xffffffff, 0x00070006,
622 0x246e, 0xffffffff, 0x0008000b,
623 0x246f, 0xffffffff, 0x000a0009,
624 0x2470, 0xffffffff, 0x000d000c,
625 0x2480, 0xffffffff, 0x00090008,
626 0x2481, 0xffffffff, 0x000b000a,
627 0x2482, 0xffffffff, 0x000c000f,
628 0x2483, 0xffffffff, 0x000e000d,
629 0x2484, 0xffffffff, 0x00110010,
630 0x2485, 0xffffffff, 0x000a0009,
631 0x2486, 0xffffffff, 0x000c000b,
632 0x2487, 0xffffffff, 0x0000000f,
633 0x2488, 0xffffffff, 0x000e000d,
634 0x2489, 0xffffffff, 0x00110010,
635 0x248a, 0xffffffff, 0x000b000a,
636 0x248b, 0xffffffff, 0x000d000c,
637 0x248c, 0xffffffff, 0x00000010,
638 0x248d, 0xffffffff, 0x000f000e,
639 0x248e, 0xffffffff, 0x00120011,
640 0x248f, 0xffffffff, 0x000c000b,
641 0x2490, 0xffffffff, 0x000e000d,
642 0x2491, 0xffffffff, 0x00000011,
643 0x2492, 0xffffffff, 0x0010000f,
644 0x2493, 0xffffffff, 0x00130012,
645 0x2494, 0xffffffff, 0x000d000c,
646 0x2495, 0xffffffff, 0x000f000e,
647 0x2496, 0xffffffff, 0x00100013,
648 0x2497, 0xffffffff, 0x00120011,
649 0x2498, 0xffffffff, 0x00150014,
650 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
651 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
652 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
653 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
654 0x000c, 0xffffffff, 0x0000001c,
655 0x000d, 0x000f0000, 0x000f0000,
656 0x0583, 0xffffffff, 0x00000100,
657 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
658 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
659 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
660 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
661 0x157a, 0x00000001, 0x00000001,
662 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
663 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
664 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
665 0x3430, 0xfffffff0, 0x00000100,
666 0x3630, 0xfffffff0, 0x00000100,
667};
668
669static const u32 verde_mgcg_cgcg_init[] =
670{
671 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
672 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
673 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
674 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
675 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
676 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
677 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
678 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
679 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
680 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
681 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
682 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
683 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
684 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
685 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
686 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
687 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
688 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
689 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
690 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
691 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
692 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
693 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
694 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
695 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
696 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
697 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
698 0x2458, 0xffffffff, 0x00010000,
699 0x2459, 0xffffffff, 0x00030002,
700 0x245a, 0xffffffff, 0x00040007,
701 0x245b, 0xffffffff, 0x00060005,
702 0x245c, 0xffffffff, 0x00090008,
703 0x245d, 0xffffffff, 0x00020001,
704 0x245e, 0xffffffff, 0x00040003,
705 0x245f, 0xffffffff, 0x00000007,
706 0x2460, 0xffffffff, 0x00060005,
707 0x2461, 0xffffffff, 0x00090008,
708 0x2462, 0xffffffff, 0x00030002,
709 0x2463, 0xffffffff, 0x00050004,
710 0x2464, 0xffffffff, 0x00000008,
711 0x2465, 0xffffffff, 0x00070006,
712 0x2466, 0xffffffff, 0x000a0009,
713 0x2467, 0xffffffff, 0x00040003,
714 0x2468, 0xffffffff, 0x00060005,
715 0x2469, 0xffffffff, 0x00000009,
716 0x246a, 0xffffffff, 0x00080007,
717 0x246b, 0xffffffff, 0x000b000a,
718 0x246c, 0xffffffff, 0x00050004,
719 0x246d, 0xffffffff, 0x00070006,
720 0x246e, 0xffffffff, 0x0008000b,
721 0x246f, 0xffffffff, 0x000a0009,
722 0x2470, 0xffffffff, 0x000d000c,
723 0x2480, 0xffffffff, 0x00090008,
724 0x2481, 0xffffffff, 0x000b000a,
725 0x2482, 0xffffffff, 0x000c000f,
726 0x2483, 0xffffffff, 0x000e000d,
727 0x2484, 0xffffffff, 0x00110010,
728 0x2485, 0xffffffff, 0x000a0009,
729 0x2486, 0xffffffff, 0x000c000b,
730 0x2487, 0xffffffff, 0x0000000f,
731 0x2488, 0xffffffff, 0x000e000d,
732 0x2489, 0xffffffff, 0x00110010,
733 0x248a, 0xffffffff, 0x000b000a,
734 0x248b, 0xffffffff, 0x000d000c,
735 0x248c, 0xffffffff, 0x00000010,
736 0x248d, 0xffffffff, 0x000f000e,
737 0x248e, 0xffffffff, 0x00120011,
738 0x248f, 0xffffffff, 0x000c000b,
739 0x2490, 0xffffffff, 0x000e000d,
740 0x2491, 0xffffffff, 0x00000011,
741 0x2492, 0xffffffff, 0x0010000f,
742 0x2493, 0xffffffff, 0x00130012,
743 0x2494, 0xffffffff, 0x000d000c,
744 0x2495, 0xffffffff, 0x000f000e,
745 0x2496, 0xffffffff, 0x00100013,
746 0x2497, 0xffffffff, 0x00120011,
747 0x2498, 0xffffffff, 0x00150014,
748 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
749 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
750 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
751 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
752 0x000c, 0xffffffff, 0x0000001c,
753 0x000d, 0x000f0000, 0x000f0000,
754 0x0583, 0xffffffff, 0x00000100,
755 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
756 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
757 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
758 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
759 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
760 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
761 0x157a, 0x00000001, 0x00000001,
762 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
763 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
764 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
765 0x3430, 0xfffffff0, 0x00000100,
766 0x3630, 0xfffffff0, 0x00000100,
767};
768
769static const u32 oland_mgcg_cgcg_init[] =
770{
771 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
772 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
773 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
774 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
775 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
776 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
777 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
778 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
779 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
780 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
781 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
782 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
783 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
784 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
785 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
786 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
787 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
788 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
789 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
790 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
791 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
792 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
793 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
794 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
795 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
796 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
797 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
798 0x2458, 0xffffffff, 0x00010000,
799 0x2459, 0xffffffff, 0x00030002,
800 0x245a, 0xffffffff, 0x00040007,
801 0x245b, 0xffffffff, 0x00060005,
802 0x245c, 0xffffffff, 0x00090008,
803 0x245d, 0xffffffff, 0x00020001,
804 0x245e, 0xffffffff, 0x00040003,
805 0x245f, 0xffffffff, 0x00000007,
806 0x2460, 0xffffffff, 0x00060005,
807 0x2461, 0xffffffff, 0x00090008,
808 0x2462, 0xffffffff, 0x00030002,
809 0x2463, 0xffffffff, 0x00050004,
810 0x2464, 0xffffffff, 0x00000008,
811 0x2465, 0xffffffff, 0x00070006,
812 0x2466, 0xffffffff, 0x000a0009,
813 0x2467, 0xffffffff, 0x00040003,
814 0x2468, 0xffffffff, 0x00060005,
815 0x2469, 0xffffffff, 0x00000009,
816 0x246a, 0xffffffff, 0x00080007,
817 0x246b, 0xffffffff, 0x000b000a,
818 0x246c, 0xffffffff, 0x00050004,
819 0x246d, 0xffffffff, 0x00070006,
820 0x246e, 0xffffffff, 0x0008000b,
821 0x246f, 0xffffffff, 0x000a0009,
822 0x2470, 0xffffffff, 0x000d000c,
823 0x2471, 0xffffffff, 0x00060005,
824 0x2472, 0xffffffff, 0x00080007,
825 0x2473, 0xffffffff, 0x0000000b,
826 0x2474, 0xffffffff, 0x000a0009,
827 0x2475, 0xffffffff, 0x000d000c,
828 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
829 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
830 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
831 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
832 0x000c, 0xffffffff, 0x0000001c,
833 0x000d, 0x000f0000, 0x000f0000,
834 0x0583, 0xffffffff, 0x00000100,
835 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
836 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
837 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
838 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
839 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
840 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
841 0x157a, 0x00000001, 0x00000001,
842 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
843 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
844 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
845 0x3430, 0xfffffff0, 0x00000100,
846 0x3630, 0xfffffff0, 0x00000100,
847};
848
849static const u32 hainan_mgcg_cgcg_init[] =
850{
851 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc,
852 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
853 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
854 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
855 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
856 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
857 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
858 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
859 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
860 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
861 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
862 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
863 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
864 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
865 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
866 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
867 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
868 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
869 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
870 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
871 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
872 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
873 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
874 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
875 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
876 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
877 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
878 0x2458, 0xffffffff, 0x00010000,
879 0x2459, 0xffffffff, 0x00030002,
880 0x245a, 0xffffffff, 0x00040007,
881 0x245b, 0xffffffff, 0x00060005,
882 0x245c, 0xffffffff, 0x00090008,
883 0x245d, 0xffffffff, 0x00020001,
884 0x245e, 0xffffffff, 0x00040003,
885 0x245f, 0xffffffff, 0x00000007,
886 0x2460, 0xffffffff, 0x00060005,
887 0x2461, 0xffffffff, 0x00090008,
888 0x2462, 0xffffffff, 0x00030002,
889 0x2463, 0xffffffff, 0x00050004,
890 0x2464, 0xffffffff, 0x00000008,
891 0x2465, 0xffffffff, 0x00070006,
892 0x2466, 0xffffffff, 0x000a0009,
893 0x2467, 0xffffffff, 0x00040003,
894 0x2468, 0xffffffff, 0x00060005,
895 0x2469, 0xffffffff, 0x00000009,
896 0x246a, 0xffffffff, 0x00080007,
897 0x246b, 0xffffffff, 0x000b000a,
898 0x246c, 0xffffffff, 0x00050004,
899 0x246d, 0xffffffff, 0x00070006,
900 0x246e, 0xffffffff, 0x0008000b,
901 0x246f, 0xffffffff, 0x000a0009,
902 0x2470, 0xffffffff, 0x000d000c,
903 0x2471, 0xffffffff, 0x00060005,
904 0x2472, 0xffffffff, 0x00080007,
905 0x2473, 0xffffffff, 0x0000000b,
906 0x2474, 0xffffffff, 0x000a0009,
907 0x2475, 0xffffffff, 0x000d000c,
908 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
909 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
910 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080,
911 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
912 0x000c, 0xffffffff, 0x0000001c,
913 0x000d, 0x000f0000, 0x000f0000,
914 0x0583, 0xffffffff, 0x00000100,
915 0x0409, 0xffffffff, 0x00000100,
916 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104,
917 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000,
918 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000,
919 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001,
920 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
921 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
922 0x3430, 0xfffffff0, 0x00000100,
923 0x3630, 0xfffffff0, 0x00000100,
924};
925
926/* tahiti, pitcairn, verde */
927static const struct amdgpu_video_codec_info tahiti_video_codecs_encode_array[] =
928{
929 {
930 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
931 .max_width = 2048,
932 .max_height = 1152,
933 .max_pixels_per_frame = 2048 * 1152,
934 .max_level = 0,
935 },
936};
937
938static const struct amdgpu_video_codecs tahiti_video_codecs_encode =
939{
940 .codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array),
941 .codec_array = tahiti_video_codecs_encode_array,
942};
943
944/* oland and hainan don't support encode */
945static const struct amdgpu_video_codecs hainan_video_codecs_encode =
946{
947 .codec_count = 0,
948 .codec_array = NULL,
949};
950
951/* tahiti, pitcairn, verde, oland */
952static const struct amdgpu_video_codec_info tahiti_video_codecs_decode_array[] =
953{
954 {
955 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
956 .max_width = 2048,
957 .max_height = 1152,
958 .max_pixels_per_frame = 2048 * 1152,
959 .max_level = 3,
960 },
961 {
962 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
963 .max_width = 2048,
964 .max_height = 1152,
965 .max_pixels_per_frame = 2048 * 1152,
966 .max_level = 5,
967 },
968 {
969 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
970 .max_width = 2048,
971 .max_height = 1152,
972 .max_pixels_per_frame = 2048 * 1152,
973 .max_level = 41,
974 },
975 {
976 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
977 .max_width = 2048,
978 .max_height = 1152,
979 .max_pixels_per_frame = 2048 * 1152,
980 .max_level = 4,
981 },
982};
983
984static const struct amdgpu_video_codecs tahiti_video_codecs_decode =
985{
986 .codec_count = ARRAY_SIZE(tahiti_video_codecs_decode_array),
987 .codec_array = tahiti_video_codecs_decode_array,
988};
989
990/* hainan doesn't support decode */
991static const struct amdgpu_video_codecs hainan_video_codecs_decode =
992{
993 .codec_count = 0,
994 .codec_array = NULL,
995};
996
997static int si_query_video_codecs(struct amdgpu_device *adev, bool encode,
998 const struct amdgpu_video_codecs **codecs)
999{
1000 switch (adev->asic_type) {
1001 case CHIP_VERDE:
1002 case CHIP_TAHITI:
1003 case CHIP_PITCAIRN:
1004 if (encode)
1005 *codecs = &tahiti_video_codecs_encode;
1006 else
1007 *codecs = &tahiti_video_codecs_decode;
1008 return 0;
1009 case CHIP_OLAND:
1010 if (encode)
1011 *codecs = &hainan_video_codecs_encode;
1012 else
1013 *codecs = &tahiti_video_codecs_decode;
1014 return 0;
1015 case CHIP_HAINAN:
1016 if (encode)
1017 *codecs = &hainan_video_codecs_encode;
1018 else
1019 *codecs = &hainan_video_codecs_decode;
1020 return 0;
1021 default:
1022 return -EINVAL;
1023 }
1024}
1025
1026static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
1027{
1028 unsigned long flags;
1029 u32 r;
1030
1031 spin_lock_irqsave(&adev->reg.pcie.lock, flags);
1032 WREG32(AMDGPU_PCIE_INDEX, reg);
1033 (void)RREG32(AMDGPU_PCIE_INDEX);
1034 r = RREG32(AMDGPU_PCIE_DATA);
1035 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
1036 return r;
1037}
1038
1039static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1040{
1041 unsigned long flags;
1042
1043 spin_lock_irqsave(&adev->reg.pcie.lock, flags);
1044 WREG32(AMDGPU_PCIE_INDEX, reg);
1045 (void)RREG32(AMDGPU_PCIE_INDEX);
1046 WREG32(AMDGPU_PCIE_DATA, v);
1047 (void)RREG32(AMDGPU_PCIE_DATA);
1048 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
1049}
1050
1051static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
1052{
1053 unsigned long flags;
1054 u32 r;
1055
1056 spin_lock_irqsave(&adev->reg.pcie.lock, flags);
1057 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1058 (void)RREG32(PCIE_PORT_INDEX);
1059 r = RREG32(PCIE_PORT_DATA);
1060 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
1061 return r;
1062}
1063
1064static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1065{
1066 unsigned long flags;
1067
1068 spin_lock_irqsave(&adev->reg.pcie.lock, flags);
1069 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1070 (void)RREG32(PCIE_PORT_INDEX);
1071 WREG32(PCIE_PORT_DATA, (v));
1072 (void)RREG32(PCIE_PORT_DATA);
1073 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
1074}
1075
1076static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
1077{
1078 unsigned long flags;
1079 u32 r;
1080
1081 spin_lock_irqsave(&adev->reg.smc.lock, flags);
1082 WREG32(mmSMC_IND_INDEX_0, (reg));
1083 r = RREG32(mmSMC_IND_DATA_0);
1084 spin_unlock_irqrestore(&adev->reg.smc.lock, flags);
1085 return r;
1086}
1087
1088static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1089{
1090 unsigned long flags;
1091
1092 spin_lock_irqsave(&adev->reg.smc.lock, flags);
1093 WREG32(mmSMC_IND_INDEX_0, (reg));
1094 WREG32(mmSMC_IND_DATA_0, (v));
1095 spin_unlock_irqrestore(&adev->reg.smc.lock, flags);
1096}
1097
1098static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
1099{
1100 unsigned long flags;
1101 u32 r;
1102
1103 spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags);
1104 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
1105 r = RREG32(mmUVD_CTX_DATA);
1106 spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags);
1107 return r;
1108}
1109
1110static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1111{
1112 unsigned long flags;
1113
1114 spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags);
1115 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
1116 WREG32(mmUVD_CTX_DATA, (v));
1117 spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags);
1118}
1119
1120static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = {
1121 {mmGRBM_STATUS},
1122 {mmGRBM_STATUS2},
1123 {mmGRBM_STATUS_SE0},
1124 {mmGRBM_STATUS_SE1},
1125 {mmSRBM_STATUS},
1126 {mmSRBM_STATUS2},
1127 {mmDMA_STATUS_REG + DMA0_REGISTER_OFFSET},
1128 {mmDMA_STATUS_REG + DMA1_REGISTER_OFFSET},
1129 {mmCP_STAT},
1130 {mmCP_STALLED_STAT1},
1131 {mmCP_STALLED_STAT2},
1132 {mmCP_STALLED_STAT3},
1133 {mmGB_ADDR_CONFIG},
1134 {mmMC_ARB_RAMCFG},
1135 {mmGB_TILE_MODE0},
1136 {mmGB_TILE_MODE1},
1137 {mmGB_TILE_MODE2},
1138 {mmGB_TILE_MODE3},
1139 {mmGB_TILE_MODE4},
1140 {mmGB_TILE_MODE5},
1141 {mmGB_TILE_MODE6},
1142 {mmGB_TILE_MODE7},
1143 {mmGB_TILE_MODE8},
1144 {mmGB_TILE_MODE9},
1145 {mmGB_TILE_MODE10},
1146 {mmGB_TILE_MODE11},
1147 {mmGB_TILE_MODE12},
1148 {mmGB_TILE_MODE13},
1149 {mmGB_TILE_MODE14},
1150 {mmGB_TILE_MODE15},
1151 {mmGB_TILE_MODE16},
1152 {mmGB_TILE_MODE17},
1153 {mmGB_TILE_MODE18},
1154 {mmGB_TILE_MODE19},
1155 {mmGB_TILE_MODE20},
1156 {mmGB_TILE_MODE21},
1157 {mmGB_TILE_MODE22},
1158 {mmGB_TILE_MODE23},
1159 {mmGB_TILE_MODE24},
1160 {mmGB_TILE_MODE25},
1161 {mmGB_TILE_MODE26},
1162 {mmGB_TILE_MODE27},
1163 {mmGB_TILE_MODE28},
1164 {mmGB_TILE_MODE29},
1165 {mmGB_TILE_MODE30},
1166 {mmGB_TILE_MODE31},
1167 {mmCC_RB_BACKEND_DISABLE, true},
1168 {mmGC_USER_RB_BACKEND_DISABLE, true},
1169 {mmPA_SC_RASTER_CONFIG, true},
1170};
1171
1172static uint32_t si_get_register_value(struct amdgpu_device *adev,
1173 bool indexed, u32 se_num,
1174 u32 sh_num, u32 reg_offset)
1175{
1176 if (indexed) {
1177 uint32_t val;
1178 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
1179 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
1180
1181 switch (reg_offset) {
1182 case mmCC_RB_BACKEND_DISABLE:
1183 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
1184 case mmGC_USER_RB_BACKEND_DISABLE:
1185 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
1186 case mmPA_SC_RASTER_CONFIG:
1187 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
1188 }
1189
1190 mutex_lock(&adev->grbm_idx_mutex);
1191 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1192 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
1193
1194 val = RREG32(reg_offset);
1195
1196 if (se_num != 0xffffffff || sh_num != 0xffffffff)
1197 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1198 mutex_unlock(&adev->grbm_idx_mutex);
1199 return val;
1200 } else {
1201 unsigned idx;
1202
1203 switch (reg_offset) {
1204 case mmGB_ADDR_CONFIG:
1205 return adev->gfx.config.gb_addr_config;
1206 case mmMC_ARB_RAMCFG:
1207 return adev->gfx.config.mc_arb_ramcfg;
1208 case mmGB_TILE_MODE0:
1209 case mmGB_TILE_MODE1:
1210 case mmGB_TILE_MODE2:
1211 case mmGB_TILE_MODE3:
1212 case mmGB_TILE_MODE4:
1213 case mmGB_TILE_MODE5:
1214 case mmGB_TILE_MODE6:
1215 case mmGB_TILE_MODE7:
1216 case mmGB_TILE_MODE8:
1217 case mmGB_TILE_MODE9:
1218 case mmGB_TILE_MODE10:
1219 case mmGB_TILE_MODE11:
1220 case mmGB_TILE_MODE12:
1221 case mmGB_TILE_MODE13:
1222 case mmGB_TILE_MODE14:
1223 case mmGB_TILE_MODE15:
1224 case mmGB_TILE_MODE16:
1225 case mmGB_TILE_MODE17:
1226 case mmGB_TILE_MODE18:
1227 case mmGB_TILE_MODE19:
1228 case mmGB_TILE_MODE20:
1229 case mmGB_TILE_MODE21:
1230 case mmGB_TILE_MODE22:
1231 case mmGB_TILE_MODE23:
1232 case mmGB_TILE_MODE24:
1233 case mmGB_TILE_MODE25:
1234 case mmGB_TILE_MODE26:
1235 case mmGB_TILE_MODE27:
1236 case mmGB_TILE_MODE28:
1237 case mmGB_TILE_MODE29:
1238 case mmGB_TILE_MODE30:
1239 case mmGB_TILE_MODE31:
1240 idx = (reg_offset - mmGB_TILE_MODE0);
1241 return adev->gfx.config.tile_mode_array[idx];
1242 default:
1243 return RREG32(reg_offset);
1244 }
1245 }
1246}
1247static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1248 u32 sh_num, u32 reg_offset, u32 *value)
1249{
1250 uint32_t i;
1251
1252 *value = 0;
1253 for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) {
1254 bool indexed = si_allowed_read_registers[i].grbm_indexed;
1255
1256 if (reg_offset != si_allowed_read_registers[i].reg_offset)
1257 continue;
1258
1259 *value = si_get_register_value(adev, indexed, se_num, sh_num,
1260 reg_offset);
1261 return 0;
1262 }
1263 return -EINVAL;
1264}
1265
1266static bool si_read_disabled_bios(struct amdgpu_device *adev)
1267{
1268 u32 bus_cntl;
1269 u32 d1vga_control = 0;
1270 u32 d2vga_control = 0;
1271 u32 vga_render_control = 0;
1272 u32 rom_cntl;
1273 bool r;
1274
1275 bus_cntl = RREG32(mmBUS_CNTL);
1276 if (adev->mode_info.num_crtc) {
1277 d1vga_control = RREG32(mmD1VGA_CONTROL);
1278 d2vga_control = RREG32(mmD2VGA_CONTROL);
1279 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
1280 }
1281 rom_cntl = RREG32(R600_ROM_CNTL);
1282
1283 /* enable the rom */
1284 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
1285 if (adev->mode_info.num_crtc) {
1286 /* Disable VGA mode */
1287 WREG32(mmD1VGA_CONTROL,
1288 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
1289 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
1290 WREG32(mmD2VGA_CONTROL,
1291 (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
1292 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
1293 WREG32(mmVGA_RENDER_CONTROL,
1294 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
1295 }
1296 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
1297
1298 r = amdgpu_read_bios(adev);
1299
1300 /* restore regs */
1301 WREG32(mmBUS_CNTL, bus_cntl);
1302 if (adev->mode_info.num_crtc) {
1303 WREG32(mmD1VGA_CONTROL, d1vga_control);
1304 WREG32(mmD2VGA_CONTROL, d2vga_control);
1305 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
1306 }
1307 WREG32(R600_ROM_CNTL, rom_cntl);
1308 return r;
1309}
1310
1311#define mmROM_INDEX 0x2A
1312#define mmROM_DATA 0x2B
1313
1314static bool si_read_bios_from_rom(struct amdgpu_device *adev,
1315 u8 *bios, u32 length_bytes)
1316{
1317 u32 *dw_ptr;
1318 u32 i, length_dw;
1319
1320 if (bios == NULL)
1321 return false;
1322 if (length_bytes == 0)
1323 return false;
1324 /* APU vbios image is part of sbios image */
1325 if (adev->flags & AMD_IS_APU)
1326 return false;
1327
1328 dw_ptr = (u32 *)bios;
1329 length_dw = ALIGN(length_bytes, 4) / 4;
1330 /* set rom index to 0 */
1331 WREG32(mmROM_INDEX, 0);
1332 for (i = 0; i < length_dw; i++)
1333 dw_ptr[i] = RREG32(mmROM_DATA);
1334
1335 return true;
1336}
1337
1338static void si_set_clk_bypass_mode(struct amdgpu_device *adev)
1339{
1340 u32 tmp, i;
1341
1342 tmp = RREG32(mmCG_SPLL_FUNC_CNTL);
1343 tmp |= CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
1344 WREG32(mmCG_SPLL_FUNC_CNTL, tmp);
1345
1346 tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);
1347 tmp |= CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK;
1348 WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp);
1349
1350 for (i = 0; i < adev->usec_timeout; i++) {
1351 if (RREG32(mmCG_SPLL_STATUS) & CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK)
1352 break;
1353 udelay(1);
1354 }
1355
1356 tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);
1357 tmp &= ~(CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK |
1358 CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK);
1359 WREG32(mmCG_SPLL_FUNC_CNTL_2, tmp);
1360
1361 tmp = RREG32(MPLL_CNTL_MODE);
1362 tmp &= ~MPLL_MCLK_SEL;
1363 WREG32(MPLL_CNTL_MODE, tmp);
1364}
1365
1366static void si_spll_powerdown(struct amdgpu_device *adev)
1367{
1368 u32 tmp;
1369
1370 tmp = RREG32(mmSPLL_CNTL_MODE);
1371 tmp |= SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK;
1372 WREG32(mmSPLL_CNTL_MODE, tmp);
1373
1374 tmp = RREG32(mmCG_SPLL_FUNC_CNTL);
1375 tmp |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
1376 WREG32(mmCG_SPLL_FUNC_CNTL, tmp);
1377
1378 tmp = RREG32(mmCG_SPLL_FUNC_CNTL);
1379 tmp |= CG_SPLL_FUNC_CNTL__SPLL_SLEEP_MASK;
1380 WREG32(mmCG_SPLL_FUNC_CNTL, tmp);
1381
1382 tmp = RREG32(mmSPLL_CNTL_MODE);
1383 tmp &= ~SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK;
1384 WREG32(mmSPLL_CNTL_MODE, tmp);
1385}
1386
1387static int si_gpu_pci_config_reset(struct amdgpu_device *adev)
1388{
1389 u32 i;
1390 int r = -EINVAL;
1391
1392 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
1393
1394 /* set mclk/sclk to bypass */
1395 si_set_clk_bypass_mode(adev);
1396 /* powerdown spll */
1397 si_spll_powerdown(adev);
1398 /* disable BM */
1399 pci_clear_master(adev->pdev);
1400 /* reset */
1401 amdgpu_device_pci_config_reset(adev);
1402
1403 udelay(100);
1404
1405 /* wait for asic to come out of reset */
1406 for (i = 0; i < adev->usec_timeout; i++) {
1407 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
1408 /* enable BM */
1409 pci_set_master(adev->pdev);
1410 adev->has_hw_reset = true;
1411 r = 0;
1412 break;
1413 }
1414 udelay(1);
1415 }
1416 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
1417
1418 return r;
1419}
1420
1421static int si_asic_supports_baco(struct amdgpu_device *adev)
1422{
1423 return 0;
1424}
1425
1426static enum amd_reset_method
1427si_asic_reset_method(struct amdgpu_device *adev)
1428{
1429 if (amdgpu_reset_method == AMD_RESET_METHOD_PCI)
1430 return amdgpu_reset_method;
1431 else if (amdgpu_reset_method != AMD_RESET_METHOD_LEGACY &&
1432 amdgpu_reset_method != -1)
1433 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
1434 amdgpu_reset_method);
1435
1436 return AMD_RESET_METHOD_LEGACY;
1437}
1438
1439static int si_asic_reset(struct amdgpu_device *adev)
1440{
1441 int r;
1442
1443 switch (si_asic_reset_method(adev)) {
1444 case AMD_RESET_METHOD_PCI:
1445 dev_info(adev->dev, "PCI reset\n");
1446 r = amdgpu_device_pci_reset(adev);
1447 break;
1448 default:
1449 dev_info(adev->dev, "PCI CONFIG reset\n");
1450 r = si_gpu_pci_config_reset(adev);
1451 break;
1452 }
1453
1454 return r;
1455}
1456
1457static u32 si_get_config_memsize(struct amdgpu_device *adev)
1458{
1459 return RREG32(mmCONFIG_MEMSIZE);
1460}
1461
1462static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1463{
1464 uint32_t temp;
1465
1466 temp = RREG32(mmCONFIG_CNTL);
1467 if (!state) {
1468 temp &= ~(1<<0);
1469 temp |= (1<<1);
1470 } else {
1471 temp &= ~(1<<1);
1472 }
1473 WREG32(mmCONFIG_CNTL, temp);
1474}
1475
1476static u32 si_get_xclk(struct amdgpu_device *adev)
1477{
1478 u32 reference_clock = adev->clock.spll.reference_freq;
1479 u32 tmp;
1480
1481 tmp = RREG32(mmCG_CLKPIN_CNTL_2);
1482 if (tmp & CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK)
1483 return TCLK;
1484
1485 tmp = RREG32(mmCG_CLKPIN_CNTL);
1486 if (tmp & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)
1487 return reference_clock / 4;
1488
1489 return reference_clock;
1490}
1491
1492static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1493{
1494 if (!ring || !ring->funcs->emit_wreg) {
1495 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1496 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
1497 } else {
1498 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
1499 }
1500}
1501
1502static void si_invalidate_hdp(struct amdgpu_device *adev,
1503 struct amdgpu_ring *ring)
1504{
1505 if (!ring || !ring->funcs->emit_wreg) {
1506 WREG32(mmHDP_DEBUG0, 1);
1507 RREG32(mmHDP_DEBUG0);
1508 } else {
1509 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
1510 }
1511}
1512
1513static bool si_need_reset_on_init(struct amdgpu_device *adev)
1514{
1515 return false;
1516}
1517
1518static int si_get_pcie_lanes(struct amdgpu_device *adev)
1519{
1520 u32 link_width_cntl;
1521
1522 if (adev->flags & AMD_IS_APU)
1523 return 0;
1524
1525 link_width_cntl = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL);
1526
1527 switch ((link_width_cntl & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT) {
1528 case LC_LINK_WIDTH_X1:
1529 return 1;
1530 case LC_LINK_WIDTH_X2:
1531 return 2;
1532 case LC_LINK_WIDTH_X4:
1533 return 4;
1534 case LC_LINK_WIDTH_X8:
1535 return 8;
1536 case LC_LINK_WIDTH_X0:
1537 case LC_LINK_WIDTH_X16:
1538 default:
1539 return 16;
1540 }
1541}
1542
1543static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes)
1544{
1545 u32 link_width_cntl, mask;
1546
1547 if (adev->flags & AMD_IS_APU)
1548 return;
1549
1550 switch (lanes) {
1551 case 0:
1552 mask = LC_LINK_WIDTH_X0;
1553 break;
1554 case 1:
1555 mask = LC_LINK_WIDTH_X1;
1556 break;
1557 case 2:
1558 mask = LC_LINK_WIDTH_X2;
1559 break;
1560 case 4:
1561 mask = LC_LINK_WIDTH_X4;
1562 break;
1563 case 8:
1564 mask = LC_LINK_WIDTH_X8;
1565 break;
1566 case 16:
1567 mask = LC_LINK_WIDTH_X16;
1568 break;
1569 default:
1570 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
1571 return;
1572 }
1573
1574 link_width_cntl = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL);
1575 link_width_cntl &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK;
1576 link_width_cntl |= mask << PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT;
1577 link_width_cntl |= (PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK |
1578 PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK);
1579
1580 WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1581}
1582
1583static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1584 uint64_t *count1)
1585{
1586 uint32_t perfctr = 0;
1587 uint64_t cnt0_of, cnt1_of;
1588 int tmp;
1589
1590 /* This reports 0 on APUs, so return to avoid writing/reading registers
1591 * that may or may not be different from their GPU counterparts
1592 */
1593 if (adev->flags & AMD_IS_APU)
1594 return;
1595
1596 /* Set the 2 events that we wish to watch, defined above */
1597 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
1598 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1599 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1600
1601 /* Write to enable desired perf counters */
1602 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
1603 /* Zero out and enable the perf counters
1604 * Write 0x5:
1605 * Bit 0 = Start all counters(1)
1606 * Bit 2 = Global counter reset enable(1)
1607 */
1608 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
1609
1610 msleep(1000);
1611
1612 /* Load the shadow and disable the perf counters
1613 * Write 0x2:
1614 * Bit 0 = Stop counters(0)
1615 * Bit 1 = Load the shadow counters(1)
1616 */
1617 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
1618
1619 /* Read register values to get any >32bit overflow */
1620 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
1621 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1622 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1623
1624 /* Get the values and add the overflow */
1625 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1626 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1627}
1628
1629static uint64_t si_get_pcie_replay_count(struct amdgpu_device *adev)
1630{
1631 uint64_t nak_r, nak_g;
1632
1633 /* Get the number of NAKs received and generated */
1634 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
1635 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
1636
1637 /* Add the total number of NAKs, i.e the number of replays */
1638 return (nak_r + nak_g);
1639}
1640
1641static int si_uvd_send_upll_ctlreq(struct amdgpu_device *adev,
1642 unsigned cg_upll_func_cntl)
1643{
1644 unsigned i;
1645
1646 /* Make sure UPLL_CTLREQ is deasserted */
1647 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
1648
1649 mdelay(10);
1650
1651 /* Assert UPLL_CTLREQ */
1652 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
1653
1654 /* Wait for CTLACK and CTLACK2 to get asserted */
1655 for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) {
1656 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
1657
1658 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
1659 break;
1660 mdelay(10);
1661 }
1662
1663 /* Deassert UPLL_CTLREQ */
1664 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
1665
1666 if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) {
1667 DRM_ERROR("Timeout setting UVD clocks!\n");
1668 return -ETIMEDOUT;
1669 }
1670
1671 return 0;
1672}
1673
1674static unsigned si_uvd_calc_upll_post_div(unsigned vco_freq,
1675 unsigned target_freq,
1676 unsigned pd_min,
1677 unsigned pd_even)
1678{
1679 unsigned post_div = vco_freq / target_freq;
1680
1681 /* Adjust to post divider minimum value */
1682 if (post_div < pd_min)
1683 post_div = pd_min;
1684
1685 /* We alway need a frequency less than or equal the target */
1686 if ((vco_freq / post_div) > target_freq)
1687 post_div += 1;
1688
1689 /* Post dividers above a certain value must be even */
1690 if (post_div > pd_even && post_div % 2)
1691 post_div += 1;
1692
1693 return post_div;
1694}
1695
1696/**
1697 * si_calc_upll_dividers - calc UPLL clock dividers
1698 *
1699 * @adev: amdgpu_device pointer
1700 * @vclk: wanted VCLK
1701 * @dclk: wanted DCLK
1702 * @vco_min: minimum VCO frequency
1703 * @vco_max: maximum VCO frequency
1704 * @fb_factor: factor to multiply vco freq with
1705 * @fb_mask: limit and bitmask for feedback divider
1706 * @pd_min: post divider minimum
1707 * @pd_max: post divider maximum
1708 * @pd_even: post divider must be even above this value
1709 * @optimal_fb_div: resulting feedback divider
1710 * @optimal_vclk_div: resulting vclk post divider
1711 * @optimal_dclk_div: resulting dclk post divider
1712 *
1713 * Calculate dividers for UVDs UPLL (except APUs).
1714 * Returns zero on success; -EINVAL on error.
1715 */
1716static int si_calc_upll_dividers(struct amdgpu_device *adev,
1717 unsigned vclk, unsigned dclk,
1718 unsigned vco_min, unsigned vco_max,
1719 unsigned fb_factor, unsigned fb_mask,
1720 unsigned pd_min, unsigned pd_max,
1721 unsigned pd_even,
1722 unsigned *optimal_fb_div,
1723 unsigned *optimal_vclk_div,
1724 unsigned *optimal_dclk_div)
1725{
1726 unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq;
1727
1728 /* Start off with something large */
1729 unsigned optimal_score = ~0;
1730
1731 /* Loop through vco from low to high */
1732 vco_min = max(max(vco_min, vclk), dclk);
1733 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
1734 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
1735 unsigned vclk_div, dclk_div, score;
1736
1737 do_div(fb_div, ref_freq);
1738
1739 /* fb div out of range ? */
1740 if (fb_div > fb_mask)
1741 break; /* It can oly get worse */
1742
1743 fb_div &= fb_mask;
1744
1745 /* Calc vclk divider with current vco freq */
1746 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk,
1747 pd_min, pd_even);
1748 if (vclk_div > pd_max)
1749 break; /* vco is too big, it has to stop */
1750
1751 /* Calc dclk divider with current vco freq */
1752 dclk_div = si_uvd_calc_upll_post_div(vco_freq, dclk,
1753 pd_min, pd_even);
1754 if (dclk_div > pd_max)
1755 break; /* vco is too big, it has to stop */
1756
1757 /* Calc score with current vco freq */
1758 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
1759
1760 /* Determine if this vco setting is better than current optimal settings */
1761 if (score < optimal_score) {
1762 *optimal_fb_div = fb_div;
1763 *optimal_vclk_div = vclk_div;
1764 *optimal_dclk_div = dclk_div;
1765 optimal_score = score;
1766 if (optimal_score == 0)
1767 break; /* It can't get better than this */
1768 }
1769 }
1770
1771 /* Did we found a valid setup ? */
1772 if (optimal_score == ~0)
1773 return -EINVAL;
1774
1775 return 0;
1776}
1777
1778static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1779{
1780 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
1781 int r;
1782
1783 /* Bypass vclk and dclk with bclk */
1784 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1785 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
1786 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
1787
1788 /* Put PLL in bypass mode */
1789 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
1790
1791 if (!vclk || !dclk) {
1792 /* Keep the Bypass mode */
1793 return 0;
1794 }
1795
1796 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000,
1797 16384, 0x03FFFFFF, 0, 128, 5,
1798 &fb_div, &vclk_div, &dclk_div);
1799 if (r)
1800 return r;
1801
1802 /* Set RESET_ANTI_MUX to 0 */
1803 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
1804
1805 /* Set VCO_MODE to 1 */
1806 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
1807
1808 /* Disable sleep mode */
1809 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
1810
1811 /* Deassert UPLL_RESET */
1812 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
1813
1814 mdelay(1);
1815
1816 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);
1817 if (r)
1818 return r;
1819
1820 /* Assert UPLL_RESET again */
1821 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
1822
1823 /* Disable spread spectrum. */
1824 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
1825
1826 /* Set feedback divider */
1827 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
1828
1829 /* Set ref divider to 0 */
1830 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
1831
1832 if (fb_div < 307200)
1833 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
1834 else
1835 WREG32_P(CG_UPLL_FUNC_CNTL_4,
1836 UPLL_SPARE_ISPARE9,
1837 ~UPLL_SPARE_ISPARE9);
1838
1839 /* Set PDIV_A and PDIV_B */
1840 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1841 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
1842 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
1843
1844 /* Give the PLL some time to settle */
1845 mdelay(15);
1846
1847 /* Deassert PLL_RESET */
1848 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
1849
1850 mdelay(15);
1851
1852 /* Switch from bypass mode to normal mode */
1853 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
1854
1855 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);
1856 if (r)
1857 return r;
1858
1859 /* Switch VCLK and DCLK selection */
1860 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1861 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
1862 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
1863
1864 mdelay(100);
1865
1866 return 0;
1867}
1868
1869static int si_vce_send_vcepll_ctlreq(struct amdgpu_device *adev)
1870{
1871 unsigned i;
1872
1873 /* Make sure VCEPLL_CTLREQ is deasserted */
1874 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
1875
1876 mdelay(10);
1877
1878 /* Assert UPLL_CTLREQ */
1879 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
1880
1881 /* Wait for CTLACK and CTLACK2 to get asserted */
1882 for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) {
1883 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
1884
1885 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)
1886 break;
1887 mdelay(10);
1888 }
1889
1890 /* Deassert UPLL_CTLREQ */
1891 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
1892
1893 if (i == SI_MAX_CTLACKS_ASSERTION_WAIT) {
1894 DRM_ERROR("Timeout setting VCE clocks!\n");
1895 return -ETIMEDOUT;
1896 }
1897
1898 return 0;
1899}
1900
1901static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1902{
1903 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0;
1904 int r;
1905
1906 /* Bypass evclk and ecclk with bclk */
1907 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
1908 EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1),
1909 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
1910
1911 /* Put PLL in bypass mode */
1912 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,
1913 ~VCEPLL_BYPASS_EN_MASK);
1914
1915 if (!evclk || !ecclk) {
1916 /*
1917 * On some chips, the PLL takes way too long to get out of
1918 * sleep mode, causing a timeout waiting on CTLACK/CTLACK2.
1919 * Leave the PLL running in bypass mode.
1920 */
1921 if (adev->pdev->device == 0x6780)
1922 return 0;
1923
1924 /* Keep the Bypass mode, put PLL to sleep */
1925 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
1926 ~VCEPLL_SLEEP_MASK);
1927 return 0;
1928 }
1929
1930 r = si_calc_upll_dividers(adev, evclk, ecclk, 125000, 250000,
1931 16384, 0x03FFFFFF, 0, 128, 5,
1932 &fb_div, &evclk_div, &ecclk_div);
1933 if (r)
1934 return r;
1935
1936 /* Set RESET_ANTI_MUX to 0 */
1937 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
1938
1939 /* Set VCO_MODE to 1 */
1940 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,
1941 ~VCEPLL_VCO_MODE_MASK);
1942
1943 /* Toggle VCEPLL_SLEEP to 1 then back to 0 */
1944 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
1945 ~VCEPLL_SLEEP_MASK);
1946 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);
1947
1948 /* Deassert VCEPLL_RESET */
1949 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
1950
1951 mdelay(1);
1952
1953 r = si_vce_send_vcepll_ctlreq(adev);
1954 if (r)
1955 return r;
1956
1957 /* Assert VCEPLL_RESET again */
1958 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);
1959
1960 /* Disable spread spectrum. */
1961 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
1962
1963 /* Set feedback divider */
1964 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3,
1965 VCEPLL_FB_DIV(fb_div),
1966 ~VCEPLL_FB_DIV_MASK);
1967
1968 /* Set ref divider to 0 */
1969 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);
1970
1971 /* Set PDIV_A and PDIV_B */
1972 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
1973 VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div),
1974 ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK));
1975
1976 /* Give the PLL some time to settle */
1977 mdelay(15);
1978
1979 /* Deassert PLL_RESET */
1980 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
1981
1982 mdelay(15);
1983
1984 /* Switch from bypass mode to normal mode */
1985 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);
1986
1987 r = si_vce_send_vcepll_ctlreq(adev);
1988 if (r)
1989 return r;
1990
1991 /* Switch VCLK and DCLK selection */
1992 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
1993 EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16),
1994 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
1995
1996 mdelay(100);
1997
1998 return 0;
1999}
2000
2001static const struct amdgpu_asic_funcs si_asic_funcs =
2002{
2003 .read_disabled_bios = &si_read_disabled_bios,
2004 .read_bios_from_rom = &si_read_bios_from_rom,
2005 .read_register = &si_read_register,
2006 .reset = &si_asic_reset,
2007 .reset_method = &si_asic_reset_method,
2008 .set_vga_state = &si_vga_set_state,
2009 .get_xclk = &si_get_xclk,
2010 .set_uvd_clocks = &si_set_uvd_clocks,
2011 .set_vce_clocks = &si_set_vce_clocks,
2012 .get_pcie_lanes = &si_get_pcie_lanes,
2013 .set_pcie_lanes = &si_set_pcie_lanes,
2014 .get_config_memsize = &si_get_config_memsize,
2015 .flush_hdp = &si_flush_hdp,
2016 .invalidate_hdp = &si_invalidate_hdp,
2017 .get_pcie_usage = &si_get_pcie_usage,
2018 .need_reset_on_init = &si_need_reset_on_init,
2019 .get_pcie_replay_count = &si_get_pcie_replay_count,
2020 .supports_baco = &si_asic_supports_baco,
2021 .query_video_codecs = &si_query_video_codecs,
2022};
2023
2024static uint32_t si_get_rev_id(struct amdgpu_device *adev)
2025{
2026 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
2027 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
2028}
2029
2030static int si_common_early_init(struct amdgpu_ip_block *ip_block)
2031{
2032 struct amdgpu_device *adev = ip_block->adev;
2033
2034 adev->reg.smc.rreg = si_smc_rreg;
2035 adev->reg.smc.wreg = si_smc_wreg;
2036 adev->reg.pcie.rreg = &si_pcie_rreg;
2037 adev->reg.pcie.wreg = &si_pcie_wreg;
2038 adev->reg.pcie.port_rreg = &si_pciep_rreg;
2039 adev->reg.pcie.port_wreg = &si_pciep_wreg;
2040 adev->reg.uvd_ctx.rreg = &si_uvd_ctx_rreg;
2041 adev->reg.uvd_ctx.wreg = &si_uvd_ctx_wreg;
2042
2043 adev->asic_funcs = &si_asic_funcs;
2044
2045 adev->rev_id = si_get_rev_id(adev);
2046 adev->external_rev_id = 0xFF;
2047 switch (adev->asic_type) {
2048 case CHIP_TAHITI:
2049 adev->cg_flags =
2050 AMD_CG_SUPPORT_GFX_MGCG |
2051 AMD_CG_SUPPORT_GFX_MGLS |
2052 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2053 AMD_CG_SUPPORT_GFX_CGLS |
2054 AMD_CG_SUPPORT_GFX_CGTS |
2055 AMD_CG_SUPPORT_GFX_CP_LS |
2056 AMD_CG_SUPPORT_MC_MGCG |
2057 AMD_CG_SUPPORT_SDMA_MGCG |
2058 AMD_CG_SUPPORT_BIF_LS |
2059 AMD_CG_SUPPORT_VCE_MGCG |
2060 AMD_CG_SUPPORT_UVD_MGCG |
2061 AMD_CG_SUPPORT_HDP_LS |
2062 AMD_CG_SUPPORT_HDP_MGCG;
2063 adev->pg_flags = 0;
2064 adev->external_rev_id = (adev->rev_id == 0) ? 1 :
2065 (adev->rev_id == 1) ? 5 : 6;
2066 break;
2067 case CHIP_PITCAIRN:
2068 adev->cg_flags =
2069 AMD_CG_SUPPORT_GFX_MGCG |
2070 AMD_CG_SUPPORT_GFX_MGLS |
2071 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2072 AMD_CG_SUPPORT_GFX_CGLS |
2073 AMD_CG_SUPPORT_GFX_CGTS |
2074 AMD_CG_SUPPORT_GFX_CP_LS |
2075 AMD_CG_SUPPORT_GFX_RLC_LS |
2076 AMD_CG_SUPPORT_MC_LS |
2077 AMD_CG_SUPPORT_MC_MGCG |
2078 AMD_CG_SUPPORT_SDMA_MGCG |
2079 AMD_CG_SUPPORT_BIF_LS |
2080 AMD_CG_SUPPORT_VCE_MGCG |
2081 AMD_CG_SUPPORT_UVD_MGCG |
2082 AMD_CG_SUPPORT_HDP_LS |
2083 AMD_CG_SUPPORT_HDP_MGCG;
2084 adev->pg_flags = 0;
2085 adev->external_rev_id = adev->rev_id + 20;
2086 break;
2087
2088 case CHIP_VERDE:
2089 adev->cg_flags =
2090 AMD_CG_SUPPORT_GFX_MGCG |
2091 AMD_CG_SUPPORT_GFX_MGLS |
2092 AMD_CG_SUPPORT_GFX_CGLS |
2093 AMD_CG_SUPPORT_GFX_CGTS |
2094 AMD_CG_SUPPORT_GFX_CGTS_LS |
2095 AMD_CG_SUPPORT_GFX_CP_LS |
2096 AMD_CG_SUPPORT_MC_LS |
2097 AMD_CG_SUPPORT_MC_MGCG |
2098 AMD_CG_SUPPORT_SDMA_MGCG |
2099 AMD_CG_SUPPORT_SDMA_LS |
2100 AMD_CG_SUPPORT_BIF_LS |
2101 AMD_CG_SUPPORT_VCE_MGCG |
2102 AMD_CG_SUPPORT_UVD_MGCG |
2103 AMD_CG_SUPPORT_HDP_LS |
2104 AMD_CG_SUPPORT_HDP_MGCG;
2105 adev->pg_flags = 0;
2106 //???
2107 adev->external_rev_id = adev->rev_id + 40;
2108 break;
2109 case CHIP_OLAND:
2110 adev->cg_flags =
2111 AMD_CG_SUPPORT_GFX_MGCG |
2112 AMD_CG_SUPPORT_GFX_MGLS |
2113 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2114 AMD_CG_SUPPORT_GFX_CGLS |
2115 AMD_CG_SUPPORT_GFX_CGTS |
2116 AMD_CG_SUPPORT_GFX_CP_LS |
2117 AMD_CG_SUPPORT_GFX_RLC_LS |
2118 AMD_CG_SUPPORT_MC_LS |
2119 AMD_CG_SUPPORT_MC_MGCG |
2120 AMD_CG_SUPPORT_SDMA_MGCG |
2121 AMD_CG_SUPPORT_BIF_LS |
2122 AMD_CG_SUPPORT_UVD_MGCG |
2123 AMD_CG_SUPPORT_HDP_LS |
2124 AMD_CG_SUPPORT_HDP_MGCG;
2125 adev->pg_flags = 0;
2126 adev->external_rev_id = 60;
2127 break;
2128 case CHIP_HAINAN:
2129 adev->cg_flags =
2130 AMD_CG_SUPPORT_GFX_MGCG |
2131 AMD_CG_SUPPORT_GFX_MGLS |
2132 /*AMD_CG_SUPPORT_GFX_CGCG |*/
2133 AMD_CG_SUPPORT_GFX_CGLS |
2134 AMD_CG_SUPPORT_GFX_CGTS |
2135 AMD_CG_SUPPORT_GFX_CP_LS |
2136 AMD_CG_SUPPORT_GFX_RLC_LS |
2137 AMD_CG_SUPPORT_MC_LS |
2138 AMD_CG_SUPPORT_MC_MGCG |
2139 AMD_CG_SUPPORT_SDMA_MGCG |
2140 AMD_CG_SUPPORT_BIF_LS |
2141 AMD_CG_SUPPORT_HDP_LS |
2142 AMD_CG_SUPPORT_HDP_MGCG;
2143 adev->pg_flags = 0;
2144 adev->external_rev_id = 70;
2145 break;
2146
2147 default:
2148 return -EINVAL;
2149 }
2150
2151 return 0;
2152}
2153
2154static void si_init_golden_registers(struct amdgpu_device *adev)
2155{
2156 switch (adev->asic_type) {
2157 case CHIP_TAHITI:
2158 amdgpu_device_program_register_sequence(adev,
2159 tahiti_golden_registers,
2160 ARRAY_SIZE(tahiti_golden_registers));
2161 amdgpu_device_program_register_sequence(adev,
2162 tahiti_golden_rlc_registers,
2163 ARRAY_SIZE(tahiti_golden_rlc_registers));
2164 amdgpu_device_program_register_sequence(adev,
2165 tahiti_mgcg_cgcg_init,
2166 ARRAY_SIZE(tahiti_mgcg_cgcg_init));
2167 amdgpu_device_program_register_sequence(adev,
2168 tahiti_golden_registers2,
2169 ARRAY_SIZE(tahiti_golden_registers2));
2170 break;
2171 case CHIP_PITCAIRN:
2172 amdgpu_device_program_register_sequence(adev,
2173 pitcairn_golden_registers,
2174 ARRAY_SIZE(pitcairn_golden_registers));
2175 amdgpu_device_program_register_sequence(adev,
2176 pitcairn_golden_rlc_registers,
2177 ARRAY_SIZE(pitcairn_golden_rlc_registers));
2178 amdgpu_device_program_register_sequence(adev,
2179 pitcairn_mgcg_cgcg_init,
2180 ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
2181 break;
2182 case CHIP_VERDE:
2183 amdgpu_device_program_register_sequence(adev,
2184 verde_golden_registers,
2185 ARRAY_SIZE(verde_golden_registers));
2186 amdgpu_device_program_register_sequence(adev,
2187 verde_golden_rlc_registers,
2188 ARRAY_SIZE(verde_golden_rlc_registers));
2189 amdgpu_device_program_register_sequence(adev,
2190 verde_mgcg_cgcg_init,
2191 ARRAY_SIZE(verde_mgcg_cgcg_init));
2192 amdgpu_device_program_register_sequence(adev,
2193 verde_pg_init,
2194 ARRAY_SIZE(verde_pg_init));
2195 break;
2196 case CHIP_OLAND:
2197 amdgpu_device_program_register_sequence(adev,
2198 oland_golden_registers,
2199 ARRAY_SIZE(oland_golden_registers));
2200 amdgpu_device_program_register_sequence(adev,
2201 oland_golden_rlc_registers,
2202 ARRAY_SIZE(oland_golden_rlc_registers));
2203 amdgpu_device_program_register_sequence(adev,
2204 oland_mgcg_cgcg_init,
2205 ARRAY_SIZE(oland_mgcg_cgcg_init));
2206 break;
2207 case CHIP_HAINAN:
2208 amdgpu_device_program_register_sequence(adev,
2209 hainan_golden_registers,
2210 ARRAY_SIZE(hainan_golden_registers));
2211 amdgpu_device_program_register_sequence(adev,
2212 hainan_golden_registers2,
2213 ARRAY_SIZE(hainan_golden_registers2));
2214 amdgpu_device_program_register_sequence(adev,
2215 hainan_mgcg_cgcg_init,
2216 ARRAY_SIZE(hainan_mgcg_cgcg_init));
2217 break;
2218
2219
2220 default:
2221 break;
2222 }
2223}
2224
2225static void si_pcie_gen3_enable(struct amdgpu_device *adev)
2226{
2227 struct pci_dev *root = adev->pdev->bus->self;
2228 u32 speed_cntl, current_data_rate;
2229 int i;
2230 u16 tmp16;
2231
2232 if (pci_is_root_bus(adev->pdev->bus))
2233 return;
2234
2235 if (amdgpu_pcie_gen2 == 0)
2236 return;
2237
2238 if (adev->flags & AMD_IS_APU)
2239 return;
2240
2241 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2242 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
2243 return;
2244
2245 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL);
2246 current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >>
2247 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2248 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
2249 if (current_data_rate == 2) {
2250 drm_info(adev_to_drm(adev), "PCIE gen 3 link speeds already enabled\n");
2251 return;
2252 }
2253 drm_info(adev_to_drm(adev), "enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
2254 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
2255 if (current_data_rate == 1) {
2256 drm_info(adev_to_drm(adev), "PCIE gen 2 link speeds already enabled\n");
2257 return;
2258 }
2259 drm_info(adev_to_drm(adev), "enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
2260 }
2261
2262 if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))
2263 return;
2264
2265 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
2266 if (current_data_rate != 2) {
2267 u16 bridge_cfg, gpu_cfg;
2268 u16 bridge_cfg2, gpu_cfg2;
2269 u32 max_lw, current_lw, tmp;
2270
2271 pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
2272 pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
2273
2274 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
2275 max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT;
2276 current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK) >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT;
2277
2278 if (current_lw < max_lw) {
2279 tmp = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL);
2280 if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {
2281 tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK);
2282 tmp |= (max_lw << PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT);
2283 tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK | PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK;
2284 WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);
2285 }
2286 }
2287
2288 for (i = 0; i < 10; i++) {
2289 pcie_capability_read_word(adev->pdev,
2290 PCI_EXP_DEVSTA,
2291 &tmp16);
2292 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
2293 break;
2294
2295 pcie_capability_read_word(root, PCI_EXP_LNKCTL,
2296 &bridge_cfg);
2297 pcie_capability_read_word(adev->pdev,
2298 PCI_EXP_LNKCTL,
2299 &gpu_cfg);
2300
2301 pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
2302 &bridge_cfg2);
2303 pcie_capability_read_word(adev->pdev,
2304 PCI_EXP_LNKCTL2,
2305 &gpu_cfg2);
2306
2307 tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4);
2308 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
2309 WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp);
2310
2311 tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4);
2312 tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;
2313 WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp);
2314
2315 mdelay(100);
2316
2317 pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,
2318 PCI_EXP_LNKCTL_HAWD,
2319 bridge_cfg &
2320 PCI_EXP_LNKCTL_HAWD);
2321 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,
2322 PCI_EXP_LNKCTL_HAWD,
2323 gpu_cfg &
2324 PCI_EXP_LNKCTL_HAWD);
2325
2326 pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2,
2327 PCI_EXP_LNKCTL2_ENTER_COMP |
2328 PCI_EXP_LNKCTL2_TX_MARGIN,
2329 bridge_cfg2 &
2330 (PCI_EXP_LNKCTL2_ENTER_COMP |
2331 PCI_EXP_LNKCTL2_TX_MARGIN));
2332 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,
2333 PCI_EXP_LNKCTL2_ENTER_COMP |
2334 PCI_EXP_LNKCTL2_TX_MARGIN,
2335 gpu_cfg2 &
2336 (PCI_EXP_LNKCTL2_ENTER_COMP |
2337 PCI_EXP_LNKCTL2_TX_MARGIN));
2338
2339 tmp = RREG32_PCIE_PORT(ixPCIE_LC_CNTL4);
2340 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
2341 WREG32_PCIE_PORT(ixPCIE_LC_CNTL4, tmp);
2342 }
2343 }
2344 }
2345
2346 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK;
2347 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;
2348 WREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL, speed_cntl);
2349
2350 tmp16 = 0;
2351 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2352 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
2353 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
2354 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
2355 else
2356 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
2357 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,
2358 PCI_EXP_LNKCTL2_TLS, tmp16);
2359
2360 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL);
2361 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;
2362 WREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL, speed_cntl);
2363
2364 for (i = 0; i < adev->usec_timeout; i++) {
2365 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL);
2366 if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0)
2367 break;
2368 udelay(1);
2369 }
2370}
2371
2372static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
2373{
2374 unsigned long flags;
2375 u32 r;
2376
2377 spin_lock_irqsave(&adev->reg.pcie.lock, flags);
2378 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2379 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2380 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
2381 return r;
2382}
2383
2384static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
2385{
2386 unsigned long flags;
2387
2388 spin_lock_irqsave(&adev->reg.pcie.lock, flags);
2389 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2390 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2391 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
2392}
2393
2394static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
2395{
2396 unsigned long flags;
2397 u32 r;
2398
2399 spin_lock_irqsave(&adev->reg.pcie.lock, flags);
2400 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2401 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2402 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
2403 return r;
2404}
2405
2406static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
2407{
2408 unsigned long flags;
2409
2410 spin_lock_irqsave(&adev->reg.pcie.lock, flags);
2411 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2412 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2413 spin_unlock_irqrestore(&adev->reg.pcie.lock, flags);
2414}
2415static void si_program_aspm(struct amdgpu_device *adev)
2416{
2417 u32 data, orig;
2418 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
2419 bool disable_clkreq = false;
2420
2421 if (!amdgpu_device_should_use_aspm(adev))
2422 return;
2423
2424 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_N_FTS_CNTL);
2425 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
2426 data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) | PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;
2427 if (orig != data)
2428 WREG32_PCIE_PORT(ixPCIE_LC_N_FTS_CNTL, data);
2429
2430 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL3);
2431 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
2432 if (orig != data)
2433 WREG32_PCIE_PORT(ixPCIE_LC_CNTL3, data);
2434
2435 orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
2436 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
2437 if (orig != data)
2438 WREG32_PCIE(ixPCIE_P_CNTL, data);
2439
2440 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL);
2441 data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
2442 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
2443 if (!disable_l0s)
2444 data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT);
2445
2446 if (!disable_l1) {
2447 data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT);
2448 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
2449 if (orig != data)
2450 WREG32_PCIE_PORT(ixPCIE_LC_CNTL, data);
2451
2452 if (!disable_plloff_in_l1) {
2453 bool clk_req_support;
2454
2455 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_0);
2456 data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
2457 data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
2458 if (orig != data)
2459 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_0, data);
2460
2461 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_1);
2462 data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
2463 data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
2464 if (orig != data)
2465 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_1, data);
2466
2467 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_0);
2468 data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
2469 data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
2470 if (orig != data)
2471 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_0, data);
2472
2473 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_1);
2474 data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
2475 data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
2476 if (orig != data)
2477 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_1, data);
2478
2479 if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) {
2480 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_0);
2481 data &= ~PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK;
2482 if (orig != data)
2483 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_0, data);
2484
2485 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_1);
2486 data &= ~PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK;
2487 if (orig != data)
2488 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_1, data);
2489
2490 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_2);
2491 data &= ~PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK;
2492 if (orig != data)
2493 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_2, data);
2494
2495 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_PWRDOWN_3);
2496 data &= ~PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK;
2497 if (orig != data)
2498 si_pif_phy0_wreg(adev,ixPB0_PIF_PWRDOWN_3, data);
2499
2500 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_0);
2501 data &= ~PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK;
2502 if (orig != data)
2503 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_0, data);
2504
2505 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_1);
2506 data &= ~PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK;
2507 if (orig != data)
2508 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_1, data);
2509
2510 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_2);
2511 data &= ~PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK;
2512 if (orig != data)
2513 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_2, data);
2514
2515 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_PWRDOWN_3);
2516 data &= ~PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK;
2517 if (orig != data)
2518 si_pif_phy1_wreg(adev,ixPB1_PIF_PWRDOWN_3, data);
2519 }
2520 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL);
2521 data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
2522 data |= (3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT);
2523 if (orig != data)
2524 WREG32_PCIE_PORT(ixPCIE_LC_LINK_WIDTH_CNTL, data);
2525
2526 orig = data = si_pif_phy0_rreg(adev,ixPB0_PIF_CNTL);
2527 data &= ~PB0_PIF_CNTL__LS2_EXIT_TIME_MASK;
2528 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
2529 data |= (5 << PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT);
2530 if (orig != data)
2531 si_pif_phy0_wreg(adev,ixPB0_PIF_CNTL, data);
2532
2533 orig = data = si_pif_phy1_rreg(adev,ixPB1_PIF_CNTL);
2534 data &= ~PB1_PIF_CNTL__LS2_EXIT_TIME_MASK;
2535 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
2536 data |= (5 << PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT);
2537 if (orig != data)
2538 si_pif_phy1_wreg(adev,ixPB1_PIF_CNTL, data);
2539
2540 if (!disable_clkreq &&
2541 !pci_is_root_bus(adev->pdev->bus)) {
2542 struct pci_dev *root = adev->pdev->bus->self;
2543 u32 lnkcap;
2544
2545 clk_req_support = false;
2546 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
2547 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
2548 clk_req_support = true;
2549 } else {
2550 clk_req_support = false;
2551 }
2552
2553 if (clk_req_support) {
2554 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL2);
2555 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
2556 if (orig != data)
2557 WREG32_PCIE_PORT(ixPCIE_LC_CNTL2, data);
2558
2559 orig = data = RREG32(mmTHM_CLK_CNTL);
2560 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | THM_CLK_CNTL__TMON_CLK_SEL_MASK);
2561 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT);
2562 if (orig != data)
2563 WREG32(mmTHM_CLK_CNTL, data);
2564
2565 orig = data = RREG32(mmMISC_CLK_CNTL);
2566 data &= ~(MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK | MISC_CLK_CNTL__ZCLK_SEL_MASK);
2567 data |= (1 << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT) | (1 << MISC_CLK_CNTL__ZCLK_SEL__SHIFT);
2568 if (orig != data)
2569 WREG32(mmMISC_CLK_CNTL, data);
2570
2571 orig = data = RREG32(mmCG_CLKPIN_CNTL);
2572 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK;
2573 if (orig != data)
2574 WREG32(mmCG_CLKPIN_CNTL, data);
2575
2576 orig = data = RREG32(mmCG_CLKPIN_CNTL_2);
2577 data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK;
2578 if (orig != data)
2579 WREG32(mmCG_CLKPIN_CNTL_2, data);
2580
2581 orig = data = RREG32(mmMPLL_BYPASSCLK_SEL);
2582 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;
2583 data |= 4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT;
2584 if (orig != data)
2585 WREG32(mmMPLL_BYPASSCLK_SEL, data);
2586
2587 orig = data = RREG32(mmSPLL_CNTL_MODE);
2588 data &= ~SPLL_CNTL_MODE__SPLL_REFCLK_SEL_MASK;
2589 if (orig != data)
2590 WREG32(mmSPLL_CNTL_MODE, data);
2591 }
2592 }
2593 } else {
2594 if (orig != data)
2595 WREG32_PCIE_PORT(ixPCIE_LC_CNTL, data);
2596 }
2597
2598 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
2599 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | PCIE_CNTL2__MST_MEM_LS_EN_MASK | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
2600 if (orig != data)
2601 WREG32_PCIE(ixPCIE_CNTL2, data);
2602
2603 if (!disable_l0s) {
2604 data = RREG32_PCIE_PORT(ixPCIE_LC_N_FTS_CNTL);
2605 if((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) {
2606 data = RREG32_PCIE(ixPCIE_LC_STATUS1);
2607 if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) && (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) {
2608 orig = data = RREG32_PCIE_PORT(ixPCIE_LC_CNTL);
2609 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
2610 if (orig != data)
2611 WREG32_PCIE_PORT(ixPCIE_LC_CNTL, data);
2612 }
2613 }
2614 }
2615}
2616
2617static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
2618{
2619 int readrq;
2620 u16 v;
2621
2622 readrq = pcie_get_readrq(adev->pdev);
2623 v = ffs(readrq) - 8;
2624 if ((v == 0) || (v == 6) || (v == 7))
2625 pcie_set_readrq(adev->pdev, 512);
2626}
2627
2628static int si_common_hw_init(struct amdgpu_ip_block *ip_block)
2629{
2630 struct amdgpu_device *adev = ip_block->adev;
2631
2632 si_fix_pci_max_read_req_size(adev);
2633 si_init_golden_registers(adev);
2634 si_pcie_gen3_enable(adev);
2635 si_program_aspm(adev);
2636
2637 return 0;
2638}
2639
2640static int si_common_hw_fini(struct amdgpu_ip_block *ip_block)
2641{
2642 return 0;
2643}
2644
2645static int si_common_resume(struct amdgpu_ip_block *ip_block)
2646{
2647 return si_common_hw_init(ip_block);
2648}
2649
2650static bool si_common_is_idle(struct amdgpu_ip_block *ip_block)
2651{
2652 return true;
2653}
2654
2655static int si_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2656 enum amd_clockgating_state state)
2657{
2658 return 0;
2659}
2660
2661static int si_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
2662 enum amd_powergating_state state)
2663{
2664 return 0;
2665}
2666
2667static const struct amd_ip_funcs si_common_ip_funcs = {
2668 .name = "si_common",
2669 .early_init = si_common_early_init,
2670 .hw_init = si_common_hw_init,
2671 .hw_fini = si_common_hw_fini,
2672 .resume = si_common_resume,
2673 .is_idle = si_common_is_idle,
2674 .set_clockgating_state = si_common_set_clockgating_state,
2675 .set_powergating_state = si_common_set_powergating_state,
2676};
2677
2678static const struct amdgpu_ip_block_version si_common_ip_block =
2679{
2680 .type = AMD_IP_BLOCK_TYPE_COMMON,
2681 .major = 1,
2682 .minor = 0,
2683 .rev = 0,
2684 .funcs = &si_common_ip_funcs,
2685};
2686
2687int si_set_ip_blocks(struct amdgpu_device *adev)
2688{
2689 switch (adev->asic_type) {
2690 case CHIP_VERDE:
2691 case CHIP_TAHITI:
2692 case CHIP_PITCAIRN:
2693 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2694 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2695 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
2696 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2697 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2698 amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2699 if (adev->enable_virtual_display)
2700 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2701#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
2702 else if (amdgpu_device_has_dc_support(adev))
2703 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2704#endif
2705 else
2706 amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
2707 amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
2708 amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block);
2709 break;
2710 case CHIP_OLAND:
2711 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2712 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2713 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
2714 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2715 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2716 amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2717 if (adev->enable_virtual_display)
2718 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2719#if defined(CONFIG_DRM_AMD_DC) && defined(CONFIG_DRM_AMD_DC_SI)
2720 else if (amdgpu_device_has_dc_support(adev))
2721 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2722#endif
2723 else
2724 amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
2725 amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
2726 break;
2727 case CHIP_HAINAN:
2728 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2729 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2730 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
2731 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2732 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2733 amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2734 if (adev->enable_virtual_display)
2735 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2736 break;
2737 default:
2738 break;
2739 }
2740 return 0;
2741}
2742