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1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "amdgpu_smu.h"
36#include "amdgpu_video_codecs.h"
37#include "atom.h"
38#include "amd_pcie.h"
39
40#include "gc/gc_11_0_0_offset.h"
41#include "gc/gc_11_0_0_sh_mask.h"
42#include "mp/mp_13_0_0_offset.h"
43
44#include "soc15.h"
45#include "soc15_common.h"
46#include "soc21.h"
47#include "mxgpu_nv.h"
48
49static const struct amd_ip_funcs soc21_common_ip_funcs;
50
51/* SOC21 */
52static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
55 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
56};
57
58static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
60 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
61};
62
63static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
64 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
65 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
66};
67
68static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {
69 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
70 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
71};
72
73static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
78 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
79};
80
81static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
86};
87
88static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {
89 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
90 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
91};
92
93static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
94 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
95 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
96};
97
98/* SRIOV SOC21, not const since data is controlled by host */
99static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
102 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
103};
104
105static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
108};
109
110static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
111 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
112 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
113};
114
115static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
116 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
117 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
118};
119
120static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
126};
127
128static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
133};
134
135static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
136 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
137 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
138};
139
140static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
141 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
142 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
143};
144
145static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = {
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)},
147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
148 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
149};
150
151static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = {
152 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0),
153 .codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0,
154};
155
156static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = {
157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
162};
163
164static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = {
165 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0),
166 .codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0,
167};
168
169
170static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
171 const struct amdgpu_video_codecs **codecs)
172{
173 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
174 return -EINVAL;
175
176 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
177 case IP_VERSION(4, 0, 0):
178 case IP_VERSION(4, 0, 2):
179 case IP_VERSION(4, 0, 4):
180 case IP_VERSION(4, 0, 5):
181 if (amdgpu_sriov_vf(adev)) {
182 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
183 !amdgpu_sriov_is_av1_support(adev)) {
184 if (encode)
185 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
186 else
187 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
188 } else {
189 if (encode)
190 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
191 else
192 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
193 }
194 } else {
195 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
196 if (encode)
197 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
198 else
199 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
200 } else {
201 if (encode)
202 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
203 else
204 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
205 }
206 }
207 return 0;
208 case IP_VERSION(4, 0, 6):
209 if (encode)
210 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
211 else
212 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
213 return 0;
214 case IP_VERSION(5, 3, 0):
215 if (encode)
216 *codecs = &vcn_5_3_0_video_codecs_encode_vcn0;
217 else
218 *codecs = &vcn_5_3_0_video_codecs_decode_vcn0;
219 return 0;
220 default:
221 return -EINVAL;
222 }
223}
224
225static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
226{
227 unsigned long flags, address, data;
228 u32 r;
229
230 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
231 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
232
233 spin_lock_irqsave(&adev->reg.didt.lock, flags);
234 WREG32(address, (reg));
235 r = RREG32(data);
236 spin_unlock_irqrestore(&adev->reg.didt.lock, flags);
237 return r;
238}
239
240static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
241{
242 unsigned long flags, address, data;
243
244 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
245 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
246
247 spin_lock_irqsave(&adev->reg.didt.lock, flags);
248 WREG32(address, (reg));
249 WREG32(data, (v));
250 spin_unlock_irqrestore(&adev->reg.didt.lock, flags);
251}
252
253static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
254{
255 return adev->nbio.funcs->get_memsize(adev);
256}
257
258static u32 soc21_get_xclk(struct amdgpu_device *adev)
259{
260 u32 reference_clock = adev->clock.spll.reference_freq;
261
262 /* reference clock is actually 99.81 Mhz rather than 100 Mhz */
263 if ((adev->flags & AMD_IS_APU) && reference_clock == 10000)
264 return 9981;
265
266 return reference_clock;
267}
268
269
270void soc21_grbm_select(struct amdgpu_device *adev,
271 u32 me, u32 pipe, u32 queue, u32 vmid)
272{
273 u32 grbm_gfx_cntl = 0;
274 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
275 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
276 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
277 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
278
279 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
280}
281
282static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
283{
284 /* todo */
285 return false;
286}
287
288static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
289 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
290 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
291 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
292 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
293 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
294 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
295 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
296 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
297 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
298 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
299 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
300 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
301 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
302 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
303 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
304 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
305 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
306 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
307 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
308};
309
310static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
311 bool indexed, u32 se_num,
312 u32 sh_num, u32 reg_offset)
313{
314 if (indexed) {
315 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset);
316 } else {
317 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
318 return adev->gfx.config.gb_addr_config;
319 return RREG32(reg_offset);
320 }
321}
322
323static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
324 u32 sh_num, u32 reg_offset, u32 *value)
325{
326 uint32_t i;
327 struct soc15_allowed_register_entry *en;
328
329 *value = 0;
330 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
331 en = &soc21_allowed_read_registers[i];
332 if (!adev->reg_offset[en->hwip][en->inst])
333 continue;
334 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
335 + en->reg_offset))
336 continue;
337
338 *value = soc21_get_register_value(adev,
339 soc21_allowed_read_registers[i].grbm_indexed,
340 se_num, sh_num, reg_offset);
341 return 0;
342 }
343 return -EINVAL;
344}
345
346#if 0
347static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
348{
349 u32 i;
350 int ret = 0;
351
352 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
353
354 /* disable BM */
355 pci_clear_master(adev->pdev);
356
357 amdgpu_device_cache_pci_state(adev->pdev);
358
359 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
360 dev_info(adev->dev, "GPU smu mode1 reset\n");
361 ret = amdgpu_dpm_mode1_reset(adev);
362 } else {
363 dev_info(adev->dev, "GPU psp mode1 reset\n");
364 ret = psp_gpu_reset(adev);
365 }
366
367 if (ret)
368 dev_err(adev->dev, "GPU mode1 reset failed\n");
369 amdgpu_device_load_pci_state(adev->pdev);
370
371 /* wait for asic to come out of reset */
372 for (i = 0; i < adev->usec_timeout; i++) {
373 u32 memsize = adev->nbio.funcs->get_memsize(adev);
374
375 if (memsize != 0xffffffff)
376 break;
377 udelay(1);
378 }
379
380 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
381
382 return ret;
383}
384#endif
385
386static enum amd_reset_method
387soc21_asic_reset_method(struct amdgpu_device *adev)
388{
389 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
390 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
391 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
392 return amdgpu_reset_method;
393
394 if (amdgpu_reset_method != -1)
395 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
396 amdgpu_reset_method);
397
398 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
399 case IP_VERSION(13, 0, 0):
400 case IP_VERSION(13, 0, 7):
401 case IP_VERSION(13, 0, 10):
402 return AMD_RESET_METHOD_MODE1;
403 case IP_VERSION(13, 0, 4):
404 case IP_VERSION(13, 0, 11):
405 case IP_VERSION(14, 0, 0):
406 case IP_VERSION(14, 0, 1):
407 case IP_VERSION(14, 0, 4):
408 case IP_VERSION(14, 0, 5):
409 case IP_VERSION(15, 0, 0):
410 case IP_VERSION(15, 0, 5):
411 case IP_VERSION(15, 0, 9):
412 return AMD_RESET_METHOD_MODE2;
413 default:
414 if (amdgpu_dpm_is_baco_supported(adev))
415 return AMD_RESET_METHOD_BACO;
416 else
417 return AMD_RESET_METHOD_MODE1;
418 }
419}
420
421static int soc21_asic_reset(struct amdgpu_device *adev)
422{
423 int ret = 0;
424
425 switch (soc21_asic_reset_method(adev)) {
426 case AMD_RESET_METHOD_PCI:
427 dev_info(adev->dev, "PCI reset\n");
428 ret = amdgpu_device_pci_reset(adev);
429 break;
430 case AMD_RESET_METHOD_BACO:
431 dev_info(adev->dev, "BACO reset\n");
432 ret = amdgpu_dpm_baco_reset(adev);
433 break;
434 case AMD_RESET_METHOD_MODE2:
435 dev_info(adev->dev, "MODE2 reset\n");
436 ret = amdgpu_dpm_mode2_reset(adev);
437 break;
438 default:
439 dev_info(adev->dev, "MODE1 reset\n");
440 ret = amdgpu_device_mode1_reset(adev);
441 break;
442 }
443
444 return ret;
445}
446
447static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
448{
449 /* todo */
450 return 0;
451}
452
453static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
454{
455 /* todo */
456 return 0;
457}
458
459const struct amdgpu_ip_block_version soc21_common_ip_block = {
460 .type = AMD_IP_BLOCK_TYPE_COMMON,
461 .major = 1,
462 .minor = 0,
463 .rev = 0,
464 .funcs = &soc21_common_ip_funcs,
465};
466
467static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
468{
469 u32 sol_reg;
470
471 if (adev->flags & AMD_IS_APU)
472 return false;
473
474 /* Check sOS sign of life register to confirm sys driver and sOS
475 * are already been loaded.
476 */
477 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
478 if (sol_reg)
479 return true;
480
481 return false;
482}
483
484static void soc21_init_doorbell_index(struct amdgpu_device *adev)
485{
486 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
487 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
488 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
489 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
490 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
491 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
492 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
493 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
494 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
495 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
496 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
497 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
498 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
499 adev->doorbell_index.gfx_userqueue_start =
500 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
501 adev->doorbell_index.gfx_userqueue_end =
502 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
503 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
504 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
505 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
506 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
507 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
508 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
509 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
510 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
511 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
512 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE;
513 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
514 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
515
516 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
517 adev->doorbell_index.sdma_doorbell_range = 20;
518}
519
520static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
521 bool enter)
522{
523 if (enter)
524 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
525 else
526 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
527
528 if (adev->gfx.funcs->update_perfmon_mgcg)
529 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
530
531 return 0;
532}
533
534static const struct amdgpu_asic_funcs soc21_asic_funcs = {
535 .read_disabled_bios = &soc21_read_disabled_bios,
536 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
537 .read_register = &soc21_read_register,
538 .reset = &soc21_asic_reset,
539 .reset_method = &soc21_asic_reset_method,
540 .get_xclk = &soc21_get_xclk,
541 .set_uvd_clocks = &soc21_set_uvd_clocks,
542 .set_vce_clocks = &soc21_set_vce_clocks,
543 .get_config_memsize = &soc21_get_config_memsize,
544 .init_doorbell_index = &soc21_init_doorbell_index,
545 .need_reset_on_init = &soc21_need_reset_on_init,
546 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
547 .supports_baco = &amdgpu_dpm_is_baco_supported,
548 .query_video_codecs = &soc21_query_video_codecs,
549 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
550};
551
552static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
553{
554 struct amdgpu_device *adev = ip_block->adev;
555
556 adev->nbio.funcs->set_reg_remap(adev);
557 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg;
558 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg;
559 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64;
560 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64;
561 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg;
562 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg;
563
564 adev->reg.didt.rreg = &soc21_didt_rreg;
565 adev->reg.didt.wreg = &soc21_didt_wreg;
566
567 adev->asic_funcs = &soc21_asic_funcs;
568
569 adev->rev_id = amdgpu_device_get_rev_id(adev);
570 adev->external_rev_id = 0xff;
571 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
572 case IP_VERSION(11, 0, 0):
573 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
574 AMD_CG_SUPPORT_GFX_CGLS |
575#if 0
576 AMD_CG_SUPPORT_GFX_3D_CGCG |
577 AMD_CG_SUPPORT_GFX_3D_CGLS |
578#endif
579 AMD_CG_SUPPORT_GFX_MGCG |
580 AMD_CG_SUPPORT_REPEATER_FGCG |
581 AMD_CG_SUPPORT_GFX_FGCG |
582 AMD_CG_SUPPORT_GFX_PERF_CLK |
583 AMD_CG_SUPPORT_VCN_MGCG |
584 AMD_CG_SUPPORT_JPEG_MGCG |
585 AMD_CG_SUPPORT_ATHUB_MGCG |
586 AMD_CG_SUPPORT_ATHUB_LS |
587 AMD_CG_SUPPORT_MC_MGCG |
588 AMD_CG_SUPPORT_MC_LS |
589 AMD_CG_SUPPORT_IH_CG |
590 AMD_CG_SUPPORT_HDP_SD;
591 adev->pg_flags = AMD_PG_SUPPORT_VCN |
592 AMD_PG_SUPPORT_VCN_DPG |
593 AMD_PG_SUPPORT_JPEG |
594 AMD_PG_SUPPORT_ATHUB |
595 AMD_PG_SUPPORT_MMHUB;
596 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
597 break;
598 case IP_VERSION(11, 0, 2):
599 adev->cg_flags =
600 AMD_CG_SUPPORT_GFX_CGCG |
601 AMD_CG_SUPPORT_GFX_CGLS |
602 AMD_CG_SUPPORT_REPEATER_FGCG |
603 AMD_CG_SUPPORT_VCN_MGCG |
604 AMD_CG_SUPPORT_JPEG_MGCG |
605 AMD_CG_SUPPORT_ATHUB_MGCG |
606 AMD_CG_SUPPORT_ATHUB_LS |
607 AMD_CG_SUPPORT_IH_CG |
608 AMD_CG_SUPPORT_HDP_SD;
609 adev->pg_flags =
610 AMD_PG_SUPPORT_VCN |
611 AMD_PG_SUPPORT_VCN_DPG |
612 AMD_PG_SUPPORT_JPEG |
613 AMD_PG_SUPPORT_ATHUB |
614 AMD_PG_SUPPORT_MMHUB;
615 adev->external_rev_id = adev->rev_id + 0x10;
616 break;
617 case IP_VERSION(11, 0, 1):
618 adev->cg_flags =
619 AMD_CG_SUPPORT_GFX_CGCG |
620 AMD_CG_SUPPORT_GFX_CGLS |
621 AMD_CG_SUPPORT_GFX_MGCG |
622 AMD_CG_SUPPORT_GFX_FGCG |
623 AMD_CG_SUPPORT_REPEATER_FGCG |
624 AMD_CG_SUPPORT_GFX_PERF_CLK |
625 AMD_CG_SUPPORT_MC_MGCG |
626 AMD_CG_SUPPORT_MC_LS |
627 AMD_CG_SUPPORT_HDP_MGCG |
628 AMD_CG_SUPPORT_HDP_LS |
629 AMD_CG_SUPPORT_ATHUB_MGCG |
630 AMD_CG_SUPPORT_ATHUB_LS |
631 AMD_CG_SUPPORT_IH_CG |
632 AMD_CG_SUPPORT_BIF_MGCG |
633 AMD_CG_SUPPORT_BIF_LS |
634 AMD_CG_SUPPORT_VCN_MGCG |
635 AMD_CG_SUPPORT_JPEG_MGCG;
636 adev->pg_flags =
637 AMD_PG_SUPPORT_GFX_PG |
638 AMD_PG_SUPPORT_VCN |
639 AMD_PG_SUPPORT_VCN_DPG |
640 AMD_PG_SUPPORT_JPEG;
641 adev->external_rev_id = adev->rev_id + 0x1;
642 break;
643 case IP_VERSION(11, 0, 3):
644 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
645 AMD_CG_SUPPORT_JPEG_MGCG |
646 AMD_CG_SUPPORT_GFX_CGCG |
647 AMD_CG_SUPPORT_GFX_CGLS |
648 AMD_CG_SUPPORT_REPEATER_FGCG |
649 AMD_CG_SUPPORT_GFX_MGCG |
650 AMD_CG_SUPPORT_HDP_SD |
651 AMD_CG_SUPPORT_ATHUB_MGCG |
652 AMD_CG_SUPPORT_ATHUB_LS;
653 adev->pg_flags = AMD_PG_SUPPORT_VCN |
654 AMD_PG_SUPPORT_VCN_DPG |
655 AMD_PG_SUPPORT_JPEG;
656 adev->external_rev_id = adev->rev_id + 0x20;
657 break;
658 case IP_VERSION(11, 0, 4):
659 adev->cg_flags =
660 AMD_CG_SUPPORT_GFX_CGCG |
661 AMD_CG_SUPPORT_GFX_CGLS |
662 AMD_CG_SUPPORT_GFX_MGCG |
663 AMD_CG_SUPPORT_GFX_FGCG |
664 AMD_CG_SUPPORT_REPEATER_FGCG |
665 AMD_CG_SUPPORT_GFX_PERF_CLK |
666 AMD_CG_SUPPORT_MC_MGCG |
667 AMD_CG_SUPPORT_MC_LS |
668 AMD_CG_SUPPORT_HDP_MGCG |
669 AMD_CG_SUPPORT_HDP_LS |
670 AMD_CG_SUPPORT_ATHUB_MGCG |
671 AMD_CG_SUPPORT_ATHUB_LS |
672 AMD_CG_SUPPORT_IH_CG |
673 AMD_CG_SUPPORT_BIF_MGCG |
674 AMD_CG_SUPPORT_BIF_LS |
675 AMD_CG_SUPPORT_VCN_MGCG |
676 AMD_CG_SUPPORT_JPEG_MGCG;
677 adev->pg_flags = AMD_PG_SUPPORT_VCN |
678 AMD_PG_SUPPORT_VCN_DPG |
679 AMD_PG_SUPPORT_GFX_PG |
680 AMD_PG_SUPPORT_JPEG;
681 adev->external_rev_id = adev->rev_id + 0x80;
682 break;
683 case IP_VERSION(11, 5, 0):
684 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
685 AMD_CG_SUPPORT_JPEG_MGCG |
686 AMD_CG_SUPPORT_GFX_CGCG |
687 AMD_CG_SUPPORT_GFX_CGLS |
688 AMD_CG_SUPPORT_GFX_MGCG |
689 AMD_CG_SUPPORT_GFX_FGCG |
690 AMD_CG_SUPPORT_REPEATER_FGCG |
691 AMD_CG_SUPPORT_GFX_PERF_CLK |
692 AMD_CG_SUPPORT_GFX_3D_CGCG |
693 AMD_CG_SUPPORT_GFX_3D_CGLS |
694 AMD_CG_SUPPORT_MC_MGCG |
695 AMD_CG_SUPPORT_MC_LS |
696 AMD_CG_SUPPORT_HDP_LS |
697 AMD_CG_SUPPORT_HDP_DS |
698 AMD_CG_SUPPORT_HDP_SD |
699 AMD_CG_SUPPORT_ATHUB_MGCG |
700 AMD_CG_SUPPORT_ATHUB_LS |
701 AMD_CG_SUPPORT_IH_CG |
702 AMD_CG_SUPPORT_BIF_MGCG |
703 AMD_CG_SUPPORT_BIF_LS;
704 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
705 AMD_PG_SUPPORT_JPEG_DPG |
706 AMD_PG_SUPPORT_VCN |
707 AMD_PG_SUPPORT_JPEG |
708 AMD_PG_SUPPORT_GFX_PG;
709 if (adev->rev_id == 0)
710 adev->external_rev_id = 0x1;
711 else
712 adev->external_rev_id = adev->rev_id + 0x10;
713 break;
714 case IP_VERSION(11, 5, 1):
715 adev->cg_flags =
716 AMD_CG_SUPPORT_GFX_CGCG |
717 AMD_CG_SUPPORT_GFX_CGLS |
718 AMD_CG_SUPPORT_GFX_MGCG |
719 AMD_CG_SUPPORT_GFX_FGCG |
720 AMD_CG_SUPPORT_REPEATER_FGCG |
721 AMD_CG_SUPPORT_GFX_PERF_CLK |
722 AMD_CG_SUPPORT_GFX_3D_CGCG |
723 AMD_CG_SUPPORT_GFX_3D_CGLS |
724 AMD_CG_SUPPORT_MC_MGCG |
725 AMD_CG_SUPPORT_MC_LS |
726 AMD_CG_SUPPORT_HDP_LS |
727 AMD_CG_SUPPORT_HDP_DS |
728 AMD_CG_SUPPORT_HDP_SD |
729 AMD_CG_SUPPORT_ATHUB_MGCG |
730 AMD_CG_SUPPORT_ATHUB_LS |
731 AMD_CG_SUPPORT_IH_CG |
732 AMD_CG_SUPPORT_BIF_MGCG |
733 AMD_CG_SUPPORT_BIF_LS |
734 AMD_CG_SUPPORT_VCN_MGCG |
735 AMD_CG_SUPPORT_JPEG_MGCG;
736 adev->pg_flags =
737 AMD_PG_SUPPORT_GFX_PG |
738 AMD_PG_SUPPORT_VCN |
739 AMD_PG_SUPPORT_VCN_DPG |
740 AMD_PG_SUPPORT_JPEG;
741 adev->external_rev_id = adev->rev_id + 0xc1;
742 break;
743 case IP_VERSION(11, 5, 2):
744 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
745 AMD_CG_SUPPORT_JPEG_MGCG |
746 AMD_CG_SUPPORT_GFX_CGCG |
747 AMD_CG_SUPPORT_GFX_CGLS |
748 AMD_CG_SUPPORT_GFX_MGCG |
749 AMD_CG_SUPPORT_GFX_FGCG |
750 AMD_CG_SUPPORT_REPEATER_FGCG |
751 AMD_CG_SUPPORT_GFX_PERF_CLK |
752 AMD_CG_SUPPORT_GFX_3D_CGCG |
753 AMD_CG_SUPPORT_GFX_3D_CGLS |
754 AMD_CG_SUPPORT_MC_MGCG |
755 AMD_CG_SUPPORT_MC_LS |
756 AMD_CG_SUPPORT_HDP_LS |
757 AMD_CG_SUPPORT_HDP_DS |
758 AMD_CG_SUPPORT_HDP_SD |
759 AMD_CG_SUPPORT_ATHUB_MGCG |
760 AMD_CG_SUPPORT_ATHUB_LS |
761 AMD_CG_SUPPORT_IH_CG |
762 AMD_CG_SUPPORT_BIF_MGCG |
763 AMD_CG_SUPPORT_BIF_LS;
764 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
765 AMD_PG_SUPPORT_VCN |
766 AMD_PG_SUPPORT_JPEG_DPG |
767 AMD_PG_SUPPORT_JPEG |
768 AMD_PG_SUPPORT_GFX_PG;
769 adev->external_rev_id = adev->rev_id + 0x40;
770 break;
771 case IP_VERSION(11, 5, 3):
772 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
773 AMD_CG_SUPPORT_JPEG_MGCG |
774 AMD_CG_SUPPORT_GFX_CGCG |
775 AMD_CG_SUPPORT_GFX_CGLS |
776 AMD_CG_SUPPORT_GFX_MGCG |
777 AMD_CG_SUPPORT_GFX_FGCG |
778 AMD_CG_SUPPORT_REPEATER_FGCG |
779 AMD_CG_SUPPORT_GFX_PERF_CLK |
780 AMD_CG_SUPPORT_GFX_3D_CGCG |
781 AMD_CG_SUPPORT_GFX_3D_CGLS |
782 AMD_CG_SUPPORT_MC_MGCG |
783 AMD_CG_SUPPORT_MC_LS |
784 AMD_CG_SUPPORT_HDP_LS |
785 AMD_CG_SUPPORT_HDP_DS |
786 AMD_CG_SUPPORT_HDP_SD |
787 AMD_CG_SUPPORT_ATHUB_MGCG |
788 AMD_CG_SUPPORT_ATHUB_LS |
789 AMD_CG_SUPPORT_IH_CG |
790 AMD_CG_SUPPORT_BIF_MGCG |
791 AMD_CG_SUPPORT_BIF_LS;
792 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
793 AMD_PG_SUPPORT_VCN |
794 AMD_PG_SUPPORT_JPEG_DPG |
795 AMD_PG_SUPPORT_JPEG |
796 AMD_PG_SUPPORT_GFX_PG;
797 adev->external_rev_id = adev->rev_id + 0x50;
798 break;
799 case IP_VERSION(11, 5, 4):
800 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
801 AMD_CG_SUPPORT_JPEG_MGCG |
802 AMD_CG_SUPPORT_GFX_CGCG |
803 AMD_CG_SUPPORT_GFX_CGLS |
804 AMD_CG_SUPPORT_GFX_MGCG |
805 AMD_CG_SUPPORT_GFX_FGCG |
806 AMD_CG_SUPPORT_REPEATER_FGCG |
807 AMD_CG_SUPPORT_GFX_PERF_CLK |
808 AMD_CG_SUPPORT_GFX_3D_CGCG |
809 AMD_CG_SUPPORT_GFX_3D_CGLS |
810 AMD_CG_SUPPORT_MC_MGCG |
811 AMD_CG_SUPPORT_MC_LS |
812 AMD_CG_SUPPORT_HDP_LS |
813 AMD_CG_SUPPORT_HDP_DS |
814 AMD_CG_SUPPORT_HDP_SD |
815 AMD_CG_SUPPORT_ATHUB_MGCG |
816 AMD_CG_SUPPORT_ATHUB_LS |
817 AMD_CG_SUPPORT_IH_CG |
818 AMD_CG_SUPPORT_BIF_MGCG |
819 AMD_CG_SUPPORT_BIF_LS;
820 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
821 AMD_PG_SUPPORT_VCN |
822 AMD_PG_SUPPORT_JPEG_DPG |
823 AMD_PG_SUPPORT_JPEG |
824 AMD_PG_SUPPORT_GFX_PG;
825 adev->external_rev_id = adev->rev_id + 0x1;
826 break;
827 case IP_VERSION(11, 5, 6):
828 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
829 AMD_CG_SUPPORT_GFX_CGLS |
830 AMD_CG_SUPPORT_GFX_MGCG |
831 AMD_CG_SUPPORT_GFX_FGCG |
832 AMD_CG_SUPPORT_REPEATER_FGCG |
833 AMD_CG_SUPPORT_GFX_PERF_CLK |
834 AMD_CG_SUPPORT_GFX_3D_CGCG |
835 AMD_CG_SUPPORT_GFX_3D_CGLS |
836 AMD_CG_SUPPORT_MC_MGCG |
837 AMD_CG_SUPPORT_MC_LS |
838 AMD_CG_SUPPORT_HDP_LS |
839 AMD_CG_SUPPORT_HDP_DS |
840 AMD_CG_SUPPORT_HDP_SD |
841 AMD_CG_SUPPORT_ATHUB_MGCG |
842 AMD_CG_SUPPORT_ATHUB_LS |
843 AMD_CG_SUPPORT_IH_CG |
844 AMD_CG_SUPPORT_BIF_MGCG |
845 AMD_CG_SUPPORT_BIF_LS;
846 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG;
847 adev->external_rev_id = adev->rev_id + 0xd0;
848 break;
849 case IP_VERSION(11, 7, 0):
850 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
851 AMD_CG_SUPPORT_JPEG_MGCG |
852 AMD_CG_SUPPORT_GFX_CGCG |
853 AMD_CG_SUPPORT_GFX_CGLS |
854 AMD_CG_SUPPORT_GFX_MGCG |
855 AMD_CG_SUPPORT_GFX_FGCG |
856 AMD_CG_SUPPORT_REPEATER_FGCG |
857 AMD_CG_SUPPORT_GFX_PERF_CLK |
858 AMD_CG_SUPPORT_GFX_3D_CGCG |
859 AMD_CG_SUPPORT_GFX_3D_CGLS |
860 AMD_CG_SUPPORT_MC_MGCG |
861 AMD_CG_SUPPORT_MC_LS |
862 AMD_CG_SUPPORT_HDP_LS |
863 AMD_CG_SUPPORT_HDP_DS |
864 AMD_CG_SUPPORT_HDP_SD |
865 AMD_CG_SUPPORT_ATHUB_MGCG |
866 AMD_CG_SUPPORT_ATHUB_LS |
867 AMD_CG_SUPPORT_IH_CG |
868 AMD_CG_SUPPORT_BIF_MGCG |
869 AMD_CG_SUPPORT_BIF_LS;
870 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
871 AMD_PG_SUPPORT_VCN |
872 AMD_PG_SUPPORT_JPEG |
873 AMD_PG_SUPPORT_GFX_PG;
874 adev->external_rev_id = adev->rev_id + 0xF;
875 break;
876 case IP_VERSION(11, 7, 1):
877 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
878 AMD_CG_SUPPORT_JPEG_MGCG |
879 AMD_CG_SUPPORT_GFX_CGCG |
880 AMD_CG_SUPPORT_GFX_CGLS |
881 AMD_CG_SUPPORT_GFX_MGCG |
882 AMD_CG_SUPPORT_GFX_FGCG |
883 AMD_CG_SUPPORT_REPEATER_FGCG |
884 AMD_CG_SUPPORT_GFX_PERF_CLK |
885 AMD_CG_SUPPORT_GFX_3D_CGCG |
886 AMD_CG_SUPPORT_GFX_3D_CGLS |
887 AMD_CG_SUPPORT_MC_MGCG |
888 AMD_CG_SUPPORT_MC_LS |
889 AMD_CG_SUPPORT_HDP_LS |
890 AMD_CG_SUPPORT_HDP_DS |
891 AMD_CG_SUPPORT_HDP_SD |
892 AMD_CG_SUPPORT_ATHUB_MGCG |
893 AMD_CG_SUPPORT_ATHUB_LS |
894 AMD_CG_SUPPORT_IH_CG |
895 AMD_CG_SUPPORT_BIF_MGCG |
896 AMD_CG_SUPPORT_BIF_LS;
897 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
898 AMD_PG_SUPPORT_VCN |
899 AMD_PG_SUPPORT_JPEG |
900 AMD_PG_SUPPORT_GFX_PG;
901 adev->external_rev_id = adev->rev_id + 0x40;
902 break;
903 default:
904 /* FIXME: not supported yet */
905 return -EINVAL;
906 }
907
908 if (amdgpu_sriov_vf(adev)) {
909 amdgpu_virt_init_setting(adev);
910 xgpu_nv_mailbox_set_irq_funcs(adev);
911 }
912
913 return 0;
914}
915
916static int soc21_common_late_init(struct amdgpu_ip_block *ip_block)
917{
918 struct amdgpu_device *adev = ip_block->adev;
919
920 if (amdgpu_sriov_vf(adev)) {
921 xgpu_nv_mailbox_get_irq(adev);
922 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
923 !amdgpu_sriov_is_av1_support(adev)) {
924 amdgpu_virt_update_sriov_video_codec(adev,
925 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
926 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
927 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
928 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
929 } else {
930 amdgpu_virt_update_sriov_video_codec(adev,
931 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
932 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
933 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
934 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
935 }
936 } else {
937 if (adev->nbio.ras &&
938 adev->nbio.ras_err_event_athub_irq.funcs)
939 /* don't need to fail gpu late init
940 * if enabling athub_err_event interrupt failed
941 * nbio v4_3 only support fatal error hanlding
942 * just enable the interrupt directly */
943 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
944 }
945
946 /* Enable selfring doorbell aperture late because doorbell BAR
947 * aperture will change if resize BAR successfully in gmc sw_init.
948 */
949 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
950
951 return 0;
952}
953
954static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block)
955{
956 struct amdgpu_device *adev = ip_block->adev;
957
958 if (amdgpu_sriov_vf(adev))
959 xgpu_nv_mailbox_add_irq_id(adev);
960
961 return 0;
962}
963
964static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block)
965{
966 struct amdgpu_device *adev = ip_block->adev;
967
968 /* enable aspm */
969 amdgpu_nbio_program_aspm(adev);
970 /* setup nbio registers */
971 adev->nbio.funcs->init_registers(adev);
972 /* remap HDP registers to a hole in mmio space,
973 * for the purpose of expose those registers
974 * to process space
975 */
976 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
977 adev->nbio.funcs->remap_hdp_registers(adev);
978 /* enable the doorbell aperture */
979 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
980
981 return 0;
982}
983
984static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block)
985{
986 struct amdgpu_device *adev = ip_block->adev;
987
988 /* Disable the doorbell aperture and selfring doorbell aperture
989 * separately in hw_fini because soc21_enable_doorbell_aperture
990 * has been removed and there is no need to delay disabling
991 * selfring doorbell.
992 */
993 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
994 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
995
996 if (amdgpu_sriov_vf(adev)) {
997 xgpu_nv_mailbox_put_irq(adev);
998 } else {
999 if (adev->nbio.ras &&
1000 adev->nbio.ras_err_event_athub_irq.funcs)
1001 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1002 }
1003
1004 return 0;
1005}
1006
1007static int soc21_common_suspend(struct amdgpu_ip_block *ip_block)
1008{
1009 return soc21_common_hw_fini(ip_block);
1010}
1011
1012static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
1013{
1014 u32 sol_reg1, sol_reg2;
1015
1016 /* Will reset for the following suspend abort cases.
1017 * 1) Only reset dGPU side.
1018 * 2) S3 suspend got aborted and TOS is active.
1019 * As for dGPU suspend abort cases the SOL value
1020 * will be kept as zero at this resume point.
1021 */
1022 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) {
1023 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1024 msleep(100);
1025 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1026
1027 return (sol_reg1 != sol_reg2);
1028 }
1029
1030 return false;
1031}
1032
1033static int soc21_common_resume(struct amdgpu_ip_block *ip_block)
1034{
1035 struct amdgpu_device *adev = ip_block->adev;
1036
1037 if (soc21_need_reset_on_resume(adev)) {
1038 dev_info(adev->dev, "S3 suspend aborted, resetting...");
1039 soc21_asic_reset(adev);
1040 }
1041
1042 return soc21_common_hw_init(ip_block);
1043}
1044
1045static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block)
1046{
1047 return true;
1048}
1049
1050static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1051 enum amd_clockgating_state state)
1052{
1053 struct amdgpu_device *adev = ip_block->adev;
1054
1055 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
1056 case IP_VERSION(4, 3, 0):
1057 case IP_VERSION(4, 3, 1):
1058 case IP_VERSION(7, 7, 0):
1059 case IP_VERSION(7, 7, 1):
1060 case IP_VERSION(7, 11, 0):
1061 case IP_VERSION(7, 11, 1):
1062 case IP_VERSION(7, 11, 2):
1063 case IP_VERSION(7, 11, 3):
1064 case IP_VERSION(7, 11, 4):
1065 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1066 state == AMD_CG_STATE_GATE);
1067 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1068 state == AMD_CG_STATE_GATE);
1069 adev->hdp.funcs->update_clock_gating(adev,
1070 state == AMD_CG_STATE_GATE);
1071 break;
1072 default:
1073 break;
1074 }
1075 return 0;
1076}
1077
1078static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
1079 enum amd_powergating_state state)
1080{
1081 struct amdgpu_device *adev = ip_block->adev;
1082
1083 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
1084 case IP_VERSION(6, 0, 0):
1085 case IP_VERSION(6, 0, 2):
1086 adev->lsdma.funcs->update_memory_power_gating(adev,
1087 state == AMD_PG_STATE_GATE);
1088 break;
1089 default:
1090 break;
1091 }
1092
1093 return 0;
1094}
1095
1096static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
1097{
1098 struct amdgpu_device *adev = ip_block->adev;
1099
1100 adev->nbio.funcs->get_clockgating_state(adev, flags);
1101
1102 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1103}
1104
1105static const struct amd_ip_funcs soc21_common_ip_funcs = {
1106 .name = "soc21_common",
1107 .early_init = soc21_common_early_init,
1108 .late_init = soc21_common_late_init,
1109 .sw_init = soc21_common_sw_init,
1110 .hw_init = soc21_common_hw_init,
1111 .hw_fini = soc21_common_hw_fini,
1112 .suspend = soc21_common_suspend,
1113 .resume = soc21_common_resume,
1114 .is_idle = soc21_common_is_idle,
1115 .set_clockgating_state = soc21_common_set_clockgating_state,
1116 .set_powergating_state = soc21_common_set_powergating_state,
1117 .get_clockgating_state = soc21_common_get_clockgating_state,
1118};