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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#include <drm/drm_crtc.h>
28#include <drm/drm_vblank.h>
29
30#include "amdgpu.h"
31#include "amdgpu_dm.h"
32#include "dc.h"
33#include "amdgpu_securedisplay.h"
34#include "amdgpu_dm_psr.h"
35#include "amdgpu_dm_replay.h"
36#include "dm_helpers.h"
37
38static const char *const pipe_crc_sources[] = {
39 "none",
40 "crtc",
41 "crtc dither",
42 "dprx",
43 "dprx dither",
44 "auto",
45};
46
47STATIC_IFN_KUNIT
48enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
49{
50 if (!source || !strcmp(source, "none"))
51 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
52 if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
53 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
54 if (!strcmp(source, "dprx"))
55 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
56 if (!strcmp(source, "crtc dither"))
57 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER;
58 if (!strcmp(source, "dprx dither"))
59 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER;
60
61 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
62}
63EXPORT_IF_KUNIT(dm_parse_crc_source);
64
65STATIC_IFN_KUNIT
66bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
67{
68 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
69 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER);
70}
71EXPORT_IF_KUNIT(dm_is_crc_source_crtc);
72
73STATIC_IFN_KUNIT
74bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
75{
76 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) ||
77 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER);
78}
79EXPORT_IF_KUNIT(dm_is_crc_source_dprx);
80
81STATIC_IFN_KUNIT
82bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
83{
84 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) ||
85 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) ||
86 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE);
87}
88EXPORT_IF_KUNIT(dm_need_crc_dither);
89
90/**
91 * dm_need_dp_aux() - Does this source transition require the DP AUX handle?
92 * @source: Requested CRC source.
93 * @cur_crc_src: Current CRC source.
94 *
95 * Returns true when either the new source is DPRX-based (starting DPRX CRC),
96 * or the current source is DPRX-based and the new source is NONE (stopping it).
97 *
98 * Return: true if the DP AUX handle is needed, false otherwise.
99 */
100STATIC_IFN_KUNIT
101bool dm_need_dp_aux(enum amdgpu_dm_pipe_crc_source source,
102 enum amdgpu_dm_pipe_crc_source cur_crc_src)
103{
104 return dm_is_crc_source_dprx(source) ||
105 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && dm_is_crc_source_dprx(cur_crc_src));
106}
107EXPORT_IF_KUNIT(dm_need_dp_aux);
108
109/**
110 * dm_crc_source_should_start_dprx() - Should drm_dp_start_crc() be called?
111 * @source: Requested CRC source.
112 * @cur_crc_src: Current CRC source.
113 *
114 * True when CRC is transitioning from off to a DPRX source
115 * (!enabled && enable && is_dprx(@source)).
116 *
117 * Return: true if drm_dp_start_crc() should be called, false otherwise.
118 */
119STATIC_IFN_KUNIT
120bool dm_crc_source_should_start_dprx(enum amdgpu_dm_pipe_crc_source source,
121 enum amdgpu_dm_pipe_crc_source cur_crc_src)
122{
123 return !amdgpu_dm_is_valid_crc_source(cur_crc_src) &&
124 amdgpu_dm_is_valid_crc_source(source) &&
125 dm_is_crc_source_dprx(source);
126}
127EXPORT_IF_KUNIT(dm_crc_source_should_start_dprx);
128
129/**
130 * dm_crc_source_should_stop_dprx() - Should drm_dp_stop_crc() be called?
131 * @source: Requested CRC source.
132 * @cur_crc_src: Current CRC source.
133 *
134 * True when CRC is transitioning from a DPRX source to off
135 * (enabled && !enable && is_dprx(@cur_crc_src)).
136 *
137 * Return: true if drm_dp_stop_crc() should be called, false otherwise.
138 */
139STATIC_IFN_KUNIT
140bool dm_crc_source_should_stop_dprx(enum amdgpu_dm_pipe_crc_source source,
141 enum amdgpu_dm_pipe_crc_source cur_crc_src)
142{
143 return amdgpu_dm_is_valid_crc_source(cur_crc_src) &&
144 !amdgpu_dm_is_valid_crc_source(source) &&
145 dm_is_crc_source_dprx(cur_crc_src);
146}
147EXPORT_IF_KUNIT(dm_crc_source_should_stop_dprx);
148
149const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
150 size_t *count)
151{
152 *count = ARRAY_SIZE(pipe_crc_sources);
153 return pipe_crc_sources;
154}
155EXPORT_IF_KUNIT(amdgpu_dm_crtc_get_crc_sources);
156
157#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
158static void update_phy_id_mapping(struct amdgpu_device *adev)
159{
160 struct drm_device *ddev = adev_to_drm(adev);
161 struct amdgpu_display_manager *dm = &adev->dm;
162 struct drm_connector *connector;
163 struct amdgpu_dm_connector *aconnector;
164 struct amdgpu_dm_connector *sort_connector[AMDGPU_DM_MAX_CRTC] = {NULL};
165 struct drm_connector_list_iter iter;
166 uint8_t idx = 0, idx_2 = 0, connector_cnt = 0;
167
168 dm->secure_display_ctx.phy_mapping_updated = false;
169
170 mutex_lock(&ddev->mode_config.mutex);
171 drm_connector_list_iter_begin(ddev, &iter);
172 drm_for_each_connector_iter(connector, &iter) {
173
174 if (connector->status != connector_status_connected)
175 continue;
176
177 if (idx >= AMDGPU_DM_MAX_CRTC) {
178 drm_warn(adev_to_drm(adev),
179 "%s connected connectors exceed max crtc\n",
180 __func__);
181 mutex_unlock(&ddev->mode_config.mutex);
182 return;
183 }
184
185 aconnector = to_amdgpu_dm_connector(connector);
186
187 sort_connector[idx] = aconnector;
188 idx++;
189 connector_cnt++;
190 }
191 drm_connector_list_iter_end(&iter);
192
193 /* sort connectors by link_enc_hw_instance first */
194 for (idx = connector_cnt; idx > 1 ; idx--) {
195 for (idx_2 = 0; idx_2 < (idx - 1); idx_2++) {
196 if (sort_connector[idx_2]->dc_link->link_enc_hw_inst >
197 sort_connector[idx_2 + 1]->dc_link->link_enc_hw_inst)
198 swap(sort_connector[idx_2], sort_connector[idx_2 + 1]);
199 }
200 }
201
202 /*
203 * Sort mst connectors by RAD. mst connectors with the same enc_hw_instance are already
204 * sorted together above.
205 */
206 for (idx = 0; idx < connector_cnt; /*Do nothing*/) {
207 if (sort_connector[idx]->mst_root) {
208 uint8_t i, j, k;
209 uint8_t mst_con_cnt = 1;
210
211 for (idx_2 = (idx + 1); idx_2 < connector_cnt; idx_2++) {
212 if (sort_connector[idx_2]->mst_root == sort_connector[idx]->mst_root)
213 mst_con_cnt++;
214 else
215 break;
216 }
217
218 for (i = mst_con_cnt; i > 1; i--) {
219 for (j = idx; j < (idx + i - 2); j++) {
220 int mstb_lct = sort_connector[j]->mst_output_port->parent->lct;
221 int next_mstb_lct = sort_connector[j + 1]->mst_output_port->parent->lct;
222 u8 *rad;
223 u8 *next_rad;
224 bool swap = false;
225
226 /* Sort by mst tree depth first. Then compare RAD if depth is the same*/
227 if (mstb_lct > next_mstb_lct) {
228 swap = true;
229 } else if (mstb_lct == next_mstb_lct) {
230 if (mstb_lct == 1) {
231 if (sort_connector[j]->mst_output_port->port_num > sort_connector[j + 1]->mst_output_port->port_num)
232 swap = true;
233 } else if (mstb_lct > 1) {
234 rad = sort_connector[j]->mst_output_port->parent->rad;
235 next_rad = sort_connector[j + 1]->mst_output_port->parent->rad;
236
237 for (k = 0; k < mstb_lct - 1; k++) {
238 int shift = (k % 2) ? 0 : 4;
239 int port_num = (rad[k / 2] >> shift) & 0xf;
240 int next_port_num = (next_rad[k / 2] >> shift) & 0xf;
241
242 if (port_num > next_port_num) {
243 swap = true;
244 break;
245 }
246 }
247 } else {
248 DRM_ERROR("MST LCT shouldn't be set as < 1");
249 mutex_unlock(&ddev->mode_config.mutex);
250 return;
251 }
252 }
253
254 if (swap)
255 swap(sort_connector[j], sort_connector[j + 1]);
256 }
257 }
258
259 idx += mst_con_cnt;
260 } else {
261 idx++;
262 }
263 }
264
265 /* Complete sorting. Assign relavant result to dm->secure_display_ctx.phy_id_mapping[]*/
266 memset(dm->secure_display_ctx.phy_id_mapping, 0, sizeof(dm->secure_display_ctx.phy_id_mapping));
267 for (idx = 0; idx < connector_cnt; idx++) {
268 aconnector = sort_connector[idx];
269
270 dm->secure_display_ctx.phy_id_mapping[idx].assigned = true;
271 dm->secure_display_ctx.phy_id_mapping[idx].is_mst = false;
272 dm->secure_display_ctx.phy_id_mapping[idx].enc_hw_inst = aconnector->dc_link->link_enc_hw_inst;
273
274 if (sort_connector[idx]->mst_root) {
275 dm->secure_display_ctx.phy_id_mapping[idx].is_mst = true;
276 dm->secure_display_ctx.phy_id_mapping[idx].lct = aconnector->mst_output_port->parent->lct;
277 dm->secure_display_ctx.phy_id_mapping[idx].port_num = aconnector->mst_output_port->port_num;
278 memcpy(dm->secure_display_ctx.phy_id_mapping[idx].rad,
279 aconnector->mst_output_port->parent->rad, sizeof(aconnector->mst_output_port->parent->rad));
280 }
281 }
282 mutex_unlock(&ddev->mode_config.mutex);
283
284 dm->secure_display_ctx.phy_id_mapping_cnt = connector_cnt;
285 dm->secure_display_ctx.phy_mapping_updated = true;
286}
287
288static bool get_phy_id(struct amdgpu_display_manager *dm,
289 struct amdgpu_dm_connector *aconnector, uint8_t *phy_id)
290{
291 int idx, idx_2;
292 bool found = false;
293
294 /*
295 * Assume secure display start after all connectors are probed. The connection
296 * config is static as well
297 */
298 if (!dm->secure_display_ctx.phy_mapping_updated) {
299 DRM_WARN("%s Should update the phy id table before get it's value", __func__);
300 return false;
301 }
302
303 for (idx = 0; idx < dm->secure_display_ctx.phy_id_mapping_cnt; idx++) {
304 if (!dm->secure_display_ctx.phy_id_mapping[idx].assigned) {
305 DRM_ERROR("phy_id_mapping[%d] should be assigned", idx);
306 return false;
307 }
308
309 if (aconnector->dc_link->link_enc_hw_inst ==
310 dm->secure_display_ctx.phy_id_mapping[idx].enc_hw_inst) {
311 if (!dm->secure_display_ctx.phy_id_mapping[idx].is_mst) {
312 found = true;
313 goto out;
314 } else {
315 /* Could caused by wrongly pass mst root connector */
316 if (!aconnector->mst_output_port) {
317 DRM_ERROR("%s Check mst case but connector without a port assigned", __func__);
318 return false;
319 }
320
321 if (aconnector->mst_root &&
322 aconnector->mst_root->mst_mgr.mst_primary == NULL) {
323 DRM_WARN("%s pass in a stale mst connector", __func__);
324 }
325
326 if (aconnector->mst_output_port->parent->lct == dm->secure_display_ctx.phy_id_mapping[idx].lct &&
327 aconnector->mst_output_port->port_num == dm->secure_display_ctx.phy_id_mapping[idx].port_num) {
328 if (aconnector->mst_output_port->parent->lct == 1) {
329 found = true;
330 goto out;
331 } else if (aconnector->mst_output_port->parent->lct > 1) {
332 /* Check RAD */
333 for (idx_2 = 0; idx_2 < aconnector->mst_output_port->parent->lct - 1; idx_2++) {
334 int shift = (idx_2 % 2) ? 0 : 4;
335 int port_num = (aconnector->mst_output_port->parent->rad[idx_2 / 2] >> shift) & 0xf;
336 int port_num2 = (dm->secure_display_ctx.phy_id_mapping[idx].rad[idx_2 / 2] >> shift) & 0xf;
337
338 if (port_num != port_num2)
339 break;
340 }
341
342 if (idx_2 == aconnector->mst_output_port->parent->lct - 1) {
343 found = true;
344 goto out;
345 }
346 } else {
347 DRM_ERROR("lCT should be >= 1");
348 return false;
349 }
350 }
351 }
352 }
353 }
354
355out:
356 if (found) {
357 DRM_DEBUG_DRIVER("Associated secure display PHY ID as %d", idx);
358 *phy_id = idx;
359 } else {
360 DRM_WARN("Can't find associated phy ID");
361 return false;
362 }
363
364 return true;
365}
366
367static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct dc_stream_state *stream)
368{
369 struct drm_device *drm_dev = crtc->dev;
370 struct amdgpu_display_manager *dm = &drm_to_adev(drm_dev)->dm;
371 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
372 struct amdgpu_dm_connector *aconnector;
373 bool was_activated;
374 uint8_t phy_id;
375 unsigned long flags;
376 int i;
377
378 spin_lock_irqsave(&drm_dev->event_lock, flags);
379 was_activated = acrtc->dm_irq_params.crc_window_activated;
380 for (i = 0; i < MAX_CRC_WINDOW_NUM; i++) {
381 acrtc->dm_irq_params.window_param[i].x_start = 0;
382 acrtc->dm_irq_params.window_param[i].y_start = 0;
383 acrtc->dm_irq_params.window_param[i].x_end = 0;
384 acrtc->dm_irq_params.window_param[i].y_end = 0;
385 acrtc->dm_irq_params.window_param[i].enable = false;
386 acrtc->dm_irq_params.window_param[i].update_win = false;
387 acrtc->dm_irq_params.window_param[i].skip_frame_cnt = 0;
388 }
389 acrtc->dm_irq_params.crc_window_activated = false;
390 spin_unlock_irqrestore(&drm_dev->event_lock, flags);
391
392 /* Disable secure_display if it was enabled */
393 if (was_activated && dm->secure_display_ctx.op_mode == LEGACY_MODE) {
394 /* stop ROI update on this crtc */
395 flush_work(&dm->secure_display_ctx.crtc_ctx[crtc->index].notify_ta_work);
396 flush_work(&dm->secure_display_ctx.crtc_ctx[crtc->index].forward_roi_work);
397 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
398
399 if (aconnector && get_phy_id(dm, aconnector, &phy_id)) {
400 if (dm->secure_display_ctx.support_mul_roi)
401 dc_stream_forward_multiple_crc_window(stream, NULL, phy_id, true);
402 else
403 dc_stream_forward_crc_window(stream, NULL, phy_id, true);
404 } else {
405 DRM_DEBUG_DRIVER("%s Can't find matching phy id", __func__);
406 }
407 }
408}
409
410static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)
411{
412 struct secure_display_crtc_context *crtc_ctx;
413 struct psp_context *psp;
414 struct ta_securedisplay_cmd *securedisplay_cmd;
415 struct drm_crtc *crtc;
416 struct dc_stream_state *stream;
417 struct amdgpu_dm_connector *aconnector;
418 uint8_t phy_inst;
419 struct amdgpu_display_manager *dm;
420 struct crc_data crc_cpy[MAX_CRC_WINDOW_NUM];
421 unsigned long flags;
422 uint8_t roi_idx = 0;
423 int ret;
424 int i;
425
426 crtc_ctx = container_of(work, struct secure_display_crtc_context, notify_ta_work);
427 crtc = crtc_ctx->crtc;
428
429 if (!crtc)
430 return;
431
432 psp = &drm_to_adev(crtc->dev)->psp;
433
434 if (!psp->securedisplay_context.context.initialized) {
435 DRM_DEBUG_DRIVER("Secure Display fails to notify PSP TA\n");
436 return;
437 }
438
439 dm = &drm_to_adev(crtc->dev)->dm;
440 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
441 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
442 if (!aconnector)
443 return;
444
445 mutex_lock(&crtc->dev->mode_config.mutex);
446 if (!get_phy_id(dm, aconnector, &phy_inst)) {
447 DRM_WARN("%s Can't find mapping phy id!", __func__);
448 mutex_unlock(&crtc->dev->mode_config.mutex);
449 return;
450 }
451 mutex_unlock(&crtc->dev->mode_config.mutex);
452
453 spin_lock_irqsave(&crtc->dev->event_lock, flags);
454 memcpy(crc_cpy, crtc_ctx->crc_info.crc, sizeof(struct crc_data) * MAX_CRC_WINDOW_NUM);
455 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
456
457 /* need lock for multiple crtcs to use the command buffer */
458 mutex_lock(&psp->securedisplay_context.mutex);
459 /* PSP TA is expected to finish data transmission over I2C within current frame,
460 * even there are up to 4 crtcs request to send in this frame.
461 */
462 if (dm->secure_display_ctx.support_mul_roi) {
463 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
464 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2);
465
466 securedisplay_cmd->securedisplay_in_message.send_roi_crc_v2.phy_id = phy_inst;
467
468 for (i = 0; i < MAX_CRC_WINDOW_NUM; i++) {
469 if (crc_cpy[i].crc_ready)
470 roi_idx |= 1 << i;
471 }
472 securedisplay_cmd->securedisplay_in_message.send_roi_crc_v2.roi_idx = roi_idx;
473
474 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC_V2);
475 } else {
476 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
477 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
478
479 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst;
480
481 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
482 }
483
484 if (!ret) {
485 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS)
486 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
487 }
488
489 mutex_unlock(&psp->securedisplay_context.mutex);
490}
491
492static void
493amdgpu_dm_forward_crc_window(struct work_struct *work)
494{
495 struct secure_display_crtc_context *crtc_ctx;
496 struct amdgpu_display_manager *dm;
497 struct drm_crtc *crtc;
498 struct dc_stream_state *stream;
499 struct amdgpu_dm_connector *aconnector;
500 struct crc_window roi_cpy[MAX_CRC_WINDOW_NUM];
501 unsigned long flags;
502 uint8_t phy_id;
503
504 crtc_ctx = container_of(work, struct secure_display_crtc_context, forward_roi_work);
505 crtc = crtc_ctx->crtc;
506
507 if (!crtc)
508 return;
509
510 dm = &drm_to_adev(crtc->dev)->dm;
511 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
512 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
513
514 if (!aconnector)
515 return;
516
517 mutex_lock(&crtc->dev->mode_config.mutex);
518 if (!get_phy_id(dm, aconnector, &phy_id)) {
519 DRM_WARN("%s Can't find mapping phy id!", __func__);
520 mutex_unlock(&crtc->dev->mode_config.mutex);
521 return;
522 }
523 mutex_unlock(&crtc->dev->mode_config.mutex);
524
525 spin_lock_irqsave(&crtc->dev->event_lock, flags);
526 memcpy(roi_cpy, crtc_ctx->roi, sizeof(struct crc_window) * MAX_CRC_WINDOW_NUM);
527 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
528
529 mutex_lock(&dm->dc_lock);
530 if (dm->secure_display_ctx.support_mul_roi)
531 dc_stream_forward_multiple_crc_window(stream, roi_cpy,
532 phy_id, false);
533 else
534 dc_stream_forward_crc_window(stream, &roi_cpy[0].rect,
535 phy_id, false);
536 mutex_unlock(&dm->dc_lock);
537}
538
539bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)
540{
541 struct drm_device *drm_dev = crtc->dev;
542 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
543 bool ret = false;
544
545 spin_lock_irq(&drm_dev->event_lock);
546 ret = acrtc->dm_irq_params.crc_window_activated;
547 spin_unlock_irq(&drm_dev->event_lock);
548
549 return ret;
550}
551#endif
552
553int
554amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
555 size_t *values_cnt)
556{
557 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
558
559 if (source == AMDGPU_DM_PIPE_CRC_SOURCE_INVALID) {
560 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
561 src_name, crtc->index);
562 return -EINVAL;
563 }
564
565 *values_cnt = 3;
566 return 0;
567}
568EXPORT_IF_KUNIT(amdgpu_dm_crtc_verify_crc_source);
569
570int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
571 struct dm_crtc_state *dm_crtc_state,
572 enum amdgpu_dm_pipe_crc_source source)
573{
574 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
575 struct dc_stream_state *stream_state = dm_crtc_state->stream;
576 bool enable = amdgpu_dm_is_valid_crc_source(source);
577 int ret = 0;
578 enum crc_poly_mode crc_poly_mode = CRC_POLY_MODE_16;
579
580 /* Configuration will be deferred to stream enable. */
581 if (!stream_state)
582 return -EINVAL;
583
584 mutex_lock(&adev->dm.dc_lock);
585
586 /* Notify power module about CRC window active to disable PSR/Replay
587 * Power module will check caps internally and skip if not supported
588 */
589 if (enable) {
590 amdgpu_dm_psr_set_event(&adev->dm, stream_state, true,
591 psr_event_crc_window_active, true);
592
593 amdgpu_dm_replay_set_event(&adev->dm, stream_state, true,
594 replay_event_crc_window_active, true);
595 }
596
597 /* CRC polynomial selection only support for DCN3.6+ except DCN4.0.1 */
598 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) &&
599 (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1))) {
600 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
601
602 crc_poly_mode = acrtc->dm_irq_params.crc_poly_mode;
603 }
604
605 /* Enable or disable CRTC CRC generation */
606 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
607 int i;
608
609 for (i = 0; i < MAX_CRC_WINDOW_NUM; i++) {
610 if (!dc_stream_configure_crc(stream_state->ctx->dc,
611 stream_state, NULL, enable, enable,
612 i, true, crc_poly_mode)) {
613 ret = -EINVAL;
614 goto unlock;
615 }
616 }
617 }
618
619 /* Configure dithering */
620 if (!dm_need_crc_dither(source)) {
621 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
622 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
623 DYN_EXPANSION_DISABLE);
624 } else {
625 dc_stream_set_dither_option(stream_state,
626 DITHER_OPTION_DEFAULT);
627 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
628 DYN_EXPANSION_AUTO);
629 }
630
631 if (!enable) {
632 /* Notify power module about CRC window inactive to re-enable PSR/Replay
633 * Power module will check caps internally and skip if not supported
634 */
635 amdgpu_dm_psr_set_event(&adev->dm, stream_state, false,
636 psr_event_crc_window_active, false);
637
638 amdgpu_dm_replay_set_event(&adev->dm, stream_state, false,
639 replay_event_crc_window_active, false);
640 }
641unlock:
642 mutex_unlock(&adev->dm.dc_lock);
643
644 return ret;
645}
646EXPORT_IF_KUNIT(amdgpu_dm_crtc_configure_crc_source);
647
648int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
649{
650 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
651 enum amdgpu_dm_pipe_crc_source cur_crc_src;
652 struct drm_crtc_commit *commit;
653 struct dm_crtc_state *crtc_state;
654 struct drm_device *drm_dev = crtc->dev;
655#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
656 struct amdgpu_device *adev = drm_to_adev(drm_dev);
657 struct amdgpu_display_manager *dm = &adev->dm;
658#endif
659 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
660 struct drm_dp_aux *aux = NULL;
661 bool enable = false;
662 bool enabled = false;
663 int ret = 0;
664
665 if (source == AMDGPU_DM_PIPE_CRC_SOURCE_INVALID) {
666 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
667 src_name, crtc->index);
668 return -EINVAL;
669 }
670
671 ret = drm_modeset_lock(&crtc->mutex, NULL);
672 if (ret)
673 return ret;
674
675 spin_lock(&crtc->commit_lock);
676 commit = list_first_entry_or_null(&crtc->commit_list,
677 struct drm_crtc_commit, commit_entry);
678 if (commit)
679 drm_crtc_commit_get(commit);
680 spin_unlock(&crtc->commit_lock);
681
682 if (commit) {
683 /*
684 * Need to wait for all outstanding programming to complete
685 * in commit tail since it can modify CRC related fields and
686 * hardware state. Since we're holding the CRTC lock we're
687 * guaranteed that no other commit work can be queued off
688 * before we modify the state below.
689 */
690 ret = wait_for_completion_interruptible_timeout(
691 &commit->hw_done, 10 * HZ);
692 if (ret < 0 && ret != -ERESTARTSYS)
693 goto cleanup;
694
695 if (ret == 0) {
696 ret = -ETIMEDOUT;
697 goto cleanup;
698 }
699 }
700
701 enable = amdgpu_dm_is_valid_crc_source(source);
702 crtc_state = to_dm_crtc_state(crtc->state);
703 spin_lock_irq(&drm_dev->event_lock);
704 cur_crc_src = acrtc->dm_irq_params.crc_src;
705 spin_unlock_irq(&drm_dev->event_lock);
706
707 /*
708 * USER REQ SRC | CURRENT SRC | BEHAVIOR
709 * -----------------------------
710 * None | None | Do nothing
711 * None | CRTC | Disable CRTC CRC, set default to dither
712 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither
713 * None | CRTC DITHER | Disable CRTC CRC
714 * None | DPRX DITHER | Disable DPRX CRC, need 'aux'
715 * CRTC | XXXX | Enable CRTC CRC, no dither
716 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither
717 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither
718 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither
719 */
720 if (dm_need_dp_aux(source, cur_crc_src)) {
721 struct amdgpu_dm_connector *aconn = NULL;
722 struct drm_connector *connector;
723 struct drm_connector_list_iter conn_iter;
724
725 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
726 drm_for_each_connector_iter(connector, &conn_iter) {
727 if (!connector->state || connector->state->crtc != crtc)
728 continue;
729
730 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
731 continue;
732
733 aconn = to_amdgpu_dm_connector(connector);
734 break;
735 }
736 drm_connector_list_iter_end(&conn_iter);
737
738 if (!aconn) {
739 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
740 ret = -EINVAL;
741 goto cleanup;
742 }
743
744 aux = (aconn->mst_output_port) ? &aconn->mst_output_port->aux : &aconn->dm_dp_aux.aux;
745
746 if (!aux) {
747 DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
748 ret = -EINVAL;
749 goto cleanup;
750 }
751
752 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
753 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) {
754 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n");
755 ret = -EINVAL;
756 goto cleanup;
757 }
758
759 }
760
761 /*
762 * Reading the CRC requires the vblank interrupt handler to be
763 * enabled. Keep a reference until CRC capture stops.
764 */
765 enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src);
766 if (!enabled && enable) {
767 ret = drm_crtc_vblank_get(crtc);
768 if (ret)
769 goto cleanup;
770 }
771
772#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
773 /* Reset secure_display when we change crc source from debugfs */
774 amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream);
775#endif
776
777 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
778 ret = -EINVAL;
779 goto cleanup;
780 }
781
782 if (dm_crc_source_should_start_dprx(source, cur_crc_src)) {
783 /* !enabled && enable && is_dprx(source): CRC off → DPRX on */
784 if (drm_dp_start_crc(aux, crtc)) {
785 DRM_DEBUG_DRIVER("dp start crc failed\n");
786 ret = -EINVAL;
787 goto cleanup;
788 }
789 } else if (dm_crc_source_should_stop_dprx(source, cur_crc_src)) {
790 /* enabled && !enable && is_dprx(cur_crc_src): DPRX on → CRC off */
791 drm_crtc_vblank_put(crtc);
792 if (drm_dp_stop_crc(aux)) {
793 DRM_DEBUG_DRIVER("dp stop crc failed\n");
794 ret = -EINVAL;
795 goto cleanup;
796 }
797 } else if (enabled && !enable) {
798 /* Non-DPRX source (e.g. CRTC) turning off: release vblank ref */
799 drm_crtc_vblank_put(crtc);
800 }
801
802 spin_lock_irq(&drm_dev->event_lock);
803 acrtc->dm_irq_params.crc_src = source;
804 spin_unlock_irq(&drm_dev->event_lock);
805
806 /* Reset crc_skipped on dm state */
807 crtc_state->crc_skip_count = 0;
808
809#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
810 /* Initialize phy id mapping table for secure display*/
811 if (dm->secure_display_ctx.op_mode == LEGACY_MODE &&
812 !dm->secure_display_ctx.phy_mapping_updated)
813 update_phy_id_mapping(adev);
814#endif
815
816cleanup:
817 if (commit)
818 drm_crtc_commit_put(commit);
819
820 drm_modeset_unlock(&crtc->mutex);
821
822 return ret;
823}
824EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_crc_source);
825
826/**
827 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC.
828 * @crtc: DRM CRTC object.
829 *
830 * This function should be called at the end of a vblank, when the fb has been
831 * fully processed through the pipe.
832 */
833void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
834{
835 struct dm_crtc_state *crtc_state;
836 struct dc_stream_state *stream_state;
837 struct drm_device *drm_dev;
838 enum amdgpu_dm_pipe_crc_source cur_crc_src;
839 struct amdgpu_crtc *acrtc;
840 uint32_t crcs[3];
841 unsigned long flags;
842
843 if (!crtc || !crtc->state || !crtc->dev)
844 return;
845
846 crtc_state = to_dm_crtc_state(crtc->state);
847 if (!crtc_state->stream)
848 return;
849
850 stream_state = crtc_state->stream;
851 acrtc = to_amdgpu_crtc(crtc);
852 drm_dev = crtc->dev;
853
854 spin_lock_irqsave(&drm_dev->event_lock, flags);
855 cur_crc_src = acrtc->dm_irq_params.crc_src;
856 spin_unlock_irqrestore(&drm_dev->event_lock, flags);
857
858 /* Early return if CRC capture is not enabled. */
859 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src))
860 return;
861
862 /*
863 * Since flipping and crc enablement happen asynchronously, we - more
864 * often than not - will be returning an 'uncooked' crc on first frame.
865 * Probably because hw isn't ready yet. For added security, skip the
866 * first two CRC values.
867 */
868 if (crtc_state->crc_skip_count < 2) {
869 crtc_state->crc_skip_count += 1;
870 return;
871 }
872
873 if (dm_is_crc_source_crtc(cur_crc_src)) {
874 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 0,
875 &crcs[0], &crcs[1], &crcs[2]))
876 return;
877
878 drm_crtc_add_crc_entry(crtc, true,
879 drm_crtc_accurate_vblank_count(crtc), crcs);
880 }
881}
882EXPORT_IF_KUNIT(amdgpu_dm_crtc_handle_crc_irq);
883
884#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
885void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
886{
887 struct drm_device *drm_dev = NULL;
888 enum amdgpu_dm_pipe_crc_source cur_crc_src;
889 struct amdgpu_crtc *acrtc = NULL;
890 struct amdgpu_device *adev = NULL;
891 struct secure_display_crtc_context *crtc_ctx = NULL;
892 bool reset_crc_frame_count[MAX_CRC_WINDOW_NUM] = {false};
893 uint32_t crc_r[MAX_CRC_WINDOW_NUM] = {0};
894 uint32_t crc_g[MAX_CRC_WINDOW_NUM] = {0};
895 uint32_t crc_b[MAX_CRC_WINDOW_NUM] = {0};
896 unsigned long flags1;
897 bool forward_roi_change = false;
898 bool notify_ta = false;
899 struct dc_stream_state *stream_state;
900 int i;
901
902 if (crtc == NULL)
903 return;
904
905 acrtc = to_amdgpu_crtc(crtc);
906 adev = drm_to_adev(crtc->dev);
907 drm_dev = crtc->dev;
908 stream_state = to_dm_crtc_state(crtc->state)->stream;
909
910 spin_lock_irqsave(&drm_dev->event_lock, flags1);
911 cur_crc_src = acrtc->dm_irq_params.crc_src;
912
913 /* Early return if CRC capture is not enabled. */
914 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) ||
915 !dm_is_crc_source_crtc(cur_crc_src)) {
916 spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
917 return;
918 }
919
920 if (!acrtc->dm_irq_params.crc_window_activated) {
921 spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
922 return;
923 }
924
925 crtc_ctx = &adev->dm.secure_display_ctx.crtc_ctx[acrtc->crtc_id];
926 if (WARN_ON(crtc_ctx->crtc != crtc)) {
927 /* We have set the crtc when creating secure_display_crtc_context,
928 * don't expect it to be changed here.
929 */
930 crtc_ctx->crtc = crtc;
931 }
932
933 for (i = 0; i < MAX_CRC_WINDOW_NUM; i++) {
934 struct crc_params crc_window = {
935 .windowa_x_start = acrtc->dm_irq_params.window_param[i].x_start,
936 .windowa_y_start = acrtc->dm_irq_params.window_param[i].y_start,
937 .windowa_x_end = acrtc->dm_irq_params.window_param[i].x_end,
938 .windowa_y_end = acrtc->dm_irq_params.window_param[i].y_end,
939 .windowb_x_start = acrtc->dm_irq_params.window_param[i].x_start,
940 .windowb_y_start = acrtc->dm_irq_params.window_param[i].y_start,
941 .windowb_x_end = acrtc->dm_irq_params.window_param[i].x_end,
942 .windowb_y_end = acrtc->dm_irq_params.window_param[i].y_end,
943 };
944
945 crtc_ctx->roi[i].enable = acrtc->dm_irq_params.window_param[i].enable;
946
947 if (!acrtc->dm_irq_params.window_param[i].enable) {
948 crtc_ctx->crc_info.crc[i].crc_ready = false;
949 continue;
950 }
951
952 if (acrtc->dm_irq_params.window_param[i].skip_frame_cnt) {
953 acrtc->dm_irq_params.window_param[i].skip_frame_cnt -= 1;
954 crtc_ctx->crc_info.crc[i].crc_ready = false;
955 continue;
956 }
957
958 if (acrtc->dm_irq_params.window_param[i].update_win) {
959 crtc_ctx->roi[i].rect.x = crc_window.windowa_x_start;
960 crtc_ctx->roi[i].rect.y = crc_window.windowa_y_start;
961 crtc_ctx->roi[i].rect.width = crc_window.windowa_x_end -
962 crc_window.windowa_x_start;
963 crtc_ctx->roi[i].rect.height = crc_window.windowa_y_end -
964 crc_window.windowa_y_start;
965
966 if (adev->dm.secure_display_ctx.op_mode == LEGACY_MODE)
967 /* forward task to dmub to update ROI */
968 forward_roi_change = true;
969 else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE)
970 /* update ROI via dm*/
971 dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
972 &crc_window, true, true, i, false, (enum crc_poly_mode)acrtc->dm_irq_params.crc_poly_mode);
973
974 reset_crc_frame_count[i] = true;
975
976 acrtc->dm_irq_params.window_param[i].update_win = false;
977
978 /* Statically skip 1 frame, because we may need to wait below things
979 * before sending ROI to dmub:
980 * 1. We defer the work by using system workqueue.
981 * 2. We may need to wait for dc_lock before accessing dmub.
982 */
983 acrtc->dm_irq_params.window_param[i].skip_frame_cnt = 1;
984 crtc_ctx->crc_info.crc[i].crc_ready = false;
985 } else {
986 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, i,
987 &crc_r[i], &crc_g[i], &crc_b[i]))
988 DRM_ERROR("Secure Display: fail to get crc from engine %d\n", i);
989
990 if (adev->dm.secure_display_ctx.op_mode == LEGACY_MODE)
991 /* forward task to psp to read ROI/CRC and output via I2C */
992 notify_ta = true;
993 else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE)
994 /* Avoid ROI window get changed, keep overwriting. */
995 dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
996 &crc_window, true, true, i, false, (enum crc_poly_mode)acrtc->dm_irq_params.crc_poly_mode);
997
998 /* crc ready for psp to read out */
999 crtc_ctx->crc_info.crc[i].crc_ready = true;
1000 }
1001 }
1002
1003 spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
1004
1005 if (forward_roi_change)
1006 schedule_work(&crtc_ctx->forward_roi_work);
1007
1008 if (notify_ta)
1009 schedule_work(&crtc_ctx->notify_ta_work);
1010
1011 spin_lock_irqsave(&crtc_ctx->crc_info.lock, flags1);
1012 for (i = 0; i < MAX_CRC_WINDOW_NUM; i++) {
1013 crtc_ctx->crc_info.crc[i].crc_R = crc_r[i];
1014 crtc_ctx->crc_info.crc[i].crc_G = crc_g[i];
1015 crtc_ctx->crc_info.crc[i].crc_B = crc_b[i];
1016
1017 if (!crtc_ctx->roi[i].enable) {
1018 crtc_ctx->crc_info.crc[i].frame_count = 0;
1019 continue;
1020 }
1021
1022 if (reset_crc_frame_count[i] || crtc_ctx->crc_info.crc[i].frame_count == UINT_MAX)
1023 /* Reset the reference frame count after user update the ROI
1024 * or it reaches the maximum value.
1025 */
1026 crtc_ctx->crc_info.crc[i].frame_count = 0;
1027 else
1028 crtc_ctx->crc_info.crc[i].frame_count += 1;
1029 }
1030 spin_unlock_irqrestore(&crtc_ctx->crc_info.lock, flags1);
1031}
1032
1033void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)
1034{
1035 struct secure_display_crtc_context *crtc_ctx = NULL;
1036 int i;
1037
1038 crtc_ctx = kzalloc_objs(struct secure_display_crtc_context,
1039 adev->mode_info.num_crtc);
1040
1041 if (!crtc_ctx) {
1042 adev->dm.secure_display_ctx.crtc_ctx = NULL;
1043 return;
1044 }
1045
1046 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1047 INIT_WORK(&crtc_ctx[i].forward_roi_work, amdgpu_dm_forward_crc_window);
1048 INIT_WORK(&crtc_ctx[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);
1049 crtc_ctx[i].crtc = &adev->mode_info.crtcs[i]->base;
1050 spin_lock_init(&crtc_ctx[i].crc_info.lock);
1051 }
1052
1053 adev->dm.secure_display_ctx.crtc_ctx = crtc_ctx;
1054
1055 adev->dm.secure_display_ctx.op_mode = DISPLAY_CRC_MODE;
1056}
1057#endif