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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2019 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
28#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
29
30#include "dc_types.h"
31
32struct drm_crtc;
33struct dm_crtc_state;
34struct amdgpu_device;
35
36enum amdgpu_dm_pipe_crc_source {
37 AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
38 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
39 AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
40 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
41 AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
42 AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
43 AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
44};
45
46#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
47#define MAX_CRTC 6
48
49enum secure_display_mode {
50 /* via dmub + psp */
51 LEGACY_MODE = 0,
52 /* driver directly */
53 DISPLAY_CRC_MODE,
54 SECURE_DISPLAY_MODE_MAX,
55};
56
57struct phy_id_mapping {
58 bool assigned;
59 bool is_mst;
60 uint8_t enc_hw_inst;
61 u8 lct;
62 u8 port_num;
63 u8 rad[8];
64};
65
66struct crc_data {
67 uint32_t crc_R;
68 uint32_t crc_G;
69 uint32_t crc_B;
70 uint32_t frame_count;
71 bool crc_ready;
72};
73
74struct crc_info {
75 struct crc_data crc[MAX_CRC_WINDOW_NUM];
76 spinlock_t lock;
77};
78
79struct crc_window_param {
80 uint16_t x_start;
81 uint16_t y_start;
82 uint16_t x_end;
83 uint16_t y_end;
84 /* CRC window is activated or not*/
85 bool enable;
86 /* Update crc window during vertical blank or not */
87 bool update_win;
88 /* skip reading/writing for few frames */
89 int skip_frame_cnt;
90};
91
92struct secure_display_crtc_context {
93 /* work to notify PSP TA*/
94 struct work_struct notify_ta_work;
95
96 /* work to forward ROI to dmcu/dmub */
97 struct work_struct forward_roi_work;
98
99 struct drm_crtc *crtc;
100
101 /* Region of Interest (ROI) */
102 struct crc_window roi[MAX_CRC_WINDOW_NUM];
103
104 struct crc_info crc_info;
105};
106
107struct secure_display_context {
108
109 struct secure_display_crtc_context *crtc_ctx;
110 /* Whether dmub support multiple ROI setting */
111 bool support_mul_roi;
112 enum secure_display_mode op_mode;
113 bool phy_mapping_updated;
114 int phy_id_mapping_cnt;
115 struct phy_id_mapping phy_id_mapping[MAX_CRTC];
116};
117#endif
118
119static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
120{
121 return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
122 (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
123}
124
125/* amdgpu_dm_crc.c */
126#ifdef CONFIG_DEBUG_FS
127int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
128 struct dm_crtc_state *dm_crtc_state,
129 enum amdgpu_dm_pipe_crc_source source);
130int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
131int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
132 const char *src_name,
133 size_t *values_cnt);
134const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
135 size_t *count);
136void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
137#else
138#define amdgpu_dm_crtc_set_crc_source NULL
139#define amdgpu_dm_crtc_verify_crc_source NULL
140#define amdgpu_dm_crtc_get_crc_sources NULL
141#define amdgpu_dm_crtc_handle_crc_irq(x)
142#endif
143
144#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
145bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
146void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);
147void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev);
148#else
149#define amdgpu_dm_crc_window_is_activated(x)
150#define amdgpu_dm_crtc_handle_crc_window_irq(x)
151#define amdgpu_dm_crtc_secure_display_create_contexts(x)
152#endif
153
154#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
155enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source);
156bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src);
157bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src);
158bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src);
159bool dm_need_dp_aux(enum amdgpu_dm_pipe_crc_source source,
160 enum amdgpu_dm_pipe_crc_source cur_crc_src);
161bool dm_crc_source_should_start_dprx(enum amdgpu_dm_pipe_crc_source source,
162 enum amdgpu_dm_pipe_crc_source cur_crc_src);
163bool dm_crc_source_should_stop_dprx(enum amdgpu_dm_pipe_crc_source source,
164 enum amdgpu_dm_pipe_crc_source cur_crc_src);
165#endif
166
167#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */