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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26#include <drm/drm_vblank.h>
27#include <drm/drm_atomic_helper.h>
28
29#include "dc.h"
30#include "amdgpu.h"
31#include "amdgpu_dm_psr.h"
32#include "amdgpu_dm_replay.h"
33#include "amdgpu_dm_crtc.h"
34#include "amdgpu_dm_irq.h"
35#include "amdgpu_dm_plane.h"
36#include "amdgpu_dm_trace.h"
37#include "amdgpu_dm_debugfs.h"
38#include "dm_helpers.h"
39#include "modules/inc/mod_power.h"
40
41#define HPD_DETECTION_PERIOD_uS 2000000
42#define HPD_DETECTION_TIME_uS 100000
43
44void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
45{
46 struct drm_crtc *crtc = &acrtc->base;
47 struct drm_device *dev = crtc->dev;
48 unsigned long flags;
49
50 drm_crtc_handle_vblank(crtc);
51
52 spin_lock_irqsave(&dev->event_lock, flags);
53
54 /* Send completion event for cursor-only commits */
55 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
56 drm_crtc_send_vblank_event(crtc, acrtc->event);
57 drm_crtc_vblank_put(crtc);
58 acrtc->event = NULL;
59 }
60
61 spin_unlock_irqrestore(&dev->event_lock, flags);
62}
63EXPORT_IF_KUNIT(amdgpu_dm_crtc_handle_vblank);
64
65bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
66 struct dc_stream_state *new_stream,
67 struct dc_stream_state *old_stream)
68{
69 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
70}
71EXPORT_IF_KUNIT(amdgpu_dm_crtc_modeset_required);
72
73bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
74
75{
76 return acrtc->dm_irq_params.freesync_config.state ==
77 VRR_STATE_ACTIVE_VARIABLE ||
78 acrtc->dm_irq_params.freesync_config.state ==
79 VRR_STATE_ACTIVE_FIXED;
80}
81EXPORT_IF_KUNIT(amdgpu_dm_crtc_vrr_active_irq);
82
83int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
84{
85 enum dc_irq_source irq_source;
86 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
87 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
88 int rc;
89
90 if (acrtc->otg_inst == -1)
91 return 0;
92
93 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
94
95 rc = amdgpu_dm_irq_set(adev, irq_source, enable) ? 0 : -EBUSY;
96
97 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
98 acrtc->crtc_id, enable ? "en" : "dis", rc);
99 return rc;
100}
101EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_vupdate_irq);
102
103bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
104{
105 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
106 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
107}
108EXPORT_IF_KUNIT(amdgpu_dm_crtc_vrr_active);
109
110/**
111 * amdgpu_dm_crtc_set_static_screen_optimze() - Toggle static screen optimizations.
112 *
113 * @dm: display manager
114 * @stream: DC stream state
115 * @sso_enable: desired static screen optimization state
116 * @allow_sr_entry: whether entry into self-refresh mode is allowed
117 *
118 * This function uses the static-screen optimization state as the trigger to
119 * set/clear the Replay and PSR vsync-related events.
120 */
121void amdgpu_dm_crtc_set_static_screen_optimze(
122 struct amdgpu_display_manager *dm,
123 struct dc_stream_state *stream,
124 bool sso_enable, bool allow_sr_entry)
125{
126 struct dc_link *link = stream->link;
127 bool set_vsync_event = !sso_enable;
128
129 /*
130 * allow_sr_entry gates only entry. A disable request must still set
131 * the vsync events to force Replay and PSR1 out and keep them blocked.
132 */
133 if (sso_enable && !allow_sr_entry)
134 return;
135
136 amdgpu_dm_replay_set_event(dm, stream,
137 set_vsync_event, replay_event_vsync, set_vsync_event);
138
139 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
140 amdgpu_dm_psr_set_event(dm, stream,
141 set_vsync_event, psr_event_vsync, set_vsync_event);
142}
143EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_static_screen_optimze);
144
145bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
146{
147 struct drm_connector *connector;
148 struct drm_connector_list_iter iter;
149 struct drm_device *dev;
150 bool is_headless = true;
151
152 if (adev == NULL)
153 return true;
154
155 dev = adev->dm.ddev;
156
157 drm_connector_list_iter_begin(dev, &iter);
158 drm_for_each_connector_iter(connector, &iter) {
159
160 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
161 continue;
162
163 if (connector->status == connector_status_connected) {
164 is_headless = false;
165 break;
166 }
167 }
168 drm_connector_list_iter_end(&iter);
169 return is_headless;
170}
171EXPORT_IF_KUNIT(amdgpu_dm_is_headless);
172
173STATIC_IFN_KUNIT void amdgpu_dm_idle_worker(struct work_struct *work)
174{
175 struct idle_workqueue *idle_work;
176
177 idle_work = container_of(work, struct idle_workqueue, work);
178 idle_work->dm->idle_workqueue->running = true;
179
180 while (idle_work->enable) {
181 fsleep(HPD_DETECTION_PERIOD_uS);
182 mutex_lock(&idle_work->dm->dc_lock);
183 if (!idle_work->dm->dc->idle_optimizations_allowed) {
184 mutex_unlock(&idle_work->dm->dc_lock);
185 break;
186 }
187 dc_allow_idle_optimizations(idle_work->dm->dc, false);
188
189 mutex_unlock(&idle_work->dm->dc_lock);
190 fsleep(HPD_DETECTION_TIME_uS);
191 mutex_lock(&idle_work->dm->dc_lock);
192
193 if (!amdgpu_dm_is_headless(idle_work->dm->adev) &&
194 !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) {
195 mutex_unlock(&idle_work->dm->dc_lock);
196 break;
197 }
198
199 if (idle_work->enable) {
200 dc_post_update_surfaces_to_stream(idle_work->dm->dc);
201 dc_allow_idle_optimizations(idle_work->dm->dc, true);
202 }
203 mutex_unlock(&idle_work->dm->dc_lock);
204 }
205 idle_work->dm->idle_workqueue->running = false;
206}
207EXPORT_IF_KUNIT(amdgpu_dm_idle_worker);
208
209struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)
210{
211 struct idle_workqueue *idle_work;
212
213 idle_work = kzalloc_obj(*idle_work);
214 if (ZERO_OR_NULL_PTR(idle_work))
215 return NULL;
216
217 idle_work->dm = &adev->dm;
218 idle_work->enable = false;
219 idle_work->running = false;
220 INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker);
221
222 return idle_work;
223}
224EXPORT_IF_KUNIT(idle_create_workqueue);
225
226STATIC_IFN_KUNIT void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
227{
228 struct vblank_control_work *vblank_work =
229 container_of(work, struct vblank_control_work, work);
230 struct amdgpu_display_manager *dm = vblank_work->dm;
231
232 mutex_lock(&dm->dc_lock);
233
234 if (vblank_work->enable) {
235 dm->active_vblank_irq_count++;
236 amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism,
237 DM_ISM_EVENT_EXIT_IDLE_REQUESTED);
238 } else {
239 if (dm->active_vblank_irq_count > 0)
240 dm->active_vblank_irq_count--;
241 amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism,
242 DM_ISM_EVENT_ENTER_IDLE_REQUESTED);
243 }
244
245 mutex_unlock(&dm->dc_lock);
246
247 dc_stream_release(vblank_work->stream);
248
249 kfree(vblank_work);
250}
251EXPORT_IF_KUNIT(amdgpu_dm_crtc_vblank_control_worker);
252
253static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
254{
255 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
256 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
257 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
258 struct amdgpu_display_manager *dm = &adev->dm;
259 struct vblank_control_work *work;
260 int irq_type;
261 int rc = 0;
262
263 if (enable && !acrtc->base.enabled) {
264 drm_dbg_vbl(crtc->dev,
265 "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n",
266 acrtc->crtc_id, acrtc->base.enabled);
267 return -EINVAL;
268 }
269
270 irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
271
272 if (enable && acrtc_state->stream) {
273 struct dc *dc = adev->dm.dc;
274 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
275 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
276 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
277 bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||
278 pr->config.replay_supported;
279
280 /*
281 * IPS & self-refresh feature can cause vblank counter resets between
282 * vblank disable and enable.
283 * It may cause system stuck due to waiting for the vblank counter.
284 * Call this function to estimate missed vblanks by using timestamps and
285 * update the vblank counter in DRM.
286 */
287 if (dc->caps.ips_support &&
288 dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
289 sr_supported && vblank->config.disable_immediate)
290 drm_crtc_vblank_restore(crtc);
291 }
292
293 /*
294 * On DCN, VUPDATE_NO_LOCK is the single OTG interrupt used to deliver
295 * vblank and pageflip completion events, so enable it whenever vblank
296 * is enabled. On DCE, vupdate is only needed in VRR mode.
297 */
298 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) {
299 if (enable) {
300 rc = amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type);
301 drm_dbg_vbl(crtc->dev, "Get vupdate_irq ret=%d\n", rc);
302 } else {
303 rc = amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type);
304 drm_dbg_vbl(crtc->dev, "Put vupdate_irq ret=%d\n", rc);
305 }
306 } else if (dc_supports_vrr(dm->dc->ctx->dce_version)) {
307 if (enable) {
308 /* vblank irq on -> Only need vupdate irq in vrr mode
309 * Not ref-counted since we need explicit enable/disable
310 * for DCE VRR handling
311 */
312 if (amdgpu_dm_crtc_vrr_active(acrtc_state))
313 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
314 } else {
315 /* vblank irq off -> vupdate irq off */
316 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
317 }
318 }
319
320 if (rc)
321 return rc;
322
323 /*
324 * VLINE0 (crtc_irq) and GRPH_PFLIP (pageflip_irq) are only used on
325 * DCE. On DCN, vblank and pageflip completion are delivered from
326 * VUPDATE_NO_LOCK (enabled above), so don't touch them here.
327 */
328 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) {
329 /* crtc vblank or vstartup interrupt */
330 if (enable) {
331 rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type);
332 drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc);
333 } else {
334 rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type);
335 drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc);
336 }
337
338 if (rc)
339 return rc;
340
341 /*
342 * hubp surface flip interrupt
343 *
344 * We have no guarantee that the frontend index maps to the same
345 * backend index - some even map to more than one.
346 *
347 * TODO: Use a different interrupt or check DC itself for the mapping.
348 */
349 if (enable) {
350 rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type);
351 drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc);
352 } else {
353 rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type);
354 drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc);
355 }
356
357 if (rc)
358 return rc;
359 }
360
361#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
362 /* crtc vline0 interrupt, only available on DCN+ */
363 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) {
364 if (enable) {
365 rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type);
366 drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc);
367 } else {
368 rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type);
369 drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc);
370 }
371
372 if (rc)
373 return rc;
374 }
375#endif
376
377 if (amdgpu_in_reset(adev))
378 return 0;
379
380 if (dm->vblank_control_workqueue) {
381 work = kzalloc_obj(*work, GFP_ATOMIC);
382 if (!work)
383 return -ENOMEM;
384
385 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker);
386 work->dm = dm;
387 work->acrtc = acrtc;
388 work->enable = enable;
389
390 if (acrtc_state->stream) {
391 dc_stream_retain(acrtc_state->stream);
392 work->stream = acrtc_state->stream;
393 }
394
395 queue_work(dm->vblank_control_workqueue, &work->work);
396 }
397
398 return 0;
399}
400
401int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
402{
403 return amdgpu_dm_crtc_set_vblank(crtc, true);
404}
405EXPORT_IF_KUNIT(amdgpu_dm_crtc_enable_vblank);
406
407void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
408{
409 amdgpu_dm_crtc_set_vblank(crtc, false);
410}
411EXPORT_IF_KUNIT(amdgpu_dm_crtc_disable_vblank);
412
413STATIC_IFN_KUNIT void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
414 struct drm_crtc_state *state)
415{
416 struct dm_crtc_state *cur = to_dm_crtc_state(state);
417
418 /* TODO Destroy dc_stream objects are stream object is flattened */
419 if (cur->stream)
420 dc_stream_release(cur->stream);
421
422
423 __drm_atomic_helper_crtc_destroy_state(state);
424
425
426 kfree(state);
427}
428EXPORT_IF_KUNIT(amdgpu_dm_crtc_destroy_state);
429
430STATIC_IFN_KUNIT struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
431{
432 struct dm_crtc_state *state, *cur;
433
434 cur = to_dm_crtc_state(crtc->state);
435
436 if (WARN_ON(!crtc->state))
437 return NULL;
438
439 state = kzalloc_obj(*state);
440 if (!state)
441 return NULL;
442
443 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
444
445 if (cur->stream) {
446 state->stream = cur->stream;
447 dc_stream_retain(state->stream);
448 }
449
450 state->active_planes = cur->active_planes;
451 state->vrr_infopacket = cur->vrr_infopacket;
452 state->abm_level = cur->abm_level;
453 state->vrr_supported = cur->vrr_supported;
454 state->freesync_config = cur->freesync_config;
455 state->cm_has_degamma = cur->cm_has_degamma;
456 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
457 state->regamma_tf = cur->regamma_tf;
458 state->crc_skip_count = cur->crc_skip_count;
459 state->mpo_requested = cur->mpo_requested;
460 state->cursor_mode = cur->cursor_mode;
461 /* TODO Duplicate dc_stream after objects are stream object is flattened */
462
463 return &state->base;
464}
465EXPORT_IF_KUNIT(amdgpu_dm_crtc_duplicate_state);
466
467static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
468{
469 /*
470 * amdgpu_dm_ism_fini() is intentionally called in amdgpu_dm_fini().
471 * It must be called before dc_destroy() in amdgpu_dm_fini()
472 * to avoid ISM accessing an invalid dc handle once dc is released.
473 */
474
475 drm_crtc_cleanup(crtc);
476 kfree(crtc);
477}
478
479STATIC_IFN_KUNIT void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
480{
481 struct dm_crtc_state *state;
482
483 state = kzalloc_obj(*state);
484 if (!state)
485 return;
486
487 if (crtc->state)
488 amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
489
490 __drm_atomic_helper_crtc_reset(crtc, &state->base);
491}
492EXPORT_IF_KUNIT(amdgpu_dm_crtc_reset_state);
493
494#ifdef CONFIG_DEBUG_FS
495static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
496{
497 crtc_debugfs_init(crtc);
498
499 return 0;
500}
501#endif
502
503#ifdef AMD_PRIVATE_COLOR
504/**
505 * dm_crtc_additional_color_mgmt - enable additional color properties
506 * @crtc: DRM CRTC
507 *
508 * This function lets the driver enable post-blending CRTC regamma transfer
509 * function property in addition to DRM CRTC gamma LUT. Default value means
510 * linear transfer function, which is the default CRTC gamma LUT behaviour
511 * without this property.
512 */
513static void
514dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
515{
516 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
517
518 if (adev->dm.dc->caps.color.mpc.ogam_ram)
519 drm_object_attach_property(&crtc->base,
520 adev->mode_info.regamma_tf_property,
521 AMDGPU_TRANSFER_FUNCTION_DEFAULT);
522}
523
524static int
525amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
526 struct drm_crtc_state *state,
527 struct drm_property *property,
528 uint64_t val)
529{
530 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
531 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
532
533 if (property == adev->mode_info.regamma_tf_property) {
534 if (acrtc_state->regamma_tf != val) {
535 acrtc_state->regamma_tf = val;
536 acrtc_state->base.color_mgmt_changed |= 1;
537 }
538 } else {
539 drm_dbg_atomic(crtc->dev,
540 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
541 crtc->base.id, crtc->name,
542 property->base.id, property->name);
543 return -EINVAL;
544 }
545
546 return 0;
547}
548
549static int
550amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
551 const struct drm_crtc_state *state,
552 struct drm_property *property,
553 uint64_t *val)
554{
555 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
556 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
557
558 if (property == adev->mode_info.regamma_tf_property)
559 *val = acrtc_state->regamma_tf;
560 else
561 return -EINVAL;
562
563 return 0;
564}
565#endif
566
567/* Implemented only the options currently available for the driver */
568static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
569 .reset = amdgpu_dm_crtc_reset_state,
570 .destroy = amdgpu_dm_crtc_destroy,
571 .set_config = drm_atomic_helper_set_config,
572 .page_flip = drm_atomic_helper_page_flip,
573 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
574 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
575 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
576 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
577 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
578 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
579 .enable_vblank = amdgpu_dm_crtc_enable_vblank,
580 .disable_vblank = amdgpu_dm_crtc_disable_vblank,
581 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
582#if defined(CONFIG_DEBUG_FS)
583 .late_register = amdgpu_dm_crtc_late_register,
584#endif
585#ifdef AMD_PRIVATE_COLOR
586 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
587 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
588#endif
589};
590
591static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
592{
593}
594
595STATIC_IFN_KUNIT int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
596{
597 struct drm_atomic_commit *state = new_crtc_state->state;
598 struct drm_plane *plane;
599 int num_active = 0;
600
601 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
602 struct drm_plane_state *new_plane_state;
603
604 /* Cursor planes are "fake". */
605 if (plane->type == DRM_PLANE_TYPE_CURSOR)
606 continue;
607
608 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
609
610 if (!new_plane_state) {
611 /*
612 * The plane is enable on the CRTC and hasn't changed
613 * state. This means that it previously passed
614 * validation and is therefore enabled.
615 */
616 num_active += 1;
617 continue;
618 }
619
620 /* We need a framebuffer to be considered enabled. */
621 num_active += (new_plane_state->fb != NULL);
622 }
623
624 return num_active;
625}
626EXPORT_IF_KUNIT(amdgpu_dm_crtc_count_crtc_active_planes);
627
628STATIC_IFN_KUNIT void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
629 struct drm_crtc_state *new_crtc_state)
630{
631 struct dm_crtc_state *dm_new_crtc_state =
632 to_dm_crtc_state(new_crtc_state);
633
634 dm_new_crtc_state->active_planes = 0;
635
636 if (!dm_new_crtc_state->stream)
637 return;
638
639 dm_new_crtc_state->active_planes =
640 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);
641}
642EXPORT_IF_KUNIT(amdgpu_dm_crtc_update_crtc_active_planes);
643
644STATIC_IFN_KUNIT bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
645 const struct drm_display_mode *mode,
646 struct drm_display_mode *adjusted_mode)
647{
648 return true;
649}
650EXPORT_IF_KUNIT(amdgpu_dm_crtc_helper_mode_fixup);
651
652static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
653 struct drm_atomic_commit *state)
654{
655 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
656 crtc);
657 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
658 struct dc *dc = adev->dm.dc;
659 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
660 int ret = -EINVAL;
661
662 trace_amdgpu_dm_crtc_atomic_check(crtc_state);
663
664 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
665
666 if (WARN_ON(unlikely(!dm_crtc_state->stream &&
667 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
668 return ret;
669 }
670
671 /*
672 * We require the primary plane to be enabled whenever the CRTC is, otherwise
673 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
674 * planes are disabled, which is not supported by the hardware. And there is legacy
675 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
676 */
677 if (crtc_state->enable &&
678 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
679 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
680 return -EINVAL;
681 }
682
683 /*
684 * Only allow async flips for fast updates that don't change the FB
685 * pitch, the DCC state, rotation, etc.
686 */
687 if (crtc_state->async_flip &&
688 dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
689 drm_dbg_atomic(crtc->dev,
690 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
691 crtc->base.id, crtc->name);
692 return -EINVAL;
693 }
694
695 if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) {
696 struct drm_plane_state *primary_state;
697
698 /* Pull in primary plane for correct VRR handling */
699 primary_state = drm_atomic_get_plane_state(state, crtc->primary);
700 if (IS_ERR(primary_state))
701 return PTR_ERR(primary_state);
702 }
703
704 /* In some use cases, like reset, no stream is attached */
705 if (!dm_crtc_state->stream)
706 return 0;
707
708 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
709 return 0;
710
711 DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
712 return ret;
713}
714
715static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
716 .disable = amdgpu_dm_crtc_helper_disable,
717 .atomic_check = amdgpu_dm_crtc_helper_atomic_check,
718 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup,
719 .get_scanout_position = amdgpu_crtc_get_scanout_position,
720};
721
722/*
723 * This hysteresis filter as configured will:
724 *
725 * * Search through the latest 8[filter_history_size] entries in history,
726 * skipping entries that are older than [filter_old_history_threshold] frames
727 * (0 means ignore age)
728 * * Searches for short-idle-periods that lasted shorter than
729 * 4[filter_num_frames] frames-times
730 * * If there is at least 1[filter_entry_count] short-idle-period, then a delay
731 * of 4[activation_num_delay_frames] will applied before allowing idle
732 * optimizations again.
733 * * An additional delay of 11[sso_num_frames] is applied before enabling
734 * panel-specific optimizations.
735 *
736 * The values were determined empirically on another OS, optimizing for Z8
737 * residency on APUs when running a productivity + web browsing test.
738 *
739 * TODO: Run similar tests to determine if these values are also optimal for
740 * Linux, and if each APU generation benefits differently.
741 */
742static struct amdgpu_dm_ism_config default_ism_config = {
743 .filter_num_frames = 4,
744 .filter_history_size = 8,
745 .filter_entry_count = 1,
746 .activation_num_delay_frames = 4,
747 .filter_old_history_threshold = 0,
748 .sso_num_frames = 11,
749};
750
751int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
752 struct drm_plane *plane,
753 uint32_t crtc_index)
754{
755 struct amdgpu_crtc *acrtc = NULL;
756 struct drm_plane *cursor_plane;
757 bool has_degamma;
758 int res = -ENOMEM;
759
760 cursor_plane = kzalloc_obj(*cursor_plane);
761 if (!cursor_plane)
762 goto fail;
763
764 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
765 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
766
767 acrtc = kzalloc_obj(struct amdgpu_crtc);
768 if (!acrtc)
769 goto fail;
770
771 res = drm_crtc_init_with_planes(
772 dm->ddev,
773 &acrtc->base,
774 plane,
775 cursor_plane,
776 &amdgpu_dm_crtc_funcs, NULL);
777
778 if (res)
779 goto fail;
780
781 amdgpu_dm_ism_init(&acrtc->ism, &default_ism_config);
782
783 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
784
785 /* Create (reset) the plane state */
786 if (acrtc->base.funcs->reset)
787 acrtc->base.funcs->reset(&acrtc->base);
788
789 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
790 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
791
792 acrtc->crtc_id = crtc_index;
793 acrtc->base.enabled = false;
794 acrtc->otg_inst = -1;
795
796 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
797
798 /* Don't enable DRM CRTC degamma property for
799 * 1. DCE since it doesn't support programmable degamma anywhere.
800 * 2. DCN401 since pre-blending degamma LUT doesn't apply to cursor.
801 * Note: DEGAMMA properties are created even if the primary plane has the
802 * COLOR_PIPELINE property. User space can use either the DEGAMMA properties
803 * or the COLOR_PIPELINE property. An atomic commit which attempts to enable
804 * both is rejected.
805 */
806 has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&
807 dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
808
809 drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
810 true, MAX_COLOR_LUT_ENTRIES);
811
812 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
813
814#ifdef AMD_PRIVATE_COLOR
815 dm_crtc_additional_color_mgmt(&acrtc->base);
816#endif
817 return 0;
818
819fail:
820 kfree(acrtc);
821 kfree(cursor_plane);
822 return res;
823}
824