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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2019 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#ifndef AMDGPU_DM_AMDGPU_DM_HDCP_H_
28#define AMDGPU_DM_AMDGPU_DM_HDCP_H_
29
30#include "mod_hdcp.h"
31#include "hdcp.h"
32#include "dc.h"
33#include "dm_cp_psp.h"
34
35/*
36 * Minimal declarations needed by this header.
37 * Full amdgpu/DM definitions come from amdgpu_dm.h included by each .c file.
38 */
39#define AMDGPU_DM_MAX_DISPLAY_COUNT 32
40struct amdgpu_dm_connector;
41
42struct mod_hdcp;
43struct mod_hdcp_link;
44struct mod_hdcp_display;
45struct cp_psp;
46struct amdgpu_device;
47struct psp_context;
48struct file;
49struct kobject;
50struct bin_attribute;
51struct mod_hdcp_atomic_op_i2c;
52struct mod_hdcp_atomic_op_aux;
53
54struct hdcp_workqueue {
55 struct work_struct cpirq_work;
56 struct work_struct property_update_work;
57 struct delayed_work callback_dwork;
58 struct delayed_work watchdog_timer_dwork;
59 struct delayed_work property_validate_dwork;
60 struct amdgpu_dm_connector *aconnector[AMDGPU_DM_MAX_DISPLAY_COUNT];
61 struct mutex mutex;
62
63 struct mod_hdcp hdcp;
64 struct mod_hdcp_output output;
65 struct mod_hdcp_display display;
66 struct mod_hdcp_link link;
67
68 enum mod_hdcp_encryption_status encryption_status[AMDGPU_DM_MAX_DISPLAY_COUNT];
69 /* when display is unplugged from mst hub, connctor will be
70 * destroyed within dm_dp_mst_connector_destroy. connector
71 * hdcp perperties, like type, undesired, desired, enabled,
72 * will be lost. So, save hdcp properties into hdcp_work within
73 * amdgpu_dm_atomic_commit_tail. if the same display is
74 * plugged back with same display index, its hdcp properties
75 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
76 */
77 /* un-desired, desired, enabled */
78 unsigned int content_protection[AMDGPU_DM_MAX_DISPLAY_COUNT];
79 /* hdcp1.x, hdcp2.x */
80 unsigned int hdcp_content_type[AMDGPU_DM_MAX_DISPLAY_COUNT];
81
82 uint8_t max_link;
83
84 uint8_t *srm;
85 uint8_t *srm_temp;
86 uint32_t srm_version;
87 uint32_t srm_size;
88 struct bin_attribute attr;
89};
90
91void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
92 unsigned int link_index,
93 struct amdgpu_dm_connector *aconnector,
94 uint8_t content_type,
95 bool enable_encryption);
96
97void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
98void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index);
99void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *work);
100
101struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc);
102
103#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
104void process_output(struct hdcp_workqueue *hdcp_work);
105bool hdcp_get_content_protection_from_status(
106 unsigned int hdcp_content_type,
107 enum mod_hdcp_encryption_status encryption_status,
108 unsigned int *content_protection);
109void hdcp_get_link_display_adjustments(
110 bool enable_encryption,
111 u8 content_type,
112 bool fused_io_supported,
113 bool hdcp_lc_force_fw_enable,
114 bool hdcp_lc_enable_sw_fallback,
115 struct mod_hdcp_link_adjustment *link_adjust,
116 struct mod_hdcp_display_adjustment *display_adjust);
117void hdcp_update_display_encryption_control(struct hdcp_workqueue *hdcp_work,
118 struct hdcp_workqueue *hdcp_w,
119 unsigned int conn_index,
120 bool enable_encryption);
121void event_property_update(struct work_struct *work);
122void event_property_validate(struct work_struct *work);
123void event_callback(struct work_struct *work);
124void event_watchdog_timer(struct work_struct *work);
125void event_cpirq(struct work_struct *work);
126void link_lock(struct hdcp_workqueue *work, bool lock);
127void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index,
128 struct amdgpu_dm_connector *aconnector);
129uint8_t *psp_get_srm(struct psp_context *psp, uint32_t *srm_version, uint32_t *srm_size);
130int psp_set_srm(struct psp_context *psp, u8 *srm, uint32_t srm_size, uint32_t *srm_version);
131bool enable_assr(void *handle, struct dc_link *link);
132void update_config(void *handle, struct cp_psp_stream_config *config);
133ssize_t srm_data_write(struct file *filp, struct kobject *kobj,
134 const struct bin_attribute *bin_attr, char *buffer,
135 loff_t pos, size_t count);
136ssize_t srm_data_read(struct file *filp, struct kobject *kobj,
137 const struct bin_attribute *bin_attr, char *buffer,
138 loff_t pos, size_t count);
139bool lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size);
140bool lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size);
141bool lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size);
142bool lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size);
143bool lp_atomic_write_poll_read_i2c(void *handle,
144 const struct mod_hdcp_atomic_op_i2c *write,
145 const struct mod_hdcp_atomic_op_i2c *poll,
146 struct mod_hdcp_atomic_op_i2c *read,
147 uint32_t poll_timeout_us, uint8_t poll_mask_msb);
148bool lp_atomic_write_poll_read_aux(void *handle,
149 const struct mod_hdcp_atomic_op_aux *write,
150 const struct mod_hdcp_atomic_op_aux *poll,
151 struct mod_hdcp_atomic_op_aux *read,
152 uint32_t poll_timeout_us, uint8_t poll_mask_msb);
153#endif
154
155#endif /* AMDGPU_DM_AMDGPU_DM_HDCP_H_ */