projects/linux·blob master · refs

1914 lines · 54.5 KiB

1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#include <acpi/video.h>
28
29#include <linux/string.h>
30#include <linux/acpi.h>
31#include <linux/i2c.h>
32
33#include <drm/drm_atomic.h>
34#include <drm/drm_probe_helper.h>
35#include <drm/amdgpu_drm.h>
36#include <drm/drm_edid.h>
37#include <drm/drm_fixed.h>
38
39#include "dm_services.h"
40#include "amdgpu.h"
41#include "dc.h"
42#include "amdgpu_dm.h"
43#include "amdgpu_dm_irq.h"
44#include "amdgpu_dm_mst_types.h"
45#include "dpcd_defs.h"
46#include "dc/inc/core_types.h"
47
48#include "dm_helpers.h"
49#include "ddc_service_types.h"
50#include "clk_mgr.h"
51#include "amdgpu_dm_helpers.h"
52
53#define MCCS_DEST_ADDR (0x6E >> 1)
54#define MCCS_SRC_ADDR 0x51
55#define MCCS_LENGTH_OFFSET 0x80
56#define MCCS_MAX_DATA_SIZE 0x20
57
58enum mccs_op_code {
59 MCCS_OP_CODE_VCP_REQUEST = 0x01,
60 MCCS_OP_CODE_VCP_REPLY = 0x02,
61 MCCS_OP_CODE_VCP_SET = 0x03,
62 MCCS_OP_CODE_VCP_RESET = 0x09,
63 MCCS_OP_CODE_CAP_REQUEST = 0xF3,
64 MCCS_OP_CODE_CAP_REPLY = 0xE3
65};
66
67enum mccs_op_buff_size {
68 MCCS_OP_BUFF_SIZE__WR_VCP_REQUEST = 5,
69 MCCS_OP_BUFF_SIZE_RD_VCP_REQUEST = 11,
70 MCCS_OP_BUFF_SIZE_WR_VCP_SET = 7,
71};
72
73enum vcp_reply_mask {
74 FREESYNC_SUPPORTED = 0x1
75};
76
77union vcp_reply {
78 struct {
79 unsigned char src_addr;
80 unsigned char length; /* Length is offset by MccsLengthOffs = 0x80 */
81 unsigned char reply_op_code; /* Should return MCCS_OP_CODE_VCP_REPLY = 0x02 */
82 unsigned char result_code; /* 00h No Error, 01h Unsupported VCP Code */
83 unsigned char request_code; /* Should return mccs vcp code sent in the vcp request */
84 unsigned char type_code; /* VCP type code: 00h Set parameter, 01h Momentary */
85 unsigned char max_value[2]; /* 2 bytes returning max value current value */
86 unsigned char present_value[2]; /* NOTE: Byte0 is MSB, Byte1 is LSB */
87 unsigned char check_sum;
88 } bytes;
89 unsigned char raw[11];
90};
91
92STATIC_IFN_KUNIT u32 edid_extract_panel_id(struct edid *edid)
93{
94 return (u32)edid->mfg_id[0] << 24 |
95 (u32)edid->mfg_id[1] << 16 |
96 (u32)EDID_PRODUCT_ID(edid);
97}
98EXPORT_IF_KUNIT(edid_extract_panel_id);
99
100STATIC_IFN_KUNIT void apply_edid_quirks(struct dc_link *link, struct edid *edid,
101 struct dc_edid_caps *edid_caps)
102{
103 struct amdgpu_dm_connector *aconnector = link->priv;
104 struct drm_device *dev = aconnector->base.dev;
105 uint32_t panel_id = edid_extract_panel_id(edid);
106
107 switch (panel_id) {
108 /* Workaround for monitors that need a delay after detecting the link */
109 case drm_edid_encode_panel_id('G', 'B', 'T', 0x3215):
110 drm_dbg_driver(dev, "Add 10s delay for link detection for panel id %X\n", panel_id);
111 edid_caps->panel_patch.wait_after_dpcd_poweroff_ms = 10000;
112 break;
113 /* Workaround for some monitors which does not work well with FAMS */
114 case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
115 case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
116 case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
117 drm_dbg_driver(dev, "Disabling FAMS on monitor with panel id %X\n", panel_id);
118 edid_caps->panel_patch.disable_fams = true;
119 break;
120 /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */
121 case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
122 case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
123 case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A):
124 case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1):
125 case drm_edid_encode_panel_id('M', 'S', 'F', 0x1003):
126 drm_dbg_driver(dev, "Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);
127 edid_caps->panel_patch.remove_sink_ext_caps = true;
128 break;
129 case drm_edid_encode_panel_id('S', 'D', 'C', 0x4154):
130 case drm_edid_encode_panel_id('S', 'D', 'C', 0x4171):
131 drm_dbg_driver(dev, "Disabling VSC on monitor with panel id %X\n", panel_id);
132 edid_caps->panel_patch.disable_colorimetry = true;
133 break;
134 /* Workaround for monitors that get corrupted by the PHY SSC reduction */
135 case drm_edid_encode_panel_id('D', 'E', 'L', 0x4147):
136 drm_dbg_driver(dev, "Skip PHY SSC reduction on panel id %X\n", panel_id);
137 link->wa_flags.skip_phy_ssc_reduction = true;
138 break;
139 /*
140 * Workaround for Apple Studio Display which exposes a 2x1 tiled panel
141 * over two SST DP links. Hide the secondary tile from userspace so
142 * compositors drive a single 5K stream on the primary link only.
143 */
144 case drm_edid_encode_panel_id('A', 'P', 'P', 0xAE3A):
145 case drm_edid_encode_panel_id('A', 'P', 'P', 0xAE42):
146 case drm_edid_encode_panel_id('A', 'P', 'P', 0xAE46):
147 drm_dbg_driver(dev, "Hiding secondary tile on panel id %X\n", panel_id);
148 edid_caps->panel_patch.disable_second_tile = true;
149 break;
150 default:
151 return;
152 }
153}
154EXPORT_IF_KUNIT(apply_edid_quirks);
155
156/**
157 * dm_helpers_parse_edid_caps() - Parse edid caps
158 *
159 * @link: current detected link
160 * @edid: [in] pointer to edid
161 * @edid_caps: [in] pointer to edid caps
162 *
163 * Return: void
164 */
165enum dc_edid_status dm_helpers_parse_edid_caps(
166 struct dc_link *link,
167 const struct dc_edid *edid,
168 struct dc_edid_caps *edid_caps)
169{
170 struct amdgpu_dm_connector *aconnector = link->priv;
171 struct drm_connector *connector = &aconnector->base;
172 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
173 struct cea_sad *sads;
174 int sad_count = -1;
175 int sadb_count = -1;
176 int i = 0;
177 uint8_t *sadb = NULL;
178
179 enum dc_edid_status result = EDID_OK;
180
181 if (!edid_caps || !edid)
182 return EDID_BAD_INPUT;
183
184 if (!drm_edid_is_valid(edid_buf))
185 result = EDID_BAD_CHECKSUM;
186
187 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
188 ((uint16_t) edid_buf->mfg_id[1])<<8;
189 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
190 ((uint16_t) edid_buf->prod_code[1])<<8;
191 edid_caps->serial_number = edid_buf->serial;
192 edid_caps->manufacture_week = edid_buf->mfg_week;
193 edid_caps->manufacture_year = edid_buf->mfg_year;
194 edid_caps->analog = !(edid_buf->input & DRM_EDID_INPUT_DIGITAL);
195
196 drm_edid_get_monitor_name(edid_buf,
197 edid_caps->display_name,
198 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
199
200 edid_caps->edid_hdmi = connector->display_info.is_hdmi;
201
202 if (edid_caps->edid_hdmi) {
203 edid_caps->qs_bit = connector->display_info.rgb_quant_range_selectable;
204 populate_hdmi_info_from_connector(link->dc->config.enable_frl, &connector->display_info.hdmi, edid_caps);
205 drm_dbg_driver(connector->dev, "%s: HDMI_FRL [%s] max_frl_rate %d\n", __func__, connector->name, edid_caps->max_frl_rate);
206 if (edid_caps->frl_dsc_support)
207 drm_dbg_driver(connector->dev, "%s: HDMI_FRL_DSC [%s] frl_dsc_10bpc %d, frl_dsc_12bpc %d, frl_dsc_all_bpp %d, frl_dsc_native_420 %d, frl_dsc_max_slices %d, frl_dsc_max_frl_rate %d, frl_dsc_total_chunk_kbytes %d\n",
208 __func__, connector->name, edid_caps->frl_dsc_10bpc, edid_caps->frl_dsc_12bpc, \
209 edid_caps->frl_dsc_all_bpp, edid_caps->frl_dsc_native_420, edid_caps->frl_dsc_max_slices, \
210 edid_caps->frl_dsc_max_frl_rate, edid_caps->frl_dsc_total_chunk_kbytes);
211 if (aconnector->hdmi_comp_auto) {
212 edid_caps->panel_patch.hdmi_comp_auto = true;
213 link->ctx->dc->debug.force_frl_max = true;
214 link->ctx->dc->debug.force_frl_dsc = true;
215 drm_dbg_driver(connector->dev, "%s: HDMI_FRL [%s] hdmi_comp_auto --> enabled\n", __func__, connector->name);
216 }
217 }
218
219 apply_edid_quirks(link, edid_buf, edid_caps);
220
221 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
222 if (sad_count <= 0)
223 return result;
224
225 edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
226 for (i = 0; i < edid_caps->audio_mode_count; ++i) {
227 struct cea_sad *sad = &sads[i];
228
229 edid_caps->audio_modes[i].format_code = sad->format;
230 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
231 edid_caps->audio_modes[i].sample_rate = sad->freq;
232 edid_caps->audio_modes[i].sample_size = sad->byte2;
233 }
234
235 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
236
237 if (sadb_count < 0) {
238 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
239 sadb_count = 0;
240 }
241
242 if (sadb_count)
243 edid_caps->speaker_flags = sadb[0];
244 else
245 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
246
247 kfree(sads);
248 kfree(sadb);
249
250 return result;
251}
252EXPORT_IF_KUNIT(dm_helpers_parse_edid_caps);
253
254STATIC_IFN_KUNIT void
255fill_dc_mst_payload_table_from_drm(struct dc_link *link,
256 bool enable,
257 struct drm_dp_mst_atomic_payload *target_payload,
258 struct dc_dp_mst_stream_allocation_table *table)
259{
260 struct dc_dp_mst_stream_allocation_table new_table = { 0 };
261 struct dc_dp_mst_stream_allocation *sa;
262 struct link_mst_stream_allocation_table copy_of_link_table =
263 link->mst_stream_alloc_table;
264
265 int i;
266 int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
267 struct link_mst_stream_allocation *dc_alloc;
268
269 /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
270 if (enable) {
271 dc_alloc =
272 &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
273 dc_alloc->vcp_id = target_payload->vcpi;
274 dc_alloc->slot_count = target_payload->time_slots;
275 } else {
276 for (i = 0; i < copy_of_link_table.stream_count; i++) {
277 dc_alloc =
278 &copy_of_link_table.stream_allocations[i];
279
280 if (dc_alloc->vcp_id == target_payload->vcpi) {
281 dc_alloc->vcp_id = 0;
282 dc_alloc->slot_count = 0;
283 break;
284 }
285 }
286 ASSERT(i != copy_of_link_table.stream_count);
287 }
288
289 /* Fill payload info*/
290 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
291 dc_alloc =
292 &copy_of_link_table.stream_allocations[i];
293 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
294 sa = &new_table.stream_allocations[new_table.stream_count];
295 sa->slot_count = dc_alloc->slot_count;
296 sa->vcp_id = dc_alloc->vcp_id;
297 new_table.stream_count++;
298 }
299 }
300
301 /* Overwrite the old table */
302 *table = new_table;
303}
304EXPORT_IF_KUNIT(fill_dc_mst_payload_table_from_drm);
305
306void dm_helpers_dp_update_branch_info(
307 struct dc_context *ctx,
308 const struct dc_link *link)
309{}
310EXPORT_IF_KUNIT(dm_helpers_dp_update_branch_info);
311
312STATIC_IFN_KUNIT void dm_helpers_construct_old_payload(
313 struct drm_dp_mst_topology_mgr *mgr,
314 struct drm_dp_mst_topology_state *mst_state,
315 struct drm_dp_mst_atomic_payload *new_payload,
316 struct drm_dp_mst_atomic_payload *old_payload)
317{
318 struct drm_dp_mst_atomic_payload *pos;
319 int pbn_per_slot = dfixed_trunc(mst_state->pbn_div);
320 u8 next_payload_vc_start = mgr->next_start_slot;
321 u8 payload_vc_start = new_payload->vc_start_slot;
322 u8 allocated_time_slots;
323
324 *old_payload = *new_payload;
325
326 /* Set correct time_slots/PBN of old payload.
327 * other fields (delete & dsc_enabled) in
328 * struct drm_dp_mst_atomic_payload are don't care fields
329 * while calling drm_dp_remove_payload_part2()
330 */
331 list_for_each_entry(pos, &mst_state->payloads, next) {
332 if (pos != new_payload &&
333 pos->vc_start_slot > payload_vc_start &&
334 pos->vc_start_slot < next_payload_vc_start)
335 next_payload_vc_start = pos->vc_start_slot;
336 }
337
338 allocated_time_slots = next_payload_vc_start - payload_vc_start;
339
340 old_payload->time_slots = allocated_time_slots;
341 old_payload->pbn = allocated_time_slots * pbn_per_slot;
342}
343EXPORT_IF_KUNIT(dm_helpers_construct_old_payload);
344
345/*
346 * Writes payload allocation table in immediate downstream device.
347 */
348bool dm_helpers_dp_mst_write_payload_allocation_table(
349 struct dc_context *ctx,
350 const struct dc_stream_state *stream,
351 struct dc_dp_mst_stream_allocation_table *proposed_table,
352 bool enable)
353{
354 struct amdgpu_dm_connector *aconnector;
355 struct drm_dp_mst_topology_state *mst_state;
356 struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
357 struct drm_dp_mst_topology_mgr *mst_mgr;
358
359 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
360 /* Accessing the connector state is required for vcpi_slots allocation
361 * and directly relies on behaviour in commit check
362 * that blocks before commit guaranteeing that the state
363 * is not gonna be swapped while still in use in commit tail
364 */
365
366 if (!aconnector || !aconnector->mst_root)
367 return false;
368
369 mst_mgr = &aconnector->mst_root->mst_mgr;
370 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
371 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
372
373 if (enable) {
374 target_payload = new_payload;
375
376 /* It's OK for this to fail */
377 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
378 } else {
379 /* construct old payload by VCPI*/
380 dm_helpers_construct_old_payload(mst_mgr, mst_state,
381 new_payload, &old_payload);
382 target_payload = &old_payload;
383
384 drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload);
385 }
386
387 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
388 * AUX message. The sequence is slot 1-63 allocated sequence for each
389 * stream. AMD ASIC stream slot allocation should follow the same
390 * sequence. copy DRM MST allocation to dc
391 */
392 fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
393
394 return true;
395}
396EXPORT_IF_KUNIT(dm_helpers_dp_mst_write_payload_allocation_table);
397
398/*
399 * poll pending down reply
400 */
401void dm_helpers_dp_mst_poll_pending_down_reply(
402 struct dc_context *ctx,
403 const struct dc_link *link)
404{}
405EXPORT_IF_KUNIT(dm_helpers_dp_mst_poll_pending_down_reply);
406
407/*
408 * Clear payload allocation table before enable MST DP link.
409 */
410void dm_helpers_dp_mst_clear_payload_allocation_table(
411 struct dc_context *ctx,
412 const struct dc_link *link)
413{}
414EXPORT_IF_KUNIT(dm_helpers_dp_mst_clear_payload_allocation_table);
415
416/*
417 * Polls for ACT (allocation change trigger) handled and sends
418 * ALLOCATE_PAYLOAD message.
419 */
420enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
421 struct dc_context *ctx,
422 const struct dc_stream_state *stream)
423{
424 struct amdgpu_dm_connector *aconnector;
425 struct drm_dp_mst_topology_mgr *mst_mgr;
426 int ret;
427
428 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
429
430 if (!aconnector || !aconnector->mst_root)
431 return ACT_FAILED;
432
433 mst_mgr = &aconnector->mst_root->mst_mgr;
434
435 if (!mst_mgr->mst_state)
436 return ACT_FAILED;
437
438 ret = drm_dp_check_act_status(mst_mgr);
439
440 if (ret)
441 return ACT_FAILED;
442
443 return ACT_SUCCESS;
444}
445EXPORT_IF_KUNIT(dm_helpers_dp_mst_poll_for_allocation_change_trigger);
446
447void dm_helpers_dp_mst_send_payload_allocation(
448 struct dc_context *ctx,
449 const struct dc_stream_state *stream)
450{
451 struct amdgpu_dm_connector *aconnector;
452 struct drm_dp_mst_topology_state *mst_state;
453 struct drm_dp_mst_topology_mgr *mst_mgr;
454 struct drm_dp_mst_atomic_payload *new_payload;
455 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
456 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
457 int ret = 0;
458
459 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
460
461 if (!aconnector || !aconnector->mst_root)
462 return;
463
464 mst_mgr = &aconnector->mst_root->mst_mgr;
465 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
466 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
467
468 ret = drm_dp_add_payload_part2(mst_mgr, new_payload);
469
470 if (ret) {
471 amdgpu_dm_set_mst_status(&aconnector->mst_status,
472 set_flag, false);
473 } else {
474 amdgpu_dm_set_mst_status(&aconnector->mst_status,
475 set_flag, true);
476 amdgpu_dm_set_mst_status(&aconnector->mst_status,
477 clr_flag, false);
478 }
479}
480EXPORT_IF_KUNIT(dm_helpers_dp_mst_send_payload_allocation);
481
482void dm_helpers_dp_mst_update_mst_mgr_for_deallocation(
483 struct dc_context *ctx,
484 const struct dc_stream_state *stream)
485{
486 struct amdgpu_dm_connector *aconnector;
487 struct drm_dp_mst_topology_state *mst_state;
488 struct drm_dp_mst_topology_mgr *mst_mgr;
489 struct drm_dp_mst_atomic_payload *new_payload, old_payload;
490 enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
491 enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
492
493 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
494
495 if (!aconnector || !aconnector->mst_root)
496 return;
497
498 mst_mgr = &aconnector->mst_root->mst_mgr;
499 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
500 new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
501 dm_helpers_construct_old_payload(mst_mgr, mst_state,
502 new_payload, &old_payload);
503
504 drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload);
505
506 amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true);
507 amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false);
508 }
509EXPORT_IF_KUNIT(dm_helpers_dp_mst_update_mst_mgr_for_deallocation);
510
511void dm_dtn_log_begin(struct dc_context *ctx,
512 struct dc_log_buffer_ctx *log_ctx)
513{
514 static const char msg[] = "[dtn begin]\n";
515
516 if (!log_ctx) {
517 pr_info("%s", msg);
518 return;
519 }
520
521 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
522}
523EXPORT_IF_KUNIT(dm_dtn_log_begin);
524
525__printf(3, 4)
526void dm_dtn_log_append_v(struct dc_context *ctx,
527 struct dc_log_buffer_ctx *log_ctx,
528 const char *msg, ...)
529{
530 va_list args;
531 size_t total;
532 int n;
533
534 if (!log_ctx) {
535 /* No context, redirect to dmesg. */
536 struct va_format vaf;
537
538 vaf.fmt = msg;
539 vaf.va = &args;
540
541 va_start(args, msg);
542 pr_info("%pV", &vaf);
543 va_end(args);
544
545 return;
546 }
547
548 /* Measure the output. */
549 va_start(args, msg);
550 n = vsnprintf(NULL, 0, msg, args);
551 va_end(args);
552
553 if (n <= 0)
554 return;
555
556 /* Reallocate the string buffer as needed. */
557 total = log_ctx->pos + n + 1;
558
559 if (total > log_ctx->size) {
560 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);
561
562 if (buf) {
563 memcpy(buf, log_ctx->buf, log_ctx->pos);
564 kfree(log_ctx->buf);
565
566 log_ctx->buf = buf;
567 log_ctx->size = total;
568 }
569 }
570
571 if (!log_ctx->buf)
572 return;
573
574 /* Write the formatted string to the log buffer. */
575 va_start(args, msg);
576 n = vscnprintf(
577 log_ctx->buf + log_ctx->pos,
578 log_ctx->size - log_ctx->pos,
579 msg,
580 args);
581 va_end(args);
582
583 if (n > 0)
584 log_ctx->pos += n;
585}
586EXPORT_IF_KUNIT(dm_dtn_log_append_v);
587
588void dm_dtn_log_end(struct dc_context *ctx,
589 struct dc_log_buffer_ctx *log_ctx)
590{
591 static const char msg[] = "[dtn end]\n";
592
593 if (!log_ctx) {
594 pr_info("%s", msg);
595 return;
596 }
597
598 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
599}
600EXPORT_IF_KUNIT(dm_dtn_log_end);
601
602bool dm_helpers_dp_mst_start_top_mgr(
603 struct dc_context *ctx,
604 const struct dc_link *link,
605 bool boot)
606{
607 struct amdgpu_dm_connector *aconnector = link->priv;
608 int ret;
609
610 if (!aconnector) {
611 DRM_ERROR("Failed to find connector for link!");
612 return false;
613 }
614
615 if (boot) {
616 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
617 aconnector, aconnector->base.base.id);
618 return true;
619 }
620
621 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
622 aconnector, aconnector->base.base.id);
623
624 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
625 if (ret < 0) {
626 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
627 return false;
628 }
629
630 DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
631 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
632
633 return true;
634}
635EXPORT_IF_KUNIT(dm_helpers_dp_mst_start_top_mgr);
636
637bool dm_helpers_dp_mst_stop_top_mgr(
638 struct dc_context *ctx,
639 struct dc_link *link)
640{
641 struct amdgpu_dm_connector *aconnector = link->priv;
642
643 if (!aconnector) {
644 DRM_ERROR("Failed to find connector for link!");
645 return false;
646 }
647
648 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
649 aconnector, aconnector->base.base.id);
650
651 if (aconnector->mst_mgr.mst_state == true) {
652 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
653 link->cur_link_settings.lane_count = 0;
654 }
655
656 return false;
657}
658EXPORT_IF_KUNIT(dm_helpers_dp_mst_stop_top_mgr);
659
660bool dm_helpers_dp_read_dpcd(
661 struct dc_context *ctx,
662 const struct dc_link *link,
663 uint32_t address,
664 uint8_t *data,
665 uint32_t size)
666{
667
668 struct amdgpu_dm_connector *aconnector = link->priv;
669
670 if (!aconnector)
671 return false;
672
673 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,
674 size) == size;
675}
676EXPORT_IF_KUNIT(dm_helpers_dp_read_dpcd);
677
678bool dm_helpers_dp_write_dpcd(
679 struct dc_context *ctx,
680 const struct dc_link *link,
681 uint32_t address,
682 const uint8_t *data,
683 uint32_t size)
684{
685 struct amdgpu_dm_connector *aconnector = link->priv;
686
687 if (!aconnector)
688 return false;
689
690 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
691 address, (uint8_t *)data, size) > 0;
692}
693EXPORT_IF_KUNIT(dm_helpers_dp_write_dpcd);
694
695bool dm_helpers_submit_i2c(
696 struct dc_context *ctx,
697 const struct dc_link *link,
698 struct i2c_command *cmd)
699{
700 struct amdgpu_dm_connector *aconnector = link->priv;
701 struct i2c_msg *msgs;
702 int i = 0;
703 int num = cmd->number_of_payloads;
704 bool result;
705
706 if (!aconnector) {
707 DRM_ERROR("Failed to find connector for link!");
708 return false;
709 }
710
711 msgs = kzalloc_objs(struct i2c_msg, num);
712
713 if (!msgs)
714 return false;
715
716 for (i = 0; i < num; i++) {
717 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
718 msgs[i].addr = cmd->payloads[i].address;
719 msgs[i].len = cmd->payloads[i].length;
720 msgs[i].buf = cmd->payloads[i].data;
721 }
722
723 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
724
725 kfree(msgs);
726
727 return result;
728}
729EXPORT_IF_KUNIT(dm_helpers_submit_i2c);
730
731bool dm_helpers_execute_fused_io(
732 struct dc_context *ctx,
733 struct dc_link *link,
734 union dmub_rb_cmd *commands,
735 uint8_t count,
736 uint32_t timeout_us
737)
738{
739 struct amdgpu_device *dev = ctx->driver_context;
740
741 return amdgpu_dm_execute_fused_io(dev, link, commands, count, timeout_us);
742}
743EXPORT_IF_KUNIT(dm_helpers_execute_fused_io);
744
745STATIC_IFN_KUNIT bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
746 bool is_write_cmd,
747 unsigned char cmd,
748 unsigned int length,
749 unsigned int offset,
750 unsigned char *data)
751{
752 bool success = false;
753 unsigned char rc_data[16] = {0};
754 unsigned char rc_offset[4] = {0};
755 unsigned char rc_length[2] = {0};
756 unsigned char rc_cmd = 0;
757 unsigned char rc_result = 0xFF;
758 unsigned char i = 0;
759 int ret;
760
761 if (is_write_cmd) {
762 // write rc data
763 memmove(rc_data, data, length);
764 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
765 if (ret < 0)
766 goto err;
767 }
768
769 // write rc offset
770 rc_offset[0] = (unsigned char) offset & 0xFF;
771 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
772 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
773 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
774 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
775 if (ret < 0)
776 goto err;
777
778 // write rc length
779 rc_length[0] = (unsigned char) length & 0xFF;
780 rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
781 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
782 if (ret < 0)
783 goto err;
784
785 // write rc cmd
786 rc_cmd = cmd | 0x80;
787 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
788 if (ret < 0)
789 goto err;
790
791 // poll until active is 0
792 for (i = 0; i < 10; i++) {
793 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
794 if (rc_cmd == cmd)
795 // active is 0
796 break;
797 msleep(10);
798 }
799
800 // read rc result
801 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
802 success = (rc_result == 0);
803
804 if (success && !is_write_cmd) {
805 // read rc data
806 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
807 }
808
809 drm_dbg_dp(aux->drm_dev, "success = %d\n", success);
810
811 return success;
812
813err:
814 DRM_ERROR("%s: write cmd ..., err = %d\n", __func__, ret);
815 return false;
816}
817EXPORT_IF_KUNIT(execute_synaptics_rc_command);
818
819STATIC_IFN_KUNIT void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
820{
821 unsigned char data[16] = {0};
822
823 drm_dbg_dp(aux->drm_dev, "Start\n");
824
825 // Step 2
826 data[0] = 'P';
827 data[1] = 'R';
828 data[2] = 'I';
829 data[3] = 'U';
830 data[4] = 'S';
831
832 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
833 return;
834
835 // Step 3 and 4
836 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
837 return;
838
839 data[0] &= (~(1 << 1)); // set bit 1 to 0
840 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
841 return;
842
843 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
844 return;
845
846 data[0] &= (~(1 << 1)); // set bit 1 to 0
847 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
848 return;
849
850 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
851 return;
852
853 data[0] &= (~(1 << 1)); // set bit 1 to 0
854 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
855 return;
856
857 // Step 3 and 5
858 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
859 return;
860
861 data[0] |= (1 << 1); // set bit 1 to 1
862 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
863 return;
864
865 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
866 return;
867
868 data[0] |= (1 << 1); // set bit 1 to 1
869
870 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
871 return;
872
873 data[0] |= (1 << 1); // set bit 1 to 1
874 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
875 return;
876
877 // Step 6
878 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
879 return;
880
881 drm_dbg_dp(aux->drm_dev, "Done\n");
882}
883EXPORT_IF_KUNIT(apply_synaptics_fifo_reset_wa);
884
885/* MST Dock */
886static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
887
888STATIC_IFN_KUNIT uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
889 struct drm_dp_aux *aux,
890 const struct dc_stream_state *stream,
891 bool enable)
892{
893 uint8_t ret = 0;
894
895 drm_dbg_dp(aux->drm_dev,
896 "MST_DSC Configure DSC to non-virtual dpcd synaptics\n");
897
898 if (enable) {
899 /* When DSC is enabled on previous boot and reboot with the hub,
900 * there is a chance that Synaptics hub gets stuck during reboot sequence.
901 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
902 */
903 if (!stream->link->link_status.link_active &&
904 memcmp(stream->link->dpcd_caps.branch_dev_name,
905 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
906 apply_synaptics_fifo_reset_wa(aux);
907
908 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
909 DRM_INFO("MST_DSC Send DSC enable to synaptics\n");
910
911 } else {
912 /* Synaptics hub not support virtual dpcd,
913 * external monitor occur garbage while disable DSC,
914 * Disable DSC only when entire link status turn to false,
915 */
916 if (!stream->link->link_status.link_active) {
917 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
918 DRM_INFO("MST_DSC Send DSC disable to synaptics\n");
919 }
920 }
921
922 return ret;
923}
924EXPORT_IF_KUNIT(write_dsc_enable_synaptics_non_virtual_dpcd_mst);
925
926bool dm_helpers_dp_write_dsc_enable(
927 struct dc_context *ctx,
928 const struct dc_stream_state *stream,
929 bool enable)
930{
931 static const uint8_t DSC_DISABLE;
932 static const uint8_t DSC_DECODING = 0x01;
933 static const uint8_t DSC_PASSTHROUGH = 0x02;
934
935 struct amdgpu_dm_connector *aconnector =
936 (struct amdgpu_dm_connector *)stream->dm_stream_context;
937 struct drm_device *dev = aconnector->base.dev;
938 struct drm_dp_mst_port *port;
939 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
940 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
941 uint8_t ret = 0;
942
943 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
944 if (!aconnector->dsc_aux)
945 return false;
946
947 // apply w/a to synaptics
948 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
949 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
950 return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
951 aconnector->dsc_aux, stream, enable_dsc);
952
953 port = aconnector->mst_output_port;
954
955 if (enable) {
956 if (port->passthrough_aux) {
957 ret = drm_dp_dpcd_write(port->passthrough_aux,
958 DP_DSC_ENABLE,
959 &enable_passthrough, 1);
960 drm_dbg_dp(dev,
961 "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
962 ret);
963 }
964
965 ret = drm_dp_dpcd_write(aconnector->dsc_aux,
966 DP_DSC_ENABLE, &enable_dsc, 1);
967 drm_dbg_dp(dev,
968 "MST_DSC Sent DSC decoding enable to %s port, ret = %u\n",
969 (port->passthrough_aux) ? "remote RX" :
970 "virtual dpcd",
971 ret);
972 } else {
973 ret = drm_dp_dpcd_write(aconnector->dsc_aux,
974 DP_DSC_ENABLE, &enable_dsc, 1);
975 drm_dbg_dp(dev,
976 "MST_DSC Sent DSC decoding disable to %s port, ret = %u\n",
977 (port->passthrough_aux) ? "remote RX" :
978 "virtual dpcd",
979 ret);
980
981 if (port->passthrough_aux) {
982 ret = drm_dp_dpcd_write(port->passthrough_aux,
983 DP_DSC_ENABLE,
984 &enable_passthrough, 1);
985 drm_dbg_dp(dev,
986 "MST_DSC Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
987 ret);
988 }
989 }
990 }
991
992 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
993 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
994 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
995 drm_dbg_dp(dev,
996 "SST_DSC Send DSC %s to SST RX\n",
997 enable_dsc ? "enable" : "disable");
998 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
999 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
1000 drm_dbg_dp(dev,
1001 "SST_DSC Send DSC %s to DP-HDMI PCON\n",
1002 enable_dsc ? "enable" : "disable");
1003 }
1004 }
1005
1006 return ret;
1007}
1008EXPORT_IF_KUNIT(dm_helpers_dp_write_dsc_enable);
1009
1010#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
1011uint dm_helpers_get_dc_debug_mask(void)
1012{
1013 return amdgpu_dc_debug_mask;
1014}
1015EXPORT_IF_KUNIT(dm_helpers_get_dc_debug_mask);
1016
1017void dm_helpers_set_dc_debug_mask(uint debug_mask)
1018{
1019 amdgpu_dc_debug_mask = debug_mask;
1020}
1021EXPORT_IF_KUNIT(dm_helpers_set_dc_debug_mask);
1022#endif
1023
1024bool dm_helpers_dp_write_hblank_reduction(struct dc_context *ctx, const struct dc_stream_state *stream)
1025{
1026 // TODO
1027 return false;
1028}
1029EXPORT_IF_KUNIT(dm_helpers_dp_write_hblank_reduction);
1030
1031bool dm_helpers_is_dp_sink_present(struct dc_link *link)
1032{
1033 bool dp_sink_present;
1034 struct amdgpu_dm_connector *aconnector = link->priv;
1035
1036 if (!aconnector) {
1037 DRM_ERROR("Failed to find connector for link!");
1038 return true;
1039 }
1040
1041 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
1042 dp_sink_present = dc_link_is_dp_sink_present(link);
1043 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
1044 return dp_sink_present;
1045}
1046EXPORT_IF_KUNIT(dm_helpers_is_dp_sink_present);
1047
1048STATIC_IFN_KUNIT int
1049dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len)
1050{
1051 struct drm_connector *connector = data;
1052 struct acpi_device *acpidev = ACPI_COMPANION(connector->dev->dev);
1053 unsigned short start = block * EDID_LENGTH;
1054 struct edid *edid;
1055 int r;
1056
1057 if (!acpidev)
1058 return -ENODEV;
1059
1060 /* fetch the entire edid from BIOS */
1061 r = acpi_video_get_edid(acpidev, ACPI_VIDEO_DISPLAY_LCD, -1, (void *)&edid);
1062 if (r < 0) {
1063 drm_dbg(connector->dev, "Failed to get EDID from ACPI: %d\n", r);
1064 return r;
1065 }
1066 if (len > r || start > r || start + len > r) {
1067 r = -EINVAL;
1068 goto cleanup;
1069 }
1070
1071 /* sanity check */
1072 if (edid->revision < 4 || !(edid->input & DRM_EDID_INPUT_DIGITAL) ||
1073 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_UNDEF) {
1074 r = -EINVAL;
1075 goto cleanup;
1076 }
1077
1078 memcpy(buf, (void *)edid + start, len);
1079 r = 0;
1080
1081cleanup:
1082 kfree(edid);
1083
1084 return r;
1085}
1086EXPORT_IF_KUNIT(dm_helpers_probe_acpi_edid);
1087
1088STATIC_IFN_KUNIT const struct drm_edid *
1089dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector)
1090{
1091 struct drm_connector *connector = &aconnector->base;
1092
1093 if (amdgpu_dc_debug_mask & DC_DISABLE_ACPI_EDID)
1094 return NULL;
1095
1096 switch (connector->connector_type) {
1097 case DRM_MODE_CONNECTOR_LVDS:
1098 case DRM_MODE_CONNECTOR_eDP:
1099 break;
1100 default:
1101 return NULL;
1102 }
1103
1104 if (connector->force == DRM_FORCE_OFF)
1105 return NULL;
1106
1107 return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector);
1108}
1109EXPORT_IF_KUNIT(dm_helpers_read_acpi_edid);
1110
1111STATIC_IFN_KUNIT const struct drm_edid *
1112dm_helpers_read_vbios_hardcoded_edid(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
1113{
1114 struct dc_bios *bios = link->ctx->dc_bios;
1115 struct embedded_panel_info info;
1116 const struct drm_edid *edid;
1117 enum bp_result r;
1118
1119 if (!dc_is_embedded_signal(link->connector_signal) ||
1120 !bios->funcs->get_embedded_panel_info)
1121 return NULL;
1122
1123 memset(&info, 0, sizeof(info));
1124 r = bios->funcs->get_embedded_panel_info(bios, &info);
1125
1126 if (r != BP_RESULT_OK) {
1127 dm_error("Error when reading embedded panel info: %u\n", r);
1128 return NULL;
1129 }
1130
1131 if (!info.fake_edid || !info.fake_edid_size) {
1132 dm_error("Embedded panel info doesn't contain an EDID\n");
1133 return NULL;
1134 }
1135
1136 edid = drm_edid_alloc(info.fake_edid, info.fake_edid_size);
1137
1138 if (!drm_edid_valid(edid)) {
1139 dm_error("EDID from embedded panel info is invalid\n");
1140 drm_edid_free(edid);
1141 return NULL;
1142 }
1143
1144 aconnector->base.display_info.width_mm = info.panel_width_mm;
1145 aconnector->base.display_info.height_mm = info.panel_height_mm;
1146
1147 return edid;
1148}
1149EXPORT_IF_KUNIT(dm_helpers_read_vbios_hardcoded_edid);
1150
1151STATIC_IFN_KUNIT uint8_t get_max_frl_rate(uint8_t max_lanes, uint8_t max_rate_per_lane)
1152{
1153 uint8_t max_frl_rate;
1154
1155 if ((max_lanes == 3) && (max_rate_per_lane == 3))
1156 max_frl_rate = 1;
1157 else if ((max_lanes == 3) && (max_rate_per_lane == 6))
1158 max_frl_rate = 2;
1159 else if ((max_lanes == 4) && (max_rate_per_lane == 6))
1160 max_frl_rate = 3;
1161 else if ((max_lanes == 4) && (max_rate_per_lane == 8))
1162 max_frl_rate = 4;
1163 else if ((max_lanes == 4) && (max_rate_per_lane == 10))
1164 max_frl_rate = 5;
1165 else if ((max_lanes == 4) && (max_rate_per_lane == 12))
1166 max_frl_rate = 6;
1167 else
1168 max_frl_rate = 0;
1169
1170 return max_frl_rate;
1171}
1172EXPORT_IF_KUNIT(get_max_frl_rate);
1173
1174STATIC_IFN_KUNIT uint8_t get_dsc_max_slices(uint8_t max_slices, int clk_per_slice)
1175{
1176 uint8_t dsc_max_slices;
1177
1178 if ((max_slices == 1) && (clk_per_slice == 340))
1179 dsc_max_slices = 1;
1180 else if ((max_slices == 2) && (clk_per_slice == 340))
1181 dsc_max_slices = 2;
1182 else if ((max_slices == 4) && (clk_per_slice == 340))
1183 dsc_max_slices = 3;
1184 else if ((max_slices == 8) && (clk_per_slice == 340))
1185 dsc_max_slices = 4;
1186 else if ((max_slices == 8) && (clk_per_slice == 400))
1187 dsc_max_slices = 5;
1188 else if ((max_slices == 12) && (clk_per_slice == 400))
1189 dsc_max_slices = 6;
1190 else if ((max_slices == 16) && (clk_per_slice == 400))
1191 dsc_max_slices = 7;
1192 else
1193 dsc_max_slices = 0;
1194
1195 return dsc_max_slices;
1196}
1197EXPORT_IF_KUNIT(get_dsc_max_slices);
1198
1199void populate_hdmi_info_from_connector(bool enable_frl, struct drm_hdmi_info *hdmi, struct dc_edid_caps *edid_caps)
1200{
1201 edid_caps->scdc_present = hdmi->scdc.supported;
1202 if (enable_frl) {
1203 edid_caps->max_frl_rate = get_max_frl_rate(hdmi->max_lanes, hdmi->max_frl_rate_per_lane);
1204 edid_caps->frl_dsc_support = hdmi->dsc_cap.v_1p2;
1205 if (edid_caps->frl_dsc_support) {
1206 /* HF-VSDB DSC max bpc is cumulative: >=12 implies 10 and 8. */
1207 if (hdmi->dsc_cap.bpc_supported >= 10)
1208 edid_caps->frl_dsc_10bpc = true;
1209 if (hdmi->dsc_cap.bpc_supported >= 12)
1210 edid_caps->frl_dsc_12bpc = true;
1211 edid_caps->frl_dsc_all_bpp = hdmi->dsc_cap.all_bpp;
1212 edid_caps->frl_dsc_native_420 = hdmi->dsc_cap.native_420;
1213 edid_caps->frl_dsc_max_slices = get_dsc_max_slices(hdmi->dsc_cap.max_slices, hdmi->dsc_cap.clk_per_slice);
1214 edid_caps->frl_dsc_max_frl_rate = get_max_frl_rate(hdmi->dsc_cap.max_lanes, hdmi->dsc_cap.max_frl_rate_per_lane);
1215 edid_caps->frl_dsc_total_chunk_kbytes = hdmi->dsc_cap.total_chunk_kbytes;
1216 }
1217 }
1218}
1219EXPORT_IF_KUNIT(populate_hdmi_info_from_connector);
1220
1221enum dc_edid_status dm_helpers_read_local_edid(
1222 struct dc_context *ctx,
1223 struct dc_link *link,
1224 struct dc_sink *sink)
1225{
1226 struct amdgpu_dm_connector *aconnector = link->priv;
1227 struct drm_connector *connector = &aconnector->base;
1228 struct i2c_adapter *ddc;
1229 int retry = 25;
1230 enum dc_edid_status edid_status = EDID_NO_RESPONSE;
1231 const struct drm_edid *drm_edid;
1232 const struct edid *edid;
1233
1234 if (link->aux_mode)
1235 ddc = &aconnector->dm_dp_aux.aux.ddc;
1236 else if (link->ddc_hw_inst == GPIO_DDC_LINE_UNKNOWN &&
1237 dc_is_embedded_signal(link->connector_signal))
1238 ddc = NULL;
1239 else
1240 ddc = &aconnector->i2c->base;
1241
1242 if (link->dc->hwss.prepare_ddc)
1243 link->dc->hwss.prepare_ddc(link);
1244
1245 /* some dongles read edid incorrectly the first time,
1246 * do check sum and retry to make sure read correct edid.
1247 */
1248 do {
1249 drm_edid = dm_helpers_read_acpi_edid(aconnector);
1250 if (drm_edid)
1251 drm_info(connector->dev, "Using ACPI provided EDID for %s\n", connector->name);
1252 else if (!ddc)
1253 drm_edid = dm_helpers_read_vbios_hardcoded_edid(link, aconnector);
1254 else
1255 drm_edid = drm_edid_read_ddc(connector, ddc);
1256 drm_edid_connector_update(connector, drm_edid);
1257
1258 /* DP Compliance Test 4.2.2.6 */
1259 if (link->aux_mode && connector->edid_corrupt)
1260 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
1261
1262 if (!drm_edid && connector->edid_corrupt) {
1263 connector->edid_corrupt = false;
1264 return EDID_BAD_CHECKSUM;
1265 }
1266
1267 if (!drm_edid)
1268 continue;
1269
1270 edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
1271 /*
1272 * Use the length of the EDID property blob populated by
1273 * drm_edid_connector_update() above. It reflects the true number
1274 * of EDID blocks, including any HDMI Forum EDID Extension Override
1275 * Data Block (HF-EEODB) count, which the raw byte 0x7e extension
1276 * count can hide (e.g. HDMI 8K sinks).
1277 */
1278 if (!edid || !connector->edid_blob_ptr ||
1279 connector->edid_blob_ptr->length > sizeof(sink->dc_edid.raw_edid))
1280 return EDID_BAD_INPUT;
1281
1282 /*
1283 * FIXME: amdgpu_dm today does not consider the HF-EEODB, which
1284 * may contain additional mode info for sinks. This is a
1285 * workaround until dc_edid is refactored out from DC into
1286 * amdgpu_dm's ownership, allowing amdgpu_dm to use drm_edid
1287 * directly
1288 */
1289 sink->dc_edid.length = connector->edid_blob_ptr->length;
1290 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
1291
1292 /* We don't need the original edid anymore */
1293 drm_edid_free(drm_edid);
1294
1295 edid_status = dm_helpers_parse_edid_caps(
1296 link,
1297 &sink->dc_edid,
1298 &sink->edid_caps);
1299
1300 } while ((edid_status == EDID_BAD_CHECKSUM || edid_status == EDID_NO_RESPONSE) && --retry > 0);
1301
1302 if (edid_status != EDID_OK)
1303 DRM_ERROR("EDID err: %d, on connector: %s",
1304 edid_status,
1305 aconnector->base.name);
1306 if (link->aux_mode) {
1307 union test_request test_request = {0};
1308 union test_response test_response = {0};
1309
1310 dm_helpers_dp_read_dpcd(ctx,
1311 link,
1312 DP_TEST_REQUEST,
1313 &test_request.raw,
1314 sizeof(union test_request));
1315
1316 if (!test_request.bits.EDID_READ)
1317 return edid_status;
1318
1319 test_response.bits.EDID_CHECKSUM_WRITE = 1;
1320
1321 dm_helpers_dp_write_dpcd(ctx,
1322 link,
1323 DP_TEST_EDID_CHECKSUM,
1324 &sink->dc_edid.raw_edid[sink->dc_edid.length-1],
1325 1);
1326
1327 dm_helpers_dp_write_dpcd(ctx,
1328 link,
1329 DP_TEST_RESPONSE,
1330 &test_response.raw,
1331 sizeof(test_response));
1332
1333 }
1334
1335 return edid_status;
1336}
1337int dm_helper_dmub_aux_transfer_sync(
1338 struct dc_context *ctx,
1339 const struct dc_link *link,
1340 struct aux_payload *payload,
1341 enum aux_return_code_type *operation_result)
1342{
1343 if (!link->hpd_status) {
1344 *operation_result = AUX_RET_ERROR_HPD_DISCON;
1345 return -1;
1346 }
1347
1348 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
1349 operation_result);
1350}
1351EXPORT_IF_KUNIT(dm_helper_dmub_aux_transfer_sync);
1352
1353int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
1354 const struct dc_link *link,
1355 struct set_config_cmd_payload *payload,
1356 enum set_config_status *operation_result)
1357{
1358 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
1359 operation_result);
1360}
1361
1362void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
1363{
1364 /* TODO: something */
1365}
1366EXPORT_IF_KUNIT(dm_set_dcn_clocks);
1367
1368void dm_helpers_dmu_timeout(struct dc_context *ctx)
1369{
1370 // TODO:
1371 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
1372}
1373EXPORT_IF_KUNIT(dm_helpers_dmu_timeout);
1374
1375void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
1376{
1377 // TODO:
1378 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
1379}
1380EXPORT_IF_KUNIT(dm_helpers_smu_timeout);
1381
1382void dm_helpers_init_panel_settings(
1383 struct dc_context *ctx,
1384 struct dc_panel_config *panel_config,
1385 struct dc_sink *sink)
1386{
1387 // Extra Panel Power Sequence
1388 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
1389 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
1390 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
1391 panel_config->pps.extra_post_t7_ms = 0;
1392 panel_config->pps.extra_pre_t11_ms = 0;
1393 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
1394 panel_config->pps.extra_post_OUI_ms = 0;
1395 // Feature DSC
1396 panel_config->dsc.disable_dsc_edp = false;
1397 panel_config->dsc.force_dsc_edp_policy = 0;
1398}
1399EXPORT_IF_KUNIT(dm_helpers_init_panel_settings);
1400
1401void dm_helpers_override_panel_settings(
1402 struct dc_context *ctx,
1403 struct dc_link *link)
1404{
1405 unsigned int panel_inst = 0;
1406
1407 // Feature DSC
1408 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1409 link->panel_config.dsc.disable_dsc_edp = true;
1410
1411 if (dc_get_edp_link_panel_inst(ctx->dc, link, &panel_inst) && panel_inst == 1) {
1412 link->panel_config.psr.disable_psr = true;
1413 link->panel_config.psr.disallow_psrsu = true;
1414 link->panel_config.psr.disallow_replay = true;
1415 }
1416}
1417EXPORT_IF_KUNIT(dm_helpers_override_panel_settings);
1418
1419void *dm_helpers_allocate_gpu_mem(
1420 struct dc_context *ctx,
1421 enum dc_gpu_mem_alloc_type type,
1422 size_t size,
1423 long long *addr)
1424{
1425 struct amdgpu_device *adev = ctx->driver_context;
1426
1427 return dm_allocate_gpu_mem(adev, type, size, addr);
1428}
1429
1430void dm_helpers_free_gpu_mem(
1431 struct dc_context *ctx,
1432 enum dc_gpu_mem_alloc_type type,
1433 void *pvMem)
1434{
1435 struct amdgpu_device *adev = ctx->driver_context;
1436
1437 dm_free_gpu_mem(adev, type, pvMem);
1438}
1439
1440bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
1441{
1442 struct amdgpu_device *adev = ctx->driver_context;
1443 enum dc_irq_source irq_source;
1444 bool ret;
1445
1446 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
1447
1448 ret = amdgpu_dm_irq_set(adev, irq_source, enable);
1449
1450 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
1451 enable ? "en" : "dis", ret);
1452 return ret;
1453}
1454EXPORT_IF_KUNIT(dm_helpers_dmub_outbox_interrupt_control);
1455
1456void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
1457{
1458 /* TODO: virtual DPCD */
1459 struct dc_link *link = stream->link;
1460 union down_spread_ctrl old_downspread;
1461 union down_spread_ctrl new_downspread;
1462
1463 if (link->aux_access_disabled)
1464 return;
1465
1466 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1467 &old_downspread.raw,
1468 sizeof(old_downspread)))
1469 return;
1470
1471 new_downspread.raw = old_downspread.raw;
1472 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1473 (stream->ignore_msa_timing_param) ? 1 : 0;
1474
1475 if (new_downspread.raw != old_downspread.raw)
1476 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1477 &new_downspread.raw,
1478 sizeof(new_downspread));
1479}
1480EXPORT_IF_KUNIT(dm_helpers_mst_enable_stream_features);
1481
1482bool dm_helpers_dp_handle_test_pattern_request(
1483 struct dc_context *ctx,
1484 const struct dc_link *link,
1485 union link_test_pattern dpcd_test_pattern,
1486 union test_misc dpcd_test_params)
1487{
1488 enum dp_test_pattern test_pattern;
1489 enum dp_test_pattern_color_space test_pattern_color_space =
1490 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1491 enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1492 enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1493 struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1494 struct pipe_ctx *pipe_ctx = NULL;
1495 struct amdgpu_dm_connector *aconnector = link->priv;
1496 struct drm_device *dev = aconnector->base.dev;
1497 struct dc_state *dc_state = ctx->dc->current_state;
1498 struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;
1499 int i;
1500
1501 for (i = 0; i < MAX_PIPES; i++) {
1502 if (pipes[i].stream == NULL)
1503 continue;
1504
1505 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1506 !pipes[i].prev_odm_pipe) {
1507 pipe_ctx = &pipes[i];
1508 break;
1509 }
1510 }
1511
1512 if (pipe_ctx == NULL)
1513 return false;
1514
1515 switch (dpcd_test_pattern.bits.PATTERN) {
1516 case LINK_TEST_PATTERN_COLOR_RAMP:
1517 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1518 break;
1519 case LINK_TEST_PATTERN_VERTICAL_BARS:
1520 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1521 break; /* black and white */
1522 case LINK_TEST_PATTERN_COLOR_SQUARES:
1523 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1524 TEST_DYN_RANGE_VESA ?
1525 DP_TEST_PATTERN_COLOR_SQUARES :
1526 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1527 break;
1528 default:
1529 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1530 break;
1531 }
1532
1533 if (dpcd_test_params.bits.CLR_FORMAT == 0)
1534 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1535 else
1536 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1537 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1538 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1539
1540 switch (dpcd_test_params.bits.BPC) {
1541 case 0: // 6 bits
1542 requestColorDepth = COLOR_DEPTH_666;
1543 break;
1544 case 1: // 8 bits
1545 requestColorDepth = COLOR_DEPTH_888;
1546 break;
1547 case 2: // 10 bits
1548 requestColorDepth = COLOR_DEPTH_101010;
1549 break;
1550 case 3: // 12 bits
1551 requestColorDepth = COLOR_DEPTH_121212;
1552 break;
1553 default:
1554 break;
1555 }
1556
1557 switch (dpcd_test_params.bits.CLR_FORMAT) {
1558 case 0:
1559 requestPixelEncoding = PIXEL_ENCODING_RGB;
1560 break;
1561 case 1:
1562 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1563 break;
1564 case 2:
1565 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1566 break;
1567 default:
1568 requestPixelEncoding = PIXEL_ENCODING_RGB;
1569 break;
1570 }
1571
1572 if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1573 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1574 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1575 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
1576 drm_dbg(dev,
1577 "original bpc %d pix encoding %d, changing to %d %d\n",
1578 pipe_ctx->stream->timing.display_color_depth,
1579 pipe_ctx->stream->timing.pixel_encoding,
1580 requestColorDepth,
1581 requestPixelEncoding);
1582 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1583 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1584
1585 dc_link_update_dsc_config(pipe_ctx);
1586
1587 aconnector->timing_changed = true;
1588 /* store current timing */
1589 if (aconnector->timing_requested)
1590 *aconnector->timing_requested = pipe_ctx->stream->timing;
1591 else
1592 drm_err(dev, "timing storage failed\n");
1593
1594 }
1595
1596 pipe_ctx->stream->test_pattern.type = test_pattern;
1597 pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;
1598
1599 /* Temp W/A for compliance test failure */
1600 dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1601 dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?
1602 clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;
1603 dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;
1604 ctx->dc->clk_mgr->funcs->update_clocks(
1605 ctx->dc->clk_mgr,
1606 dc_state,
1607 false);
1608
1609 dc_link_dp_set_test_pattern(
1610 (struct dc_link *) link,
1611 test_pattern,
1612 test_pattern_color_space,
1613 NULL,
1614 NULL,
1615 0);
1616
1617 return false;
1618}
1619EXPORT_IF_KUNIT(dm_helpers_dp_handle_test_pattern_request);
1620
1621void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1622{
1623 // TODO
1624}
1625EXPORT_IF_KUNIT(dm_set_phyd32clk);
1626
1627void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1628{
1629 struct amdgpu_device *adev = ctx->driver_context;
1630
1631 if (adev->dm.idle_workqueue) {
1632 adev->dm.idle_workqueue->enable = enable;
1633 if (enable && !adev->dm.idle_workqueue->running && amdgpu_dm_is_headless(adev))
1634 schedule_work(&adev->dm.idle_workqueue->work);
1635 }
1636}
1637EXPORT_IF_KUNIT(dm_helpers_enable_periodic_detection);
1638
1639void dm_helpers_dp_mst_update_branch_bandwidth(
1640 struct dc_context *ctx,
1641 struct dc_link *link)
1642{
1643 // TODO
1644}
1645EXPORT_IF_KUNIT(dm_helpers_dp_mst_update_branch_bandwidth);
1646
1647STATIC_IFN_KUNIT const uint32_t dm_freesync_pcon_whitelist[] = {
1648 DP_BRANCH_DEVICE_ID_0060AD,
1649 DP_BRANCH_DEVICE_ID_00E04C,
1650 DP_BRANCH_DEVICE_ID_90CC24,
1651 DP_BRANCH_DEVICE_ID_001CF8,
1652 DP_BRANCH_DEVICE_ID_001FF2,
1653};
1654EXPORT_IF_KUNIT(dm_freesync_pcon_whitelist);
1655
1656STATIC_IFN_KUNIT uint32_t dm_freesync_pcon_whitelist_count(void)
1657{
1658 return ARRAY_SIZE(dm_freesync_pcon_whitelist);
1659}
1660EXPORT_IF_KUNIT(dm_freesync_pcon_whitelist_count);
1661
1662STATIC_IFN_KUNIT bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1663{
1664 u32 i;
1665
1666 for (i = 0; i < dm_freesync_pcon_whitelist_count(); i++)
1667 if (dm_freesync_pcon_whitelist[i] == branch_dev_id)
1668 return true;
1669
1670 return false;
1671}
1672EXPORT_IF_KUNIT(dm_is_freesync_pcon_whitelist);
1673
1674enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1675{
1676 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1677 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1678
1679 switch (dpcd_caps->dongle_type) {
1680 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1681 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1682 dpcd_caps->allow_invalid_MSA_timing_param == true &&
1683 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1684 as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1685 break;
1686 default:
1687 break;
1688 }
1689
1690 return as_type;
1691}
1692EXPORT_IF_KUNIT(dm_get_adaptive_sync_support_type);
1693
1694bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream)
1695{
1696 // TODO
1697 return false;
1698}
1699EXPORT_IF_KUNIT(dm_helpers_is_fullscreen);
1700
1701bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream)
1702{
1703 // TODO
1704 return false;
1705}
1706EXPORT_IF_KUNIT(dm_helpers_is_hdr_on);
1707
1708static int mccs_operation_vcp_request(unsigned int vcp_code, struct dc_link *link,
1709 union vcp_reply *reply)
1710{
1711 const unsigned char retry_interval_ms = 40;
1712 unsigned char retry = 5;
1713 struct amdgpu_dm_connector *aconnector = link->priv;
1714 struct i2c_adapter *ddc;
1715 struct i2c_msg msg = {0};
1716 int ret = 0;
1717 int idx;
1718
1719 unsigned char wr_data[MCCS_OP_BUFF_SIZE__WR_VCP_REQUEST] = {
1720 MCCS_SRC_ADDR, /* Byte0 - Src Addr */
1721 MCCS_LENGTH_OFFSET + 2, /* Byte1 - Length */
1722 MCCS_OP_CODE_VCP_REQUEST, /* Byte2 - MCCS Command */
1723 (unsigned char) vcp_code, /* Byte3 - VCP Code */
1724 MCCS_DEST_ADDR << 1 /* Byte4 - CheckSum */
1725 };
1726
1727 /* calculate checksum */
1728 for (idx = 0; idx < (MCCS_OP_BUFF_SIZE__WR_VCP_REQUEST - 1); idx++)
1729 wr_data[(MCCS_OP_BUFF_SIZE__WR_VCP_REQUEST-1)] ^= wr_data[idx];
1730
1731 if (link->aux_mode)
1732 ddc = &aconnector->dm_dp_aux.aux.ddc;
1733 else
1734 ddc = &aconnector->i2c->base;
1735
1736 do {
1737 msg.addr = MCCS_DEST_ADDR;
1738 msg.flags = 0;
1739 msg.len = MCCS_OP_BUFF_SIZE__WR_VCP_REQUEST;
1740 msg.buf = wr_data;
1741
1742 ret = i2c_transfer(ddc, &msg, 1);
1743 if (ret != 1)
1744 goto mccs_retry;
1745
1746 msleep(retry_interval_ms);
1747
1748 msg.addr = MCCS_DEST_ADDR;
1749 msg.flags = I2C_M_RD;
1750 msg.len = MCCS_OP_BUFF_SIZE_RD_VCP_REQUEST;
1751 msg.buf = reply->raw;
1752
1753 ret = i2c_transfer(ddc, &msg, 1);
1754
1755 /* sink might reply with null msg if it can't reply in time */
1756 if (ret == 1 && reply->bytes.length > MCCS_LENGTH_OFFSET)
1757 break;
1758mccs_retry:
1759 retry--;
1760 msleep(retry_interval_ms);
1761 } while (retry);
1762
1763 if (!retry) {
1764 drm_dbg_driver(aconnector->base.dev,
1765 "%s: MCCS VCP request failed after retries", __func__);
1766 return -EIO;
1767 }
1768
1769 return 0;
1770}
1771
1772void dm_helpers_read_mccs_caps(struct dc_context *ctx, struct dc_link *link,
1773 struct dc_sink *sink)
1774{
1775 bool mccs_op = false;
1776 struct dpcd_caps *dpcd_caps;
1777 struct drm_device *dev;
1778 uint16_t freesync_vcp_value = 0;
1779 union vcp_reply vcp_reply_value = {0};
1780
1781 if (!ctx)
1782 return;
1783 dev = adev_to_drm(ctx->driver_context);
1784
1785 if (!link || !sink) {
1786 drm_dbg_driver(dev, "%s: link or sink is NULL", __func__);
1787 return;
1788 }
1789
1790 sink->mccs_caps.freesync_supported = false;
1791 dpcd_caps = &link->dpcd_caps;
1792
1793 if (sink->edid_caps.freesync_vcp_code != 0) {
1794 if (dc_is_dp_signal(link->connector_signal)) {
1795 if ((dpcd_caps->dpcd_rev.raw >= DPCD_REV_14) &&
1796 (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) &&
1797 dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id) &&
1798 (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true))
1799 mccs_op = true;
1800
1801 if ((dpcd_caps->dongle_type != DISPLAY_DONGLE_NONE &&
1802 dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)) {
1803 if (mccs_op == false)
1804 drm_dbg_driver(dev, "%s: Legacy Pcon support", __func__);
1805 mccs_op = true;
1806 }
1807
1808 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1809 // Todo: Freesync over MST
1810 mccs_op = false;
1811 }
1812 }
1813
1814 if (dc_is_hdmi_signal(link->connector_signal)) {
1815 drm_dbg_driver(dev, "%s: Local HDMI sink", __func__);
1816 mccs_op = true;
1817 }
1818
1819 if (mccs_op == true) {
1820 // MCCS VCP request to get VCP value
1821 if (!mccs_operation_vcp_request(sink->edid_caps.freesync_vcp_code, link,
1822 &vcp_reply_value)) {
1823 freesync_vcp_value = vcp_reply_value.bytes.present_value[1];
1824 freesync_vcp_value |= (uint16_t) vcp_reply_value.bytes.present_value[0] << 8;
1825 }
1826 // If VCP Value bit 0 is 1, freesyncSupport = true
1827 sink->mccs_caps.freesync_supported =
1828 (freesync_vcp_value & FREESYNC_SUPPORTED) ? true : false;
1829 }
1830 }
1831}
1832EXPORT_IF_KUNIT(dm_helpers_read_mccs_caps);
1833
1834static int mccs_operation_vcp_set(unsigned int vcp_code, struct dc_link *link, uint16_t value)
1835{
1836 const unsigned char retry_interval_ms = 40;
1837 unsigned char retry = 5;
1838 struct amdgpu_dm_connector *aconnector = link->priv;
1839 struct i2c_adapter *ddc;
1840 struct i2c_msg msg = {0};
1841 int ret = 0;
1842 int idx;
1843
1844 unsigned char wr_data[MCCS_OP_BUFF_SIZE_WR_VCP_SET] = {
1845 MCCS_SRC_ADDR, /* Byte0 - Src Addr */
1846 MCCS_LENGTH_OFFSET + 4, /* Byte1 - Length */
1847 MCCS_OP_CODE_VCP_SET, /* Byte2 - MCCS Command */
1848 (unsigned char)vcp_code, /* Byte3 - VCP Code */
1849 (unsigned char)(value >> 8), /* Byte4 - Value High Byte */
1850 (unsigned char)(value & 0xFF), /* Byte5 - Value Low Byte */
1851 MCCS_DEST_ADDR << 1 /* Byte6 - CheckSum */
1852 };
1853
1854 /* calculate checksum */
1855 for (idx = 0; idx < (MCCS_OP_BUFF_SIZE_WR_VCP_SET - 1); idx++)
1856 wr_data[MCCS_OP_BUFF_SIZE_WR_VCP_SET - 1] ^= wr_data[idx];
1857
1858 if (link->aux_mode)
1859 ddc = &aconnector->dm_dp_aux.aux.ddc;
1860 else
1861 ddc = &aconnector->i2c->base;
1862
1863 do {
1864 msg.addr = MCCS_DEST_ADDR;
1865 msg.flags = 0;
1866 msg.len = MCCS_OP_BUFF_SIZE_WR_VCP_SET;
1867 msg.buf = wr_data;
1868
1869 ret = i2c_transfer(ddc, &msg, 1);
1870 if (ret == 1)
1871 break;
1872
1873 retry--;
1874 msleep(retry_interval_ms);
1875 } while (retry);
1876
1877 if (!retry)
1878 return -EIO;
1879
1880 return 0;
1881}
1882
1883void dm_helpers_mccs_vcp_set(struct dc_context *ctx, struct dc_link *link,
1884 struct dc_sink *sink)
1885{
1886 struct drm_device *dev;
1887 const uint16_t enable = 0x0101;
1888
1889 if (!ctx)
1890 return;
1891 dev = adev_to_drm(ctx->driver_context);
1892
1893 if (!link || !sink) {
1894 drm_dbg_driver(dev, "%s: link or sink is NULL", __func__);
1895 return;
1896 }
1897
1898 if (!sink->mccs_caps.freesync_supported) {
1899 drm_dbg_driver(dev, "%s: MCCS freesync not supported on this sink", __func__);
1900 return;
1901 }
1902
1903 if (mccs_operation_vcp_set(sink->edid_caps.freesync_vcp_code, link, enable))
1904 drm_dbg_driver(dev, "%s: Failed to set VCP code %d", __func__,
1905 sink->edid_caps.freesync_vcp_code);
1906}
1907EXPORT_IF_KUNIT(dm_helpers_mccs_vcp_set);
1908
1909bool dm_helpers_submit_i2c_over_aux(struct ddc_service *ddc, uint32_t address, uint8_t offset,
1910 uint8_t *cmdBuffer, uint32_t len, bool read)
1911{
1912 //TODO: Implement this
1913 return false;
1914}