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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#ifndef __AMDGPU_DM_PLANE_H__
28#define __AMDGPU_DM_PLANE_H__
29
30#include "dc.h"
31#include <drm/drm_plane.h>
32#include "amdgpu.h"
33
34int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
35 struct dc_cursor_position *position);
36
37void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane,
38 struct drm_plane_state *old_plane_state);
39
40int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev,
41 const struct drm_plane_state *state,
42 struct dc_scaling_info *scaling_info);
43
44int amdgpu_dm_plane_helper_check_state(struct drm_plane_state *state,
45 struct drm_crtc_state *new_crtc_state);
46
47int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev,
48 const struct amdgpu_framebuffer *afb,
49 const enum surface_pixel_format format,
50 const enum dc_rotation_angle rotation,
51 struct dc_tiling_info *tiling_info,
52 struct plane_size *plane_size,
53 struct dc_plane_dcc_param *dcc,
54 struct dc_plane_address *address,
55 bool tmz_surface);
56
57int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
58 struct drm_plane *plane,
59 unsigned long possible_crtcs,
60 const struct dc_plane_cap *plane_cap);
61
62const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier);
63
64void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
65 bool *per_pixel_alpha, bool *pre_multiplied_alpha,
66 bool *global_alpha, int *global_alpha_value);
67
68bool amdgpu_dm_plane_is_video_format(uint32_t format);
69
70#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
71void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size,
72 uint64_t *cap, uint64_t mod);
73void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
74 struct dc_tiling_info *tiling_info);
75void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
76 struct dc_tiling_info *tiling_info,
77 uint64_t modifier);
78int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,
79 const enum surface_pixel_format format,
80 const enum dc_rotation_angle rotation,
81 const struct dc_tiling_info *tiling_info,
82 const struct dc_plane_dcc_param *dcc,
83 const struct dc_plane_address *address,
84 const struct plane_size *plane_size);
85bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier);
86unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier);
87int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev,
88 unsigned int plane_type, uint64_t **mods);
89int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane,
90 const struct dc_plane_cap *plane_cap,
91 uint32_t *formats, int max_formats);
92int amdgpu_dm_plane_fill_gfx9_attrs_from_modifiers(struct amdgpu_device *adev,
93 const struct amdgpu_framebuffer *afb,
94 const enum surface_pixel_format format,
95 const enum dc_rotation_angle rotation,
96 const struct plane_size *plane_size,
97 struct dc_tiling_info *tiling_info,
98 struct dc_plane_dcc_param *dcc,
99 struct dc_plane_address *address);
100int amdgpu_dm_plane_fill_gfx12_attrs_from_modifiers(struct amdgpu_device *adev,
101 const struct amdgpu_framebuffer *afb,
102 const enum surface_pixel_format format,
103 const enum dc_rotation_angle rotation,
104 const struct plane_size *plane_size,
105 struct dc_tiling_info *tiling_info,
106 struct dc_plane_dcc_param *dcc,
107 struct dc_plane_address *address);
108bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane,
109 uint32_t format,
110 uint64_t modifier);
111void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev,
112 struct drm_framebuffer *fb,
113 int *min_downscale,
114 int *max_upscale);
115int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane,
116 struct drm_atomic_commit *state, bool flip);
117int amdgpu_dm_plane_atomic_check(struct drm_plane *plane,
118 struct drm_atomic_commit *state);
119void amdgpu_dm_plane_panic_flush(struct drm_plane *plane);
120void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane);
121struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane);
122void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane,
123 struct drm_plane_state *state);
124void amdgpu_dm_plane_add_modifier_dedup(uint64_t **mods, uint64_t *size,
125 uint64_t *cap, uint64_t mod);
126int amdgpu_dm_plane_fill_gfx6_tiling_info_from_modifier(struct dc_tiling_info *tiling_info,
127 uint64_t modifier);
128#endif
129#endif