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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#include "amdgpu_dm_replay.h"
28#include "dc_dmub_srv.h"
29#include "dc.h"
30#include "amdgpu_dm.h"
31#include "modules/power/power_helpers.h"
32#include "dmub/inc/dmub_cmd.h"
33#include "dc/inc/link_service.h"
34#include "dm_helpers.h"
35
36
37/*
38 * amdgpu_dm_link_supports_replay() - check if the link supports replay
39 * @link: link
40 * @aconnector: aconnector
41 *
42 */
43bool amdgpu_dm_link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
44{
45 struct dm_connector_state *state = to_dm_connector_state(aconnector->base.state);
46 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
47 struct adaptive_sync_caps *as_caps = &link->dpcd_caps.adaptive_sync_caps;
48
49 if (!state->freesync_capable)
50 return false;
51
52 if (!aconnector->vsdb_info.replay_mode)
53 return false;
54
55 // Check the eDP version
56 if (dpcd_caps->edp_rev < EDP_REVISION_13)
57 return false;
58
59 if (!dpcd_caps->alpm_caps.bits.AUX_WAKE_ALPM_CAP)
60 return false;
61
62 // Check adaptive sync support cap
63 if (!as_caps->dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT)
64 return false;
65
66 // Sink shall populate line deviation information
67 if (dpcd_caps->pr_info.pixel_deviation_per_line == 0 ||
68 dpcd_caps->pr_info.max_deviation_line == 0)
69 return false;
70
71 return true;
72}
73EXPORT_IF_KUNIT(amdgpu_dm_link_supports_replay);
74
75/*
76 * amdgpu_dm_set_replay_caps() - setup Replay capabilities
77 * @link: link
78 * @aconnector: aconnector
79 *
80 */
81bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
82{
83 struct replay_config pr_config = { 0 };
84 union replay_debug_flags *debug_flags = NULL;
85 struct dc *dc = link->ctx->dc;
86
87 // If Replay is already set to support, return true to skip checks
88 if (link->replay_settings.config.replay_supported)
89 return true;
90
91 if (!dc_is_embedded_signal(link->connector_signal))
92 return false;
93
94 if (link->panel_config.psr.disallow_replay)
95 return false;
96
97 if (!amdgpu_dm_link_supports_replay(link, aconnector))
98 return false;
99
100 if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub ||
101 !dc->ctx->dmub_srv->dmub->feature_caps.replay_supported)
102 return false;
103
104 /* Mark Replay is supported in link and update related attributes
105 * This flag presents DPCD caps & amd_vsdb caps satisfy replay requirement.
106 */
107 pr_config.replay_cap_support = true;
108
109 // Mark Replay is supported in pr_config
110 pr_config.replay_supported = true;
111
112 pr_config.replay_enable_option = pr_enable_option_general_ui |
113 pr_enable_option_static_screen |
114 pr_enable_option_static_screen_coasting;
115 pr_config.replay_power_opt_supported = replay_power_opt_smu_opt_static_screen |
116 replay_power_opt_z10_static_screen;
117 pr_config.replay_smu_opt_supported = false;
118 pr_config.replay_support_fast_resync_in_ultra_sleep_mode =
119 aconnector->max_vfreq >= 2 * aconnector->min_vfreq;
120 pr_config.force_disable_desync_error_check = false;
121
122 debug_flags = (union replay_debug_flags *)&pr_config.debug_flags;
123 debug_flags->u32All = 0;
124 debug_flags->bitfields.visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY;
125 debug_flags->bitfields.skip_crtc_disabled = dc->debug.replay_skip_crtc_disabled;
126
127 init_replay_config(link, &pr_config);
128
129 return true;
130}
131EXPORT_IF_KUNIT(amdgpu_dm_set_replay_caps);
132
133/*
134 * amdgpu_dm_link_setup_replay() - config replay settings
135 * @stream: pointer to dc_stream_state structure
136 * @vrr_params: pointer to mod_vrr_params structure containing VRR parameters
137 *
138 * config replay link settings including coasting vtotal calculations.
139 *
140 * Return: true if successful, false if any parameter is invalid or replay not supported
141 */
142bool amdgpu_dm_link_setup_replay(struct dc_stream_state *stream,
143 struct mod_vrr_params *vrr_params)
144{
145 struct dc_link *link;
146 unsigned int static_coasting_vtotal;
147
148 if (!stream || !stream->link || !vrr_params)
149 return false;
150
151 link = stream->link;
152 if (!link->replay_settings.config.replay_supported)
153 return false;
154
155 if (link->replay_settings.replay_feature_enabled)
156 return true;
157
158 calculate_replay_link_off_frame_count(link, stream->timing.v_total,
159 stream->timing.h_total);
160
161 static_coasting_vtotal = mod_freesync_calc_v_total_from_refresh(stream,
162 vrr_params->min_refresh_in_uhz);
163
164 set_replay_coasting_vtotal(link, PR_COASTING_TYPE_NOM,
165 stream->timing.v_total);
166 set_replay_coasting_vtotal(link, PR_COASTING_TYPE_STATIC,
167 static_coasting_vtotal);
168 return true;
169}
170EXPORT_IF_KUNIT(amdgpu_dm_link_setup_replay);
171
172/*
173 * amdgpu_dm_replay_set_event() - set or clear replay event for a stream
174 * @dm: pointer to amdgpu_display_manager
175 * @stream: pointer to dc_stream_state
176 * @set_event: true to set event, false to clear event
177 * @event: replay event type to set or clear
178 * @wait_for_disable: whether to wait for replay to be disabled before returning
179 *
180 * This function sets or clears a specific replay event for the given stream.
181 * It temporarily disables idle optimizations during the operation to ensure
182 * hardware access is available.
183 *
184 * Return: true if successful, false if any parameter is invalid or operation fails
185 */
186bool amdgpu_dm_replay_set_event(struct amdgpu_display_manager *dm,
187 struct dc_stream_state *stream,
188 bool set_event,
189 enum replay_event event,
190 bool wait_for_disable)
191{
192 unsigned int replay_events;
193
194 /* Validate all required parameters */
195 if (!stream || !stream->link ||
196 !stream->link->replay_settings.replay_feature_enabled)
197 return false;
198
199 /* Get current replay events */
200 if (!mod_power_get_replay_event(dm->power_module, stream, &replay_events))
201 return false;
202
203 /* If all events already in desired state, return true. */
204 if ((replay_events & event) == (set_event ? event : 0))
205 return true;
206
207 return mod_power_set_replay_event(dm->power_module, stream,
208 set_event, event, wait_for_disable);
209}
210EXPORT_IF_KUNIT(amdgpu_dm_replay_set_event);