| 1 | |
| 2 | |
| 3 | * Copyright 2018 Advanced Micro Devices, Inc.
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| 4 | *
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 6 | * copy of this software and associated documentation files (the "Software"),
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| 7 | * to deal in the Software without restriction, including without limitation
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the
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| 10 | * Software is furnished to do so, subject to the following conditions:
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| 11 | *
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| 12 | * The above copyright notice and this permission notice shall be included in
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| 13 | * all copies or substantial portions of the Software.
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| 14 | *
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 21 | * OTHER DEALINGS IN THE SOFTWARE.
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| 22 | *
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| 23 | * Authors: AMD
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| 24 | *
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| 25 |
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| 26 |
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| 27 | #undef TRACE_SYSTEM
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| 28 | #define TRACE_SYSTEM amdgpu_dm
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| 29 |
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| 30 | #if !defined(_AMDGPU_DM_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
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| 31 | #define _AMDGPU_DM_TRACE_H_
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| 32 |
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| 33 | #include <linux/tracepoint.h>
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| 34 | #include <drm/drm_connector.h>
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| 35 | #include <drm/drm_crtc.h>
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| 36 | #include <drm/drm_plane.h>
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| 37 | #include <drm/drm_fourcc.h>
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| 38 | #include <drm/drm_framebuffer.h>
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| 39 | #include <drm/drm_encoder.h>
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| 40 | #include <drm/drm_atomic.h>
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| 41 | #include "dc/inc/hw/optc.h"
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| 42 |
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| 43 | #include "dc/inc/core_types.h"
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| 44 |
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| 45 | DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,
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| 46 | TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
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| 47 | TP_ARGS(count, reg, value),
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| 48 |
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| 49 | TP_STRUCT__entry(
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| 50 | __field(uint32_t, reg)
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| 51 | __field(uint32_t, value)
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| 52 | ),
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| 53 |
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| 54 | TP_fast_assign(
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| 55 | __entry->reg = reg;
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| 56 | __entry->value = value;
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| 57 | *count = *count + 1;
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| 58 | ),
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| 59 |
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| 60 | TP_printk("reg=0x%08lx, value=0x%08lx",
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| 61 | (unsigned long)__entry->reg,
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| 62 | (unsigned long)__entry->value)
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| 63 | );
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| 64 |
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| 65 | DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_rreg,
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| 66 | TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
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| 67 | TP_ARGS(count, reg, value));
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| 68 |
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| 69 | DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_wreg,
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| 70 | TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
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| 71 | TP_ARGS(count, reg, value));
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| 72 |
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| 73 | TRACE_EVENT(amdgpu_dc_performance,
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| 74 | TP_PROTO(unsigned long read_count, unsigned long write_count,
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| 75 | unsigned long *last_read, unsigned long *last_write,
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| 76 | const char *func, unsigned int line),
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| 77 | TP_ARGS(read_count, write_count, last_read, last_write, func, line),
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| 78 | TP_STRUCT__entry(
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| 79 | __field(uint32_t, reads)
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| 80 | __field(uint32_t, writes)
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| 81 | __field(uint32_t, read_delta)
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| 82 | __field(uint32_t, write_delta)
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| 83 | __string(func, func)
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| 84 | __field(uint32_t, line)
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| 85 | ),
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| 86 | TP_fast_assign(
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| 87 | __entry->reads = read_count;
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| 88 | __entry->writes = write_count;
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| 89 | __entry->read_delta = read_count - *last_read;
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| 90 | __entry->write_delta = write_count - *last_write;
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| 91 | __assign_str(func);
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| 92 | __entry->line = line;
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| 93 | *last_read = read_count;
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| 94 | *last_write = write_count;
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| 95 | ),
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| 96 | TP_printk("%s:%d reads=%08ld (%08ld total), writes=%08ld (%08ld total)",
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| 97 | __get_str(func), __entry->line,
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| 98 | (unsigned long)__entry->read_delta,
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| 99 | (unsigned long)__entry->reads,
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| 100 | (unsigned long)__entry->write_delta,
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| 101 | (unsigned long)__entry->writes)
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| 102 | );
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| 103 |
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| 104 | TRACE_EVENT(amdgpu_dm_connector_atomic_check,
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| 105 | TP_PROTO(const struct drm_connector_state *state),
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| 106 | TP_ARGS(state),
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| 107 |
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| 108 | TP_STRUCT__entry(
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| 109 | __field(uint32_t, conn_id)
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| 110 | __field(const struct drm_connector_state *, conn_state)
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| 111 | __field(const struct drm_atomic_commit *, state)
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| 112 | __field(const struct drm_crtc_commit *, commit)
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| 113 | __field(uint32_t, crtc_id)
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| 114 | __field(uint32_t, best_encoder_id)
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| 115 | __field(enum drm_link_status, link_status)
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| 116 | __field(bool, self_refresh_aware)
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| 117 | __field(enum hdmi_picture_aspect, picture_aspect_ratio)
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| 118 | __field(unsigned int, content_type)
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| 119 | __field(unsigned int, hdcp_content_type)
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| 120 | __field(unsigned int, content_protection)
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| 121 | __field(unsigned int, scaling_mode)
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| 122 | __field(u32, colorspace)
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| 123 | __field(u8, max_requested_bpc)
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| 124 | __field(u8, max_bpc)
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| 125 | ),
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| 126 |
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| 127 | TP_fast_assign(
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| 128 | __entry->conn_id = state->connector->base.id;
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| 129 | __entry->conn_state = state;
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| 130 | __entry->state = state->state;
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| 131 | __entry->commit = state->commit;
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| 132 | __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
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| 133 | __entry->best_encoder_id = state->best_encoder ?
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| 134 | state->best_encoder->base.id : 0;
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| 135 | __entry->link_status = state->link_status;
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| 136 | __entry->self_refresh_aware = state->self_refresh_aware;
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| 137 | __entry->picture_aspect_ratio = state->picture_aspect_ratio;
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| 138 | __entry->content_type = state->content_type;
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| 139 | __entry->hdcp_content_type = state->hdcp_content_type;
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| 140 | __entry->content_protection = state->content_protection;
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| 141 | __entry->scaling_mode = state->scaling_mode;
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| 142 | __entry->colorspace = state->colorspace;
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| 143 | __entry->max_requested_bpc = state->max_requested_bpc;
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| 144 | __entry->max_bpc = state->max_bpc;
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| 145 | ),
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| 146 |
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| 147 | TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u "
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| 148 | "best_encoder_id=%u link_status=%d self_refresh_aware=%d "
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| 149 | "picture_aspect_ratio=%d content_type=%u "
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| 150 | "hdcp_content_type=%u content_protection=%u scaling_mode=%u "
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| 151 | "colorspace=%u max_requested_bpc=%u max_bpc=%u",
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| 152 | __entry->conn_id, __entry->conn_state, __entry->state,
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| 153 | __entry->commit, __entry->crtc_id, __entry->best_encoder_id,
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| 154 | __entry->link_status, __entry->self_refresh_aware,
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| 155 | __entry->picture_aspect_ratio, __entry->content_type,
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| 156 | __entry->hdcp_content_type, __entry->content_protection,
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| 157 | __entry->scaling_mode, __entry->colorspace,
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| 158 | __entry->max_requested_bpc, __entry->max_bpc)
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| 159 | );
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| 160 |
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| 161 | TRACE_EVENT(amdgpu_dm_crtc_atomic_check,
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| 162 | TP_PROTO(const struct drm_crtc_state *state),
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| 163 | TP_ARGS(state),
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| 164 |
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| 165 | TP_STRUCT__entry(
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| 166 | __field(const struct drm_atomic_commit *, state)
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| 167 | __field(const struct drm_crtc_state *, crtc_state)
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| 168 | __field(const struct drm_crtc_commit *, commit)
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| 169 | __field(uint32_t, crtc_id)
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| 170 | __field(bool, enable)
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| 171 | __field(bool, active)
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| 172 | __field(bool, planes_changed)
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| 173 | __field(bool, mode_changed)
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| 174 | __field(bool, active_changed)
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| 175 | __field(bool, connectors_changed)
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| 176 | __field(bool, zpos_changed)
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| 177 | __field(bool, color_mgmt_changed)
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| 178 | __field(bool, no_vblank)
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| 179 | __field(bool, async_flip)
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| 180 | __field(bool, vrr_enabled)
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| 181 | __field(bool, self_refresh_active)
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| 182 | __field(u32, plane_mask)
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| 183 | __field(u32, connector_mask)
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| 184 | __field(u32, encoder_mask)
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| 185 | ),
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| 186 |
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| 187 | TP_fast_assign(
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| 188 | __entry->state = state->state;
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| 189 | __entry->crtc_state = state;
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| 190 | __entry->crtc_id = state->crtc->base.id;
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| 191 | __entry->commit = state->commit;
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| 192 | __entry->enable = state->enable;
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| 193 | __entry->active = state->active;
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| 194 | __entry->planes_changed = state->planes_changed;
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| 195 | __entry->mode_changed = state->mode_changed;
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| 196 | __entry->active_changed = state->active_changed;
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| 197 | __entry->connectors_changed = state->connectors_changed;
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| 198 | __entry->zpos_changed = state->zpos_changed;
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| 199 | __entry->color_mgmt_changed = state->color_mgmt_changed;
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| 200 | __entry->no_vblank = state->no_vblank;
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| 201 | __entry->async_flip = state->async_flip;
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| 202 | __entry->vrr_enabled = state->vrr_enabled;
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| 203 | __entry->self_refresh_active = state->self_refresh_active;
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| 204 | __entry->plane_mask = state->plane_mask;
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| 205 | __entry->connector_mask = state->connector_mask;
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| 206 | __entry->encoder_mask = state->encoder_mask;
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| 207 | ),
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| 208 |
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| 209 | TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed("
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| 210 | "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) "
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| 211 | "state(enable=%d active=%d async_flip=%d vrr_enabled=%d "
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| 212 | "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x "
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| 213 | "enc=%x)",
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| 214 | __entry->crtc_id, __entry->crtc_state, __entry->state,
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| 215 | __entry->commit, __entry->planes_changed,
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| 216 | __entry->mode_changed, __entry->active_changed,
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| 217 | __entry->connectors_changed, __entry->zpos_changed,
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| 218 | __entry->color_mgmt_changed, __entry->enable, __entry->active,
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| 219 | __entry->async_flip, __entry->vrr_enabled,
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| 220 | __entry->self_refresh_active, __entry->no_vblank,
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| 221 | __entry->plane_mask, __entry->connector_mask,
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| 222 | __entry->encoder_mask)
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| 223 | );
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| 224 |
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| 225 | DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template,
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| 226 | TP_PROTO(const struct drm_plane_state *state),
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| 227 | TP_ARGS(state),
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| 228 | TP_STRUCT__entry(
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| 229 | __field(uint32_t, plane_id)
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| 230 | __field(enum drm_plane_type, plane_type)
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| 231 | __field(const struct drm_plane_state *, plane_state)
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| 232 | __field(const struct drm_atomic_commit *, state)
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| 233 | __field(uint32_t, crtc_id)
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| 234 | __field(uint32_t, fb_id)
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| 235 | __field(uint32_t, fb_format)
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| 236 | __field(uint8_t, fb_planes)
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| 237 | __field(uint64_t, fb_modifier)
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| 238 | __field(const struct dma_fence *, fence)
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| 239 | __field(int32_t, crtc_x)
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| 240 | __field(int32_t, crtc_y)
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| 241 | __field(uint32_t, crtc_w)
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| 242 | __field(uint32_t, crtc_h)
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| 243 | __field(uint32_t, src_x)
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| 244 | __field(uint32_t, src_y)
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| 245 | __field(uint32_t, src_w)
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| 246 | __field(uint32_t, src_h)
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| 247 | __field(u32, alpha)
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| 248 | __field(uint32_t, pixel_blend_mode)
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| 249 | __field(unsigned int, rotation)
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| 250 | __field(unsigned int, zpos)
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| 251 | __field(unsigned int, normalized_zpos)
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| 252 | __field(enum drm_color_encoding, color_encoding)
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| 253 | __field(enum drm_color_range, color_range)
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| 254 | __field(bool, visible)
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| 255 | ),
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| 256 |
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| 257 | TP_fast_assign(
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| 258 | __entry->plane_id = state->plane->base.id;
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| 259 | __entry->plane_type = state->plane->type;
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| 260 | __entry->plane_state = state;
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| 261 | __entry->state = state->state;
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| 262 | __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
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| 263 | __entry->fb_id = state->fb ? state->fb->base.id : 0;
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| 264 | __entry->fb_format = state->fb ? state->fb->format->format : 0;
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| 265 | __entry->fb_planes = state->fb ? state->fb->format->num_planes : 0;
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| 266 | __entry->fb_modifier = state->fb ? state->fb->modifier : 0;
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| 267 | __entry->fence = state->fence;
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| 268 | __entry->crtc_x = state->crtc_x;
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| 269 | __entry->crtc_y = state->crtc_y;
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| 270 | __entry->crtc_w = state->crtc_w;
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| 271 | __entry->crtc_h = state->crtc_h;
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| 272 | __entry->src_x = state->src_x >> 16;
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| 273 | __entry->src_y = state->src_y >> 16;
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| 274 | __entry->src_w = state->src_w >> 16;
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| 275 | __entry->src_h = state->src_h >> 16;
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| 276 | __entry->alpha = state->alpha;
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| 277 | __entry->pixel_blend_mode = state->pixel_blend_mode;
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| 278 | __entry->rotation = state->rotation;
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| 279 | __entry->zpos = state->zpos;
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| 280 | __entry->normalized_zpos = state->normalized_zpos;
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| 281 | __entry->color_encoding = state->color_encoding;
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| 282 | __entry->color_range = state->color_range;
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| 283 | __entry->visible = state->visible;
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| 284 | ),
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| 285 |
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| 286 | TP_printk("plane_id=%u plane_type=%d plane_state=%p state=%p "
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| 287 | "crtc_id=%u fb(id=%u fmt=%c%c%c%c planes=%u mod=%llu) "
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| 288 | "fence=%p crtc_x=%d crtc_y=%d crtc_w=%u crtc_h=%u "
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| 289 | "src_x=%u src_y=%u src_w=%u src_h=%u alpha=%u "
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| 290 | "pixel_blend_mode=%u rotation=%u zpos=%u "
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| 291 | "normalized_zpos=%u color_encoding=%d color_range=%d "
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| 292 | "visible=%d",
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| 293 | __entry->plane_id, __entry->plane_type, __entry->plane_state,
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| 294 | __entry->state, __entry->crtc_id, __entry->fb_id,
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| 295 | (__entry->fb_format & 0xff) ? (__entry->fb_format & 0xff) : 'N',
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| 296 | ((__entry->fb_format >> 8) & 0xff) ? ((__entry->fb_format >> 8) & 0xff) : 'O',
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| 297 | ((__entry->fb_format >> 16) & 0xff) ? ((__entry->fb_format >> 16) & 0xff) : 'N',
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| 298 | ((__entry->fb_format >> 24) & 0x7f) ? ((__entry->fb_format >> 24) & 0x7f) : 'E',
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| 299 | __entry->fb_planes,
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| 300 | __entry->fb_modifier, __entry->fence, __entry->crtc_x,
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| 301 | __entry->crtc_y, __entry->crtc_w, __entry->crtc_h,
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| 302 | __entry->src_x, __entry->src_y, __entry->src_w, __entry->src_h,
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| 303 | __entry->alpha, __entry->pixel_blend_mode, __entry->rotation,
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| 304 | __entry->zpos, __entry->normalized_zpos,
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| 305 | __entry->color_encoding, __entry->color_range,
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| 306 | __entry->visible)
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| 307 | );
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| 308 |
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| 309 | DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_plane_atomic_check,
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| 310 | TP_PROTO(const struct drm_plane_state *state),
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| 311 | TP_ARGS(state));
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| 312 |
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| 313 | DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor,
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| 314 | TP_PROTO(const struct drm_plane_state *state),
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| 315 | TP_ARGS(state));
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| 316 |
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| 317 | TRACE_EVENT(amdgpu_dm_atomic_state_template,
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| 318 | TP_PROTO(const struct drm_atomic_commit *state),
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| 319 | TP_ARGS(state),
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| 320 |
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| 321 | TP_STRUCT__entry(
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| 322 | __field(const struct drm_atomic_commit *, state)
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| 323 | __field(bool, allow_modeset)
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| 324 | __field(bool, legacy_cursor_update)
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| 325 | __field(bool, async_update)
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| 326 | __field(bool, duplicated)
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| 327 | __field(int, num_connector)
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| 328 | __field(int, num_private_objs)
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| 329 | ),
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| 330 |
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| 331 | TP_fast_assign(
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| 332 | __entry->state = state;
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| 333 | __entry->allow_modeset = state->allow_modeset;
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| 334 | __entry->legacy_cursor_update = state->legacy_cursor_update;
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| 335 | __entry->async_update = state->async_update;
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| 336 | __entry->duplicated = state->duplicated;
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| 337 | __entry->num_connector = state->num_connector;
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| 338 | __entry->num_private_objs = state->num_private_objs;
|
| 339 | ),
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| 340 |
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| 341 | TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d "
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| 342 | "async_update=%d duplicated=%d num_connector=%d "
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| 343 | "num_private_objs=%d",
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| 344 | __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update,
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| 345 | __entry->async_update, __entry->duplicated, __entry->num_connector,
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| 346 | __entry->num_private_objs)
|
| 347 | );
|
| 348 |
|
| 349 | DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin,
|
| 350 | TP_PROTO(const struct drm_atomic_commit *state),
|
| 351 | TP_ARGS(state));
|
| 352 |
|
| 353 | DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish,
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| 354 | TP_PROTO(const struct drm_atomic_commit *state),
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| 355 | TP_ARGS(state));
|
| 356 |
|
| 357 | DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin,
|
| 358 | TP_PROTO(const struct drm_atomic_commit *state),
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| 359 | TP_ARGS(state));
|
| 360 |
|
| 361 | TRACE_EVENT(amdgpu_dm_atomic_check_finish,
|
| 362 | TP_PROTO(const struct drm_atomic_commit *state, int res),
|
| 363 | TP_ARGS(state, res),
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| 364 |
|
| 365 | TP_STRUCT__entry(
|
| 366 | __field(const struct drm_atomic_commit *, state)
|
| 367 | __field(int, res)
|
| 368 | __field(bool, async_update)
|
| 369 | __field(bool, allow_modeset)
|
| 370 | ),
|
| 371 |
|
| 372 | TP_fast_assign(
|
| 373 | __entry->state = state;
|
| 374 | __entry->res = res;
|
| 375 | __entry->async_update = state->async_update;
|
| 376 | __entry->allow_modeset = state->allow_modeset;
|
| 377 | ),
|
| 378 |
|
| 379 | TP_printk("state=%p res=%d async_update=%d allow_modeset=%d",
|
| 380 | __entry->state, __entry->res,
|
| 381 | __entry->async_update, __entry->allow_modeset)
|
| 382 | );
|
| 383 |
|
| 384 | TRACE_EVENT(amdgpu_dm_dc_pipe_state,
|
| 385 | TP_PROTO(int pipe_idx, const struct dc_plane_state *plane_state,
|
| 386 | const struct dc_stream_state *stream,
|
| 387 | const struct plane_resource *plane_res,
|
| 388 | int update_flags),
|
| 389 | TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
|
| 390 |
|
| 391 | TP_STRUCT__entry(
|
| 392 | __field(int, pipe_idx)
|
| 393 | __field(const void *, stream)
|
| 394 | __field(int, stream_w)
|
| 395 | __field(int, stream_h)
|
| 396 | __field(int, dst_x)
|
| 397 | __field(int, dst_y)
|
| 398 | __field(int, dst_w)
|
| 399 | __field(int, dst_h)
|
| 400 | __field(int, src_x)
|
| 401 | __field(int, src_y)
|
| 402 | __field(int, src_w)
|
| 403 | __field(int, src_h)
|
| 404 | __field(int, clip_x)
|
| 405 | __field(int, clip_y)
|
| 406 | __field(int, clip_w)
|
| 407 | __field(int, clip_h)
|
| 408 | __field(int, recout_x)
|
| 409 | __field(int, recout_y)
|
| 410 | __field(int, recout_w)
|
| 411 | __field(int, recout_h)
|
| 412 | __field(int, viewport_x)
|
| 413 | __field(int, viewport_y)
|
| 414 | __field(int, viewport_w)
|
| 415 | __field(int, viewport_h)
|
| 416 | __field(int, flip_immediate)
|
| 417 | __field(int, surface_pitch)
|
| 418 | __field(int, format)
|
| 419 | __field(int, swizzle)
|
| 420 | __field(unsigned int, update_flags)
|
| 421 | ),
|
| 422 |
|
| 423 | TP_fast_assign(
|
| 424 | __entry->pipe_idx = pipe_idx;
|
| 425 | __entry->stream = stream;
|
| 426 | __entry->stream_w = stream->timing.h_addressable;
|
| 427 | __entry->stream_h = stream->timing.v_addressable;
|
| 428 | __entry->dst_x = plane_state->dst_rect.x;
|
| 429 | __entry->dst_y = plane_state->dst_rect.y;
|
| 430 | __entry->dst_w = plane_state->dst_rect.width;
|
| 431 | __entry->dst_h = plane_state->dst_rect.height;
|
| 432 | __entry->src_x = plane_state->src_rect.x;
|
| 433 | __entry->src_y = plane_state->src_rect.y;
|
| 434 | __entry->src_w = plane_state->src_rect.width;
|
| 435 | __entry->src_h = plane_state->src_rect.height;
|
| 436 | __entry->clip_x = plane_state->clip_rect.x;
|
| 437 | __entry->clip_y = plane_state->clip_rect.y;
|
| 438 | __entry->clip_w = plane_state->clip_rect.width;
|
| 439 | __entry->clip_h = plane_state->clip_rect.height;
|
| 440 | __entry->recout_x = plane_res->scl_data.recout.x;
|
| 441 | __entry->recout_y = plane_res->scl_data.recout.y;
|
| 442 | __entry->recout_w = plane_res->scl_data.recout.width;
|
| 443 | __entry->recout_h = plane_res->scl_data.recout.height;
|
| 444 | __entry->viewport_x = plane_res->scl_data.viewport.x;
|
| 445 | __entry->viewport_y = plane_res->scl_data.viewport.y;
|
| 446 | __entry->viewport_w = plane_res->scl_data.viewport.width;
|
| 447 | __entry->viewport_h = plane_res->scl_data.viewport.height;
|
| 448 | __entry->flip_immediate = plane_state->flip_immediate;
|
| 449 | __entry->surface_pitch = plane_state->plane_size.surface_pitch;
|
| 450 | __entry->format = plane_state->format;
|
| 451 | __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
|
| 452 | __entry->update_flags = update_flags;
|
| 453 | ),
|
| 454 | TP_printk("pipe_idx=%d stream=%p rct(%d,%d) dst=(%d,%d,%d,%d) "
|
| 455 | "src=(%d,%d,%d,%d) clip=(%d,%d,%d,%d) recout=(%d,%d,%d,%d) "
|
| 456 | "viewport=(%d,%d,%d,%d) flip_immediate=%d pitch=%d "
|
| 457 | "format=%d swizzle=%d update_flags=%x",
|
| 458 | __entry->pipe_idx,
|
| 459 | __entry->stream,
|
| 460 | __entry->stream_w,
|
| 461 | __entry->stream_h,
|
| 462 | __entry->dst_x,
|
| 463 | __entry->dst_y,
|
| 464 | __entry->dst_w,
|
| 465 | __entry->dst_h,
|
| 466 | __entry->src_x,
|
| 467 | __entry->src_y,
|
| 468 | __entry->src_w,
|
| 469 | __entry->src_h,
|
| 470 | __entry->clip_x,
|
| 471 | __entry->clip_y,
|
| 472 | __entry->clip_w,
|
| 473 | __entry->clip_h,
|
| 474 | __entry->recout_x,
|
| 475 | __entry->recout_y,
|
| 476 | __entry->recout_w,
|
| 477 | __entry->recout_h,
|
| 478 | __entry->viewport_x,
|
| 479 | __entry->viewport_y,
|
| 480 | __entry->viewport_w,
|
| 481 | __entry->viewport_h,
|
| 482 | __entry->flip_immediate,
|
| 483 | __entry->surface_pitch,
|
| 484 | __entry->format,
|
| 485 | __entry->swizzle,
|
| 486 | __entry->update_flags
|
| 487 | )
|
| 488 | );
|
| 489 |
|
| 490 | TRACE_EVENT(amdgpu_dm_dc_clocks_state,
|
| 491 | TP_PROTO(const struct dc_clocks *clk),
|
| 492 | TP_ARGS(clk),
|
| 493 |
|
| 494 | TP_STRUCT__entry(
|
| 495 | __field(int, dispclk_khz)
|
| 496 | __field(int, dppclk_khz)
|
| 497 | __field(int, disp_dpp_voltage_level_khz)
|
| 498 | __field(int, dcfclk_khz)
|
| 499 | __field(int, socclk_khz)
|
| 500 | __field(int, dcfclk_deep_sleep_khz)
|
| 501 | __field(int, fclk_khz)
|
| 502 | __field(int, phyclk_khz)
|
| 503 | __field(int, dramclk_khz)
|
| 504 | __field(int, p_state_change_support)
|
| 505 | __field(int, prev_p_state_change_support)
|
| 506 | __field(int, pwr_state)
|
| 507 | __field(int, dtm_level)
|
| 508 | __field(int, max_supported_dppclk_khz)
|
| 509 | __field(int, max_supported_dispclk_khz)
|
| 510 | __field(int, bw_dppclk_khz)
|
| 511 | __field(int, bw_dispclk_khz)
|
| 512 | ),
|
| 513 | TP_fast_assign(
|
| 514 | __entry->dispclk_khz = clk->dispclk_khz;
|
| 515 | __entry->dppclk_khz = clk->dppclk_khz;
|
| 516 | __entry->dcfclk_khz = clk->dcfclk_khz;
|
| 517 | __entry->socclk_khz = clk->socclk_khz;
|
| 518 | __entry->dcfclk_deep_sleep_khz = clk->dcfclk_deep_sleep_khz;
|
| 519 | __entry->fclk_khz = clk->fclk_khz;
|
| 520 | __entry->phyclk_khz = clk->phyclk_khz;
|
| 521 | __entry->dramclk_khz = clk->dramclk_khz;
|
| 522 | __entry->p_state_change_support = clk->p_state_change_support;
|
| 523 | __entry->prev_p_state_change_support = clk->prev_p_state_change_support;
|
| 524 | __entry->pwr_state = clk->pwr_state;
|
| 525 | __entry->prev_p_state_change_support = clk->prev_p_state_change_support;
|
| 526 | __entry->dtm_level = clk->dtm_level;
|
| 527 | __entry->max_supported_dppclk_khz = clk->max_supported_dppclk_khz;
|
| 528 | __entry->max_supported_dispclk_khz = clk->max_supported_dispclk_khz;
|
| 529 | __entry->bw_dppclk_khz = clk->bw_dppclk_khz;
|
| 530 | __entry->bw_dispclk_khz = clk->bw_dispclk_khz;
|
| 531 | ),
|
| 532 | TP_printk("dispclk_khz=%d dppclk_khz=%d disp_dpp_voltage_level_khz=%d dcfclk_khz=%d socclk_khz=%d "
|
| 533 | "dcfclk_deep_sleep_khz=%d fclk_khz=%d phyclk_khz=%d "
|
| 534 | "dramclk_khz=%d p_state_change_support=%d "
|
| 535 | "prev_p_state_change_support=%d pwr_state=%d prev_p_state_change_support=%d "
|
| 536 | "dtm_level=%d max_supported_dppclk_khz=%d max_supported_dispclk_khz=%d "
|
| 537 | "bw_dppclk_khz=%d bw_dispclk_khz=%d ",
|
| 538 | __entry->dispclk_khz,
|
| 539 | __entry->dppclk_khz,
|
| 540 | __entry->disp_dpp_voltage_level_khz,
|
| 541 | __entry->dcfclk_khz,
|
| 542 | __entry->socclk_khz,
|
| 543 | __entry->dcfclk_deep_sleep_khz,
|
| 544 | __entry->fclk_khz,
|
| 545 | __entry->phyclk_khz,
|
| 546 | __entry->dramclk_khz,
|
| 547 | __entry->p_state_change_support,
|
| 548 | __entry->prev_p_state_change_support,
|
| 549 | __entry->pwr_state,
|
| 550 | __entry->prev_p_state_change_support,
|
| 551 | __entry->dtm_level,
|
| 552 | __entry->max_supported_dppclk_khz,
|
| 553 | __entry->max_supported_dispclk_khz,
|
| 554 | __entry->bw_dppclk_khz,
|
| 555 | __entry->bw_dispclk_khz
|
| 556 | )
|
| 557 | );
|
| 558 |
|
| 559 | TRACE_EVENT(amdgpu_dm_dce_clocks_state,
|
| 560 | TP_PROTO(const struct dce_bw_output *clk),
|
| 561 | TP_ARGS(clk),
|
| 562 |
|
| 563 | TP_STRUCT__entry(
|
| 564 | __field(bool, cpuc_state_change_enable)
|
| 565 | __field(bool, cpup_state_change_enable)
|
| 566 | __field(bool, stutter_mode_enable)
|
| 567 | __field(bool, nbp_state_change_enable)
|
| 568 | __field(bool, all_displays_in_sync)
|
| 569 | __field(int, sclk_khz)
|
| 570 | __field(int, sclk_deep_sleep_khz)
|
| 571 | __field(int, yclk_khz)
|
| 572 | __field(int, dispclk_khz)
|
| 573 | __field(int, blackout_recovery_time_us)
|
| 574 | ),
|
| 575 | TP_fast_assign(
|
| 576 | __entry->cpuc_state_change_enable = clk->cpuc_state_change_enable;
|
| 577 | __entry->cpup_state_change_enable = clk->cpup_state_change_enable;
|
| 578 | __entry->stutter_mode_enable = clk->stutter_mode_enable;
|
| 579 | __entry->nbp_state_change_enable = clk->nbp_state_change_enable;
|
| 580 | __entry->all_displays_in_sync = clk->all_displays_in_sync;
|
| 581 | __entry->sclk_khz = clk->sclk_khz;
|
| 582 | __entry->sclk_deep_sleep_khz = clk->sclk_deep_sleep_khz;
|
| 583 | __entry->yclk_khz = clk->yclk_khz;
|
| 584 | __entry->dispclk_khz = clk->dispclk_khz;
|
| 585 | __entry->blackout_recovery_time_us = clk->blackout_recovery_time_us;
|
| 586 | ),
|
| 587 | TP_printk("cpuc_state_change_enable=%d cpup_state_change_enable=%d stutter_mode_enable=%d "
|
| 588 | "nbp_state_change_enable=%d all_displays_in_sync=%d sclk_khz=%d sclk_deep_sleep_khz=%d "
|
| 589 | "yclk_khz=%d dispclk_khz=%d blackout_recovery_time_us=%d",
|
| 590 | __entry->cpuc_state_change_enable,
|
| 591 | __entry->cpup_state_change_enable,
|
| 592 | __entry->stutter_mode_enable,
|
| 593 | __entry->nbp_state_change_enable,
|
| 594 | __entry->all_displays_in_sync,
|
| 595 | __entry->sclk_khz,
|
| 596 | __entry->sclk_deep_sleep_khz,
|
| 597 | __entry->yclk_khz,
|
| 598 | __entry->dispclk_khz,
|
| 599 | __entry->blackout_recovery_time_us
|
| 600 | )
|
| 601 | );
|
| 602 |
|
| 603 | TRACE_EVENT(amdgpu_dmub_trace_high_irq,
|
| 604 | TP_PROTO(uint32_t trace_code, uint32_t tick_count, uint32_t param0,
|
| 605 | uint32_t param1),
|
| 606 | TP_ARGS(trace_code, tick_count, param0, param1),
|
| 607 | TP_STRUCT__entry(
|
| 608 | __field(uint32_t, trace_code)
|
| 609 | __field(uint32_t, tick_count)
|
| 610 | __field(uint32_t, param0)
|
| 611 | __field(uint32_t, param1)
|
| 612 | ),
|
| 613 | TP_fast_assign(
|
| 614 | __entry->trace_code = trace_code;
|
| 615 | __entry->tick_count = tick_count;
|
| 616 | __entry->param0 = param0;
|
| 617 | __entry->param1 = param1;
|
| 618 | ),
|
| 619 | TP_printk("trace_code=%u tick_count=%u param0=%u param1=%u",
|
| 620 | __entry->trace_code, __entry->tick_count,
|
| 621 | __entry->param0, __entry->param1)
|
| 622 | );
|
| 623 |
|
| 624 | TRACE_EVENT(amdgpu_refresh_rate_track,
|
| 625 | TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz),
|
| 626 | TP_ARGS(crtc_index, refresh_rate_ns, refresh_rate_hz),
|
| 627 | TP_STRUCT__entry(
|
| 628 | __field(int, crtc_index)
|
| 629 | __field(ktime_t, refresh_rate_ns)
|
| 630 | __field(uint32_t, refresh_rate_hz)
|
| 631 | ),
|
| 632 | TP_fast_assign(
|
| 633 | __entry->crtc_index = crtc_index;
|
| 634 | __entry->refresh_rate_ns = refresh_rate_ns;
|
| 635 | __entry->refresh_rate_hz = refresh_rate_hz;
|
| 636 | ),
|
| 637 | TP_printk("crtc_index=%d refresh_rate=%dHz (%lld)",
|
| 638 | __entry->crtc_index,
|
| 639 | __entry->refresh_rate_hz,
|
| 640 | __entry->refresh_rate_ns)
|
| 641 | );
|
| 642 |
|
| 643 | TRACE_EVENT(dcn_fpu,
|
| 644 | TP_PROTO(bool begin, const char *function, const int line, const int recursion_depth),
|
| 645 | TP_ARGS(begin, function, line, recursion_depth),
|
| 646 |
|
| 647 | TP_STRUCT__entry(
|
| 648 | __field(bool, begin)
|
| 649 | __field(const char *, function)
|
| 650 | __field(int, line)
|
| 651 | __field(int, recursion_depth)
|
| 652 | ),
|
| 653 | TP_fast_assign(
|
| 654 | __entry->begin = begin;
|
| 655 | __entry->function = function;
|
| 656 | __entry->line = line;
|
| 657 | __entry->recursion_depth = recursion_depth;
|
| 658 | ),
|
| 659 | TP_printk("%s: recursion_depth: %d: %s()+%d:",
|
| 660 | __entry->begin ? "begin" : "end",
|
| 661 | __entry->recursion_depth,
|
| 662 | __entry->function,
|
| 663 | __entry->line
|
| 664 | )
|
| 665 | );
|
| 666 |
|
| 667 | TRACE_EVENT(dcn_optc_lock_unlock_state,
|
| 668 | TP_PROTO(const struct optc *optc_state, int instance, bool lock, const char *function, const int line),
|
| 669 | TP_ARGS(optc_state, instance, lock, function, line),
|
| 670 |
|
| 671 | TP_STRUCT__entry(
|
| 672 | __field(const char *, function)
|
| 673 | __field(int, instance)
|
| 674 | __field(bool, lock)
|
| 675 | __field(int, line)
|
| 676 | __field(int, opp_count)
|
| 677 | __field(int, max_h_total)
|
| 678 | __field(int, max_v_total)
|
| 679 | __field(int, min_h_blank)
|
| 680 | __field(int, min_h_sync_width)
|
| 681 | __field(int, min_v_sync_width)
|
| 682 | __field(int, min_v_blank)
|
| 683 | __field(int, min_v_blank_interlace)
|
| 684 | __field(int, vstartup_start)
|
| 685 | __field(int, vupdate_offset)
|
| 686 | __field(int, vupdate_width)
|
| 687 | __field(int, vready_offset)
|
| 688 | ),
|
| 689 | TP_fast_assign(
|
| 690 | __entry->function = function;
|
| 691 | __entry->instance = instance;
|
| 692 | __entry->lock = lock;
|
| 693 | __entry->line = line;
|
| 694 | __entry->opp_count = optc_state->opp_count;
|
| 695 | __entry->max_h_total = optc_state->max_h_total;
|
| 696 | __entry->max_v_total = optc_state->max_v_total;
|
| 697 | __entry->min_h_blank = optc_state->min_h_blank;
|
| 698 | __entry->min_h_sync_width = optc_state->min_h_sync_width;
|
| 699 | __entry->min_v_sync_width = optc_state->min_v_sync_width;
|
| 700 | __entry->min_v_blank = optc_state->min_v_blank;
|
| 701 | __entry->min_v_blank_interlace = optc_state->min_v_blank_interlace;
|
| 702 | __entry->vstartup_start = optc_state->vstartup_start;
|
| 703 | __entry->vupdate_offset = optc_state->vupdate_offset;
|
| 704 | __entry->vupdate_width = optc_state->vupdate_width;
|
| 705 | __entry->vready_offset = optc_state->vupdate_offset;
|
| 706 | ),
|
| 707 | TP_printk("%s: %s()+%d: optc_instance=%d opp_count=%d max_h_total=%d max_v_total=%d "
|
| 708 | "min_h_blank=%d min_h_sync_width=%d min_v_sync_width=%d min_v_blank=%d "
|
| 709 | "min_v_blank_interlace=%d vstartup_start=%d vupdate_offset=%d vupdate_width=%d "
|
| 710 | "vready_offset=%d",
|
| 711 | __entry->lock ? "Lock" : "Unlock",
|
| 712 | __entry->function,
|
| 713 | __entry->line,
|
| 714 | __entry->instance,
|
| 715 | __entry->opp_count,
|
| 716 | __entry->max_h_total,
|
| 717 | __entry->max_v_total,
|
| 718 | __entry->min_h_blank,
|
| 719 | __entry->min_h_sync_width,
|
| 720 | __entry->min_v_sync_width,
|
| 721 | __entry->min_v_blank,
|
| 722 | __entry->min_v_blank_interlace,
|
| 723 | __entry->vstartup_start,
|
| 724 | __entry->vupdate_offset,
|
| 725 | __entry->vupdate_width,
|
| 726 | __entry->vready_offset
|
| 727 | )
|
| 728 | );
|
| 729 |
|
| 730 | TRACE_EVENT(amdgpu_dm_brightness,
|
| 731 | TP_PROTO(void *function, u32 user_brightness, u32 converted_brightness, bool aux, bool ac),
|
| 732 | TP_ARGS(function, user_brightness, converted_brightness, aux, ac),
|
| 733 | TP_STRUCT__entry(
|
| 734 | __field(void *, function)
|
| 735 | __field(u32, user_brightness)
|
| 736 | __field(u32, converted_brightness)
|
| 737 | __field(bool, aux)
|
| 738 | __field(bool, ac)
|
| 739 | ),
|
| 740 | TP_fast_assign(
|
| 741 | __entry->function = function;
|
| 742 | __entry->user_brightness = user_brightness;
|
| 743 | __entry->converted_brightness = converted_brightness;
|
| 744 | __entry->aux = aux;
|
| 745 | __entry->ac = ac;
|
| 746 | ),
|
| 747 | TP_printk("%ps: brightness requested=%u converted=%u aux=%s power=%s",
|
| 748 | (void *)__entry->function,
|
| 749 | (u32)__entry->user_brightness,
|
| 750 | (u32)__entry->converted_brightness,
|
| 751 | (__entry->aux) ? "true" : "false",
|
| 752 | (__entry->ac) ? "AC" : "DC"
|
| 753 | )
|
| 754 | );
|
| 755 |
|
| 756 | TRACE_EVENT(amdgpu_dm_ism_commit,
|
| 757 | TP_PROTO(
|
| 758 | int active_vblank_irq_count,
|
| 759 | bool vblank_enabled,
|
| 760 | bool allow_panel_sso
|
| 761 | ),
|
| 762 | TP_ARGS(
|
| 763 | active_vblank_irq_count,
|
| 764 | vblank_enabled,
|
| 765 | allow_panel_sso
|
| 766 | ),
|
| 767 | TP_STRUCT__entry(
|
| 768 | __field(int, active_vblank_irq_count)
|
| 769 | __field(bool, vblank_enabled)
|
| 770 | __field(bool, allow_panel_sso)
|
| 771 | ),
|
| 772 | TP_fast_assign(
|
| 773 | __entry->active_vblank_irq_count = active_vblank_irq_count;
|
| 774 | __entry->vblank_enabled = vblank_enabled;
|
| 775 | __entry->allow_panel_sso = allow_panel_sso;
|
| 776 | ),
|
| 777 | TP_printk(
|
| 778 | "active_vblank_irq_count=%d vblank_enabled=%d allow_panel_sso=%d",
|
| 779 | __entry->active_vblank_irq_count,
|
| 780 | __entry->vblank_enabled,
|
| 781 | __entry->allow_panel_sso
|
| 782 | )
|
| 783 | );
|
| 784 |
|
| 785 | TRACE_EVENT(amdgpu_dm_ism_event,
|
| 786 | TP_PROTO(
|
| 787 | int crtc_id,
|
| 788 | const char *prev_state,
|
| 789 | const char *curr_state,
|
| 790 | const char *event
|
| 791 | ),
|
| 792 | TP_ARGS(
|
| 793 | crtc_id,
|
| 794 | prev_state,
|
| 795 | curr_state,
|
| 796 | event
|
| 797 | ),
|
| 798 | TP_STRUCT__entry(
|
| 799 | __field(int, crtc_id)
|
| 800 | __string(prev_state, prev_state)
|
| 801 | __string(curr_state, curr_state)
|
| 802 | __string(event, event)
|
| 803 | ),
|
| 804 | TP_fast_assign(
|
| 805 | __entry->crtc_id = crtc_id;
|
| 806 | __assign_str(prev_state);
|
| 807 | __assign_str(curr_state);
|
| 808 | __assign_str(event);
|
| 809 | ),
|
| 810 | TP_printk(
|
| 811 | "[CRTC %d] %s -> %s on event %s",
|
| 812 | __entry->crtc_id,
|
| 813 | __get_str(prev_state),
|
| 814 | __get_str(curr_state),
|
| 815 | __get_str(event))
|
| 816 | );
|
| 817 |
|
| 818 |
|
| 819 | #endif
|
| 820 |
|
| 821 | #undef TRACE_INCLUDE_PATH
|
| 822 | #define TRACE_INCLUDE_PATH .
|
| 823 | #define TRACE_INCLUDE_FILE amdgpu_dm_trace
|
| 824 | #include <trace/define_trace.h>
|