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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#include "dm_services_types.h"
28
29#include "amdgpu.h"
30#include "amdgpu_dm.h"
31#include "amdgpu_dm_wb.h"
32#include "dm_helpers.h"
33#include "amdgpu_display.h"
34#include "dc.h"
35
36#include <drm/drm_edid.h>
37#include <drm/drm_atomic_state_helper.h>
38#include <drm/drm_modeset_helper_vtables.h>
39
40static const u32 amdgpu_dm_wb_formats[] = {
41 DRM_FORMAT_XRGB2101010,
42};
43
44STATIC_IFN_KUNIT int amdgpu_dm_wb_encoder_atomic_check(struct drm_encoder *encoder,
45 struct drm_crtc_state *crtc_state,
46 struct drm_connector_state *conn_state)
47{
48 struct drm_framebuffer *fb;
49 const struct drm_display_mode *mode = &crtc_state->mode;
50 bool found = false;
51 uint8_t i;
52
53 if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
54 return 0;
55
56 fb = conn_state->writeback_job->fb;
57 if (fb->width != mode->hdisplay || fb->height != mode->vdisplay) {
58 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
59 fb->width, fb->height);
60 return -EINVAL;
61 }
62
63 for (i = 0; i < ARRAY_SIZE(amdgpu_dm_wb_formats); i++) {
64 if (fb->format->format == amdgpu_dm_wb_formats[i]) {
65 found = true;
66 break;
67 }
68 }
69
70 if (!found) {
71 DRM_DEBUG_KMS("Invalid pixel format %p4cc\n",
72 &fb->format->format);
73 return -EINVAL;
74 }
75
76 return 0;
77}
78EXPORT_IF_KUNIT(amdgpu_dm_wb_encoder_atomic_check);
79
80
81STATIC_IFN_KUNIT int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector)
82{
83 /* Maximum resolution supported by DWB */
84 return drm_add_modes_noedid(connector, 3840, 2160);
85}
86EXPORT_IF_KUNIT(amdgpu_dm_wb_connector_get_modes);
87
88STATIC_IFN_KUNIT int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector,
89 struct drm_writeback_job *job)
90{
91 struct amdgpu_framebuffer *afb;
92 struct drm_gem_object *obj;
93 struct amdgpu_device *adev;
94 struct amdgpu_bo *rbo;
95 uint32_t domain;
96 int r;
97
98 if (!job->fb) {
99 DRM_DEBUG_KMS("No FB bound\n");
100 return 0;
101 }
102
103 afb = to_amdgpu_framebuffer(job->fb);
104 obj = job->fb->obj[0];
105 rbo = gem_to_amdgpu_bo(obj);
106 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
107
108 r = amdgpu_bo_reserve(rbo, true);
109 if (r) {
110 drm_err(adev_to_drm(adev), "fail to reserve bo: %pe\n", ERR_PTR(r));
111 return r;
112 }
113
114 r = dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_NUM_MOVE_FENCES);
115 if (r) {
116 drm_err(adev_to_drm(adev), "reserving fence slot failed: %pe\n", ERR_PTR(r));
117 goto error_unlock;
118 }
119
120 domain = amdgpu_display_supported_domains(adev, rbo->flags);
121
122 rbo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
123 r = amdgpu_bo_pin(rbo, domain);
124 if (unlikely(r != 0)) {
125 if (r != -ERESTARTSYS)
126 DRM_ERROR("Failed to pin framebuffer: %pe\n", ERR_PTR(r));
127 goto error_unlock;
128 }
129
130 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
131 if (unlikely(r != 0)) {
132 DRM_ERROR("%p bind failed: %pe\n", rbo, ERR_PTR(r));
133 goto error_unpin;
134 }
135
136 amdgpu_bo_unreserve(rbo);
137
138 afb->address = amdgpu_bo_gpu_offset(rbo);
139
140 amdgpu_bo_ref(rbo);
141
142 return 0;
143
144error_unpin:
145 amdgpu_bo_unpin(rbo);
146
147error_unlock:
148 amdgpu_bo_unreserve(rbo);
149 return r;
150}
151EXPORT_IF_KUNIT(amdgpu_dm_wb_prepare_job);
152
153STATIC_IFN_KUNIT void amdgpu_dm_wb_cleanup_job(struct drm_writeback_connector *connector,
154 struct drm_writeback_job *job)
155{
156 struct amdgpu_bo *rbo;
157 int r;
158
159 if (!job->fb)
160 return;
161
162 rbo = gem_to_amdgpu_bo(job->fb->obj[0]);
163 r = amdgpu_bo_reserve(rbo, false);
164 if (unlikely(r)) {
165 DRM_ERROR("failed to reserve rbo before unpin: %pe\n", ERR_PTR(r));
166 return;
167 }
168
169 amdgpu_bo_unpin(rbo);
170 amdgpu_bo_unreserve(rbo);
171 amdgpu_bo_unref(&rbo);
172}
173EXPORT_IF_KUNIT(amdgpu_dm_wb_cleanup_job);
174
175static const struct drm_encoder_helper_funcs amdgpu_dm_wb_encoder_helper_funcs = {
176 .atomic_check = amdgpu_dm_wb_encoder_atomic_check,
177};
178
179static const struct drm_connector_funcs amdgpu_dm_wb_connector_funcs = {
180 .fill_modes = drm_helper_probe_single_connector_modes,
181 .destroy = drm_connector_cleanup,
182 .reset = amdgpu_dm_connector_funcs_reset,
183 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
184 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
185};
186
187static const struct drm_connector_helper_funcs amdgpu_dm_wb_conn_helper_funcs = {
188 .get_modes = amdgpu_dm_wb_connector_get_modes,
189 .prepare_writeback_job = amdgpu_dm_wb_prepare_job,
190 .cleanup_writeback_job = amdgpu_dm_wb_cleanup_job,
191};
192
193int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm,
194 struct amdgpu_dm_wb_connector *wbcon,
195 uint32_t link_index)
196{
197 struct dc *dc = dm->dc;
198 struct dc_link *link = dc_get_link_at_index(dc, link_index);
199 int res;
200
201 wbcon->link = link;
202
203 drm_connector_helper_add(&wbcon->base.base, &amdgpu_dm_wb_conn_helper_funcs);
204
205 res = drm_writeback_connector_init(&dm->adev->ddev, &wbcon->base,
206 &amdgpu_dm_wb_connector_funcs,
207 &amdgpu_dm_wb_encoder_helper_funcs,
208 amdgpu_dm_wb_formats,
209 ARRAY_SIZE(amdgpu_dm_wb_formats),
210 amdgpu_dm_get_encoder_crtc_mask(dm->adev));
211
212 if (res)
213 return res;
214 /*
215 * Some of the properties below require access to state, like bpc.
216 * Allocate some default initial connector state with our reset helper.
217 */
218 if (wbcon->base.base.funcs->reset)
219 wbcon->base.base.funcs->reset(&wbcon->base.base);
220
221 return 0;
222}
223EXPORT_IF_KUNIT(amdgpu_dm_wb_connector_init);