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1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dc_bios_types.h"
27#include "dce_stream_encoder.h"
28#include "reg_helper.h"
29#include "hw_shared.h"
30
31#define DC_LOGGER \
32 enc110->base.ctx->logger
33
34#define REG(reg)\
35 (enc110->regs->reg)
36
37#undef FN
38#define FN(reg_name, field_name) \
39 enc110->se_shift->field_name, enc110->se_mask->field_name
40
41#define VBI_LINE_0 0
42#define DP_BLANK_MAX_RETRY 20
43#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
44
45#ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
46 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
47 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
48 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
49 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
50#endif
51
52enum {
53 DP_MST_UPDATE_MAX_RETRY = 50
54};
55
56#define DCE110_SE(audio)\
57 container_of(audio, struct dce110_stream_encoder, base)
58
59#define CTX \
60 enc110->base.ctx
61
62static void dce110_update_generic_info_packet(
63 struct dce110_stream_encoder *enc110,
64 uint32_t packet_index,
65 const struct dc_info_packet *info_packet)
66{
67 /* TODOFPGA Figure out a proper number for max_retries polling for lock
68 * use 50 for now.
69 */
70 uint32_t max_retries = 50;
71
72 /*we need turn on clock before programming AFMT block*/
73 if (REG(AFMT_CNTL))
74 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
75
76 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
77 if (packet_index >= 8)
78 ASSERT(0);
79
80 /* poll dig_update_lock is not locked -> asic internal signal
81 * assume otg master lock will unlock it
82 */
83/* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
84 0, 10, max_retries);*/
85
86 /* check if HW reading GSP memory */
87 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
88 0, 10, max_retries);
89
90 /* HW does is not reading GSP memory not reading too long ->
91 * something wrong. clear GPS memory access and notify?
92 * hw SW is writing to GSP memory
93 */
94 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
95 }
96 /* choose which generic packet to use */
97 {
98 REG_READ(AFMT_VBI_PACKET_CONTROL);
99 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
100 AFMT_GENERIC_INDEX, packet_index);
101 }
102
103 /* write generic packet header
104 * (4th byte is for GENERIC0 only) */
105 {
106 REG_SET_4(AFMT_GENERIC_HDR, 0,
107 AFMT_GENERIC_HB0, info_packet->hb0,
108 AFMT_GENERIC_HB1, info_packet->hb1,
109 AFMT_GENERIC_HB2, info_packet->hb2,
110 AFMT_GENERIC_HB3, info_packet->hb3);
111 }
112
113 /* write generic packet contents
114 * (we never use last 4 bytes)
115 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
116 {
117 const uint32_t *content =
118 (const uint32_t *) &info_packet->sb[0];
119
120 REG_WRITE(AFMT_GENERIC_0, *content++);
121 REG_WRITE(AFMT_GENERIC_1, *content++);
122 REG_WRITE(AFMT_GENERIC_2, *content++);
123 REG_WRITE(AFMT_GENERIC_3, *content++);
124 REG_WRITE(AFMT_GENERIC_4, *content++);
125 REG_WRITE(AFMT_GENERIC_5, *content++);
126 REG_WRITE(AFMT_GENERIC_6, *content++);
127 REG_WRITE(AFMT_GENERIC_7, *content);
128 }
129
130 if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
131 /* force double-buffered packet update */
132 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
133 AFMT_GENERIC0_UPDATE, (packet_index == 0),
134 AFMT_GENERIC2_UPDATE, (packet_index == 2));
135 }
136
137 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
138 switch (packet_index) {
139 case 0:
140 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
141 AFMT_GENERIC0_FRAME_UPDATE, 1);
142 break;
143 case 1:
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
145 AFMT_GENERIC1_FRAME_UPDATE, 1);
146 break;
147 case 2:
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
149 AFMT_GENERIC2_FRAME_UPDATE, 1);
150 break;
151 case 3:
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
153 AFMT_GENERIC3_FRAME_UPDATE, 1);
154 break;
155 case 4:
156 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
157 AFMT_GENERIC4_FRAME_UPDATE, 1);
158 break;
159 case 5:
160 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
161 AFMT_GENERIC5_FRAME_UPDATE, 1);
162 break;
163 case 6:
164 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
165 AFMT_GENERIC6_FRAME_UPDATE, 1);
166 break;
167 case 7:
168 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
169 AFMT_GENERIC7_FRAME_UPDATE, 1);
170 break;
171 default:
172 break;
173 }
174 }
175}
176
177static void dce110_update_hdmi_info_packet(
178 struct dce110_stream_encoder *enc110,
179 uint32_t packet_index,
180 const struct dc_info_packet *info_packet)
181{
182 uint32_t cont, send, line;
183
184 if (info_packet->valid) {
185 dce110_update_generic_info_packet(
186 enc110,
187 packet_index,
188 info_packet);
189
190 /* enable transmission of packet(s) -
191 * packet transmission begins on the next frame */
192 cont = 1;
193 /* send packet(s) every frame */
194 send = 1;
195 /* select line number to send packets on */
196 line = 2;
197 } else {
198 cont = 0;
199 send = 0;
200 line = 0;
201 }
202
203 /* choose which generic packet control to use */
204 switch (packet_index) {
205 case 0:
206 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
207 HDMI_GENERIC0_CONT, cont,
208 HDMI_GENERIC0_SEND, send,
209 HDMI_GENERIC0_LINE, line);
210 break;
211 case 1:
212 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
213 HDMI_GENERIC1_CONT, cont,
214 HDMI_GENERIC1_SEND, send,
215 HDMI_GENERIC1_LINE, line);
216 break;
217 case 2:
218 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
219 HDMI_GENERIC0_CONT, cont,
220 HDMI_GENERIC0_SEND, send,
221 HDMI_GENERIC0_LINE, line);
222 break;
223 case 3:
224 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
225 HDMI_GENERIC1_CONT, cont,
226 HDMI_GENERIC1_SEND, send,
227 HDMI_GENERIC1_LINE, line);
228 break;
229 case 4:
230 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
231 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
232 HDMI_GENERIC0_CONT, cont,
233 HDMI_GENERIC0_SEND, send,
234 HDMI_GENERIC0_LINE, line);
235 break;
236 case 5:
237 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
238 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
239 HDMI_GENERIC1_CONT, cont,
240 HDMI_GENERIC1_SEND, send,
241 HDMI_GENERIC1_LINE, line);
242 break;
243 case 6:
244 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
245 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
246 HDMI_GENERIC0_CONT, cont,
247 HDMI_GENERIC0_SEND, send,
248 HDMI_GENERIC0_LINE, line);
249 break;
250 case 7:
251 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
252 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
253 HDMI_GENERIC1_CONT, cont,
254 HDMI_GENERIC1_SEND, send,
255 HDMI_GENERIC1_LINE, line);
256 break;
257 default:
258 /* invalid HW packet index */
259 DC_LOG_WARNING(
260 "Invalid HW packet index: %s()\n",
261 __func__);
262 return;
263 }
264}
265
266/* setup stream encoder in dp mode */
267static void dce110_stream_encoder_dp_set_stream_attribute(
268 struct stream_encoder *enc,
269 struct dc_crtc_timing *crtc_timing,
270 enum dc_color_space output_color_space,
271 bool use_vsc_sdp_for_colorimetry,
272 uint32_t enable_sdp_splitting)
273{
274 (void)enable_sdp_splitting;
275 uint32_t h_active_start;
276 uint32_t v_active_start;
277 uint32_t misc0 = 0;
278 uint32_t misc1 = 0;
279 uint32_t h_blank;
280 uint32_t h_back_porch;
281 uint8_t colorimetry_bpc;
282 uint8_t dynamic_range_rgb = 0; /*full range*/
283 uint8_t dynamic_range_ycbcr = 1; /*bt709*/
284
285 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
286 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
287 if (hw_crtc_timing.flags.INTERLACE) {
288 /*the input timing is in VESA spec format with Interlace flag =1*/
289 hw_crtc_timing.v_total /= 2;
290 hw_crtc_timing.v_border_top /= 2;
291 hw_crtc_timing.v_addressable /= 2;
292 hw_crtc_timing.v_border_bottom /= 2;
293 hw_crtc_timing.v_front_porch /= 2;
294 hw_crtc_timing.v_sync_width /= 2;
295 }
296 /* set pixel encoding */
297 switch (hw_crtc_timing.pixel_encoding) {
298 case PIXEL_ENCODING_YCBCR422:
299 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
300 DP_PIXEL_ENCODING_TYPE_YCBCR422);
301 break;
302 case PIXEL_ENCODING_YCBCR444:
303 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
304 DP_PIXEL_ENCODING_TYPE_YCBCR444);
305
306 if (hw_crtc_timing.flags.Y_ONLY)
307 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
308 /* HW testing only, no use case yet.
309 * Color depth of Y-only could be
310 * 8, 10, 12, 16 bits */
311 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
312 DP_PIXEL_ENCODING_TYPE_Y_ONLY);
313 /* Note: DP_MSA_MISC1 bit 7 is the indicator
314 * of Y-only mode.
315 * This bit is set in HW if register
316 * DP_PIXEL_ENCODING is programmed to 0x4 */
317 break;
318 case PIXEL_ENCODING_YCBCR420:
319 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
320 DP_PIXEL_ENCODING_TYPE_YCBCR420);
321 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
322 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
323
324 if (enc110->se_mask->DP_VID_N_MUL)
325 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
326 break;
327 default:
328 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
329 DP_PIXEL_ENCODING_TYPE_RGB444);
330 break;
331 }
332
333 if (REG(DP_MSA_MISC))
334 misc1 = REG_READ(DP_MSA_MISC);
335
336 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
337 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
338 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
339 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
340 */
341 if (use_vsc_sdp_for_colorimetry)
342 misc1 = misc1 | 0x40;
343 else
344 misc1 = misc1 & ~0x40;
345
346 /* set color depth */
347
348 switch (hw_crtc_timing.display_color_depth) {
349 case COLOR_DEPTH_666:
350 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
351 0);
352 break;
353 case COLOR_DEPTH_888:
354 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
355 DP_COMPONENT_PIXEL_DEPTH_8BPC);
356 break;
357 case COLOR_DEPTH_101010:
358 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
359 DP_COMPONENT_PIXEL_DEPTH_10BPC);
360
361 break;
362 case COLOR_DEPTH_121212:
363 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
364 DP_COMPONENT_PIXEL_DEPTH_12BPC);
365 break;
366 default:
367 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
368 DP_COMPONENT_PIXEL_DEPTH_6BPC);
369 break;
370 }
371
372 /* set dynamic range and YCbCr range */
373
374
375 switch (hw_crtc_timing.display_color_depth) {
376 case COLOR_DEPTH_666:
377 colorimetry_bpc = 0;
378 break;
379 case COLOR_DEPTH_888:
380 colorimetry_bpc = 1;
381 break;
382 case COLOR_DEPTH_101010:
383 colorimetry_bpc = 2;
384 break;
385 case COLOR_DEPTH_121212:
386 colorimetry_bpc = 3;
387 break;
388 default:
389 colorimetry_bpc = 0;
390 break;
391 }
392
393 misc0 = colorimetry_bpc << 5;
394
395 if (REG(DP_MSA_TIMING_PARAM1)) {
396 switch (output_color_space) {
397 case COLOR_SPACE_SRGB:
398 misc0 = misc0 | 0x0;
399 misc1 = misc1 & ~0x80; /* bit7 = 0*/
400 dynamic_range_rgb = 0; /*full range*/
401 break;
402 case COLOR_SPACE_SRGB_LIMITED:
403 misc0 = misc0 | 0x8; /* bit3=1 */
404 misc1 = misc1 & ~0x80; /* bit7 = 0*/
405 dynamic_range_rgb = 1; /*limited range*/
406 break;
407 case COLOR_SPACE_YCBCR601:
408 case COLOR_SPACE_YCBCR601_LIMITED:
409 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
410 misc1 = misc1 & ~0x80; /* bit7 = 0*/
411 dynamic_range_ycbcr = 0; /*bt601*/
412 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
413 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
414 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
415 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
416 break;
417 case COLOR_SPACE_YCBCR709:
418 case COLOR_SPACE_YCBCR709_LIMITED:
419 case COLOR_SPACE_YCBCR709_BLACK:
420 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
421 misc1 = misc1 & ~0x80; /* bit7 = 0*/
422 dynamic_range_ycbcr = 1; /*bt709*/
423 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
424 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
425 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
426 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
427 break;
428 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
429 dynamic_range_rgb = 1; /*limited range*/
430 break;
431 case COLOR_SPACE_2020_RGB_FULLRANGE:
432 case COLOR_SPACE_2020_YCBCR_LIMITED:
433 case COLOR_SPACE_XR_RGB:
434 case COLOR_SPACE_MSREF_SCRGB:
435 case COLOR_SPACE_ADOBERGB:
436 case COLOR_SPACE_DCIP3:
437 case COLOR_SPACE_XV_YCC_709:
438 case COLOR_SPACE_XV_YCC_601:
439 case COLOR_SPACE_DISPLAYNATIVE:
440 case COLOR_SPACE_DOLBYVISION:
441 case COLOR_SPACE_APPCTRL:
442 case COLOR_SPACE_CUSTOMPOINTS:
443 case COLOR_SPACE_UNKNOWN:
444 default:
445 /* do nothing */
446 break;
447 }
448 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
449 REG_UPDATE_2(
450 DP_PIXEL_FORMAT,
451 DP_DYN_RANGE, dynamic_range_rgb,
452 DP_YCBCR_RANGE, dynamic_range_ycbcr);
453
454 if (REG(DP_MSA_COLORIMETRY))
455 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
456
457 if (REG(DP_MSA_MISC))
458 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
459
460 /* dcn new register
461 * dc_crtc_timing is vesa dmt struct. data from edid
462 */
463 if (REG(DP_MSA_TIMING_PARAM1))
464 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
465 DP_MSA_HTOTAL, hw_crtc_timing.h_total,
466 DP_MSA_VTOTAL, hw_crtc_timing.v_total);
467
468 /* calcuate from vesa timing parameters
469 * h_active_start related to leading edge of sync
470 */
471
472 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
473 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
474
475 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
476 hw_crtc_timing.h_sync_width;
477
478 /* start at begining of left border */
479 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
480
481
482 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
483 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
484 hw_crtc_timing.v_front_porch;
485
486
487 /* start at begining of left border */
488 if (REG(DP_MSA_TIMING_PARAM2))
489 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
490 DP_MSA_HSTART, h_active_start,
491 DP_MSA_VSTART, v_active_start);
492
493 if (REG(DP_MSA_TIMING_PARAM3))
494 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
495 DP_MSA_HSYNCWIDTH,
496 hw_crtc_timing.h_sync_width,
497 DP_MSA_HSYNCPOLARITY,
498 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
499 DP_MSA_VSYNCWIDTH,
500 hw_crtc_timing.v_sync_width,
501 DP_MSA_VSYNCPOLARITY,
502 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
503
504 /* HWDITH include border or overscan */
505 if (REG(DP_MSA_TIMING_PARAM4))
506 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
507 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
508 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
509 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
510 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
511 } else {
512 /* DCE-only path */
513 if (REG(DP_MSA_MISC))
514 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
515 }
516}
517
518static void dce110_stream_encoder_set_stream_attribute_helper(
519 struct dce110_stream_encoder *enc110,
520 struct dc_crtc_timing *crtc_timing)
521{
522 if (enc110->regs->TMDS_CNTL) {
523 switch (crtc_timing->pixel_encoding) {
524 case PIXEL_ENCODING_YCBCR422:
525 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
526 break;
527 default:
528 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
529 break;
530 }
531 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
532 } else if (enc110->regs->DIG_FE_CNTL) {
533 switch (crtc_timing->pixel_encoding) {
534 case PIXEL_ENCODING_YCBCR422:
535 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
536 break;
537 default:
538 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
539 break;
540 }
541 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
542 }
543
544}
545
546/* setup stream encoder in hdmi mode */
547static void dce110_stream_encoder_hdmi_set_stream_attribute(
548 struct stream_encoder *enc,
549 struct dc_crtc_timing *crtc_timing,
550 int actual_pix_clk_khz,
551 bool enable_audio)
552{
553 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
554 struct bp_encoder_control cntl = {0};
555
556 cntl.action = ENCODER_CONTROL_SETUP;
557 cntl.engine_id = enc110->base.id;
558 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
559 cntl.enable_dp_audio = enable_audio;
560 cntl.pixel_clock = actual_pix_clk_khz;
561 cntl.lanes_number = LANE_COUNT_FOUR;
562 cntl.color_depth = crtc_timing->display_color_depth;
563
564 if (enc110->base.bp->funcs->encoder_control(
565 enc110->base.bp, &cntl) != BP_RESULT_OK)
566 return;
567
568 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
569
570 /* setup HDMI engine */
571 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
572 REG_UPDATE_3(HDMI_CONTROL,
573 HDMI_PACKET_GEN_VERSION, 1,
574 HDMI_KEEPOUT_MODE, 1,
575 HDMI_DEEP_COLOR_ENABLE, 0);
576 } else if (enc110->regs->DIG_FE_CNTL) {
577 REG_UPDATE_5(HDMI_CONTROL,
578 HDMI_PACKET_GEN_VERSION, 1,
579 HDMI_KEEPOUT_MODE, 1,
580 HDMI_DEEP_COLOR_ENABLE, 0,
581 HDMI_DATA_SCRAMBLE_EN, 0,
582 HDMI_CLOCK_CHANNEL_RATE, 0);
583 }
584
585 switch (crtc_timing->display_color_depth) {
586 case COLOR_DEPTH_888:
587 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
588 break;
589 case COLOR_DEPTH_101010:
590 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
591 REG_UPDATE_2(HDMI_CONTROL,
592 HDMI_DEEP_COLOR_DEPTH, 1,
593 HDMI_DEEP_COLOR_ENABLE, 0);
594 } else {
595 REG_UPDATE_2(HDMI_CONTROL,
596 HDMI_DEEP_COLOR_DEPTH, 1,
597 HDMI_DEEP_COLOR_ENABLE, 1);
598 }
599 break;
600 case COLOR_DEPTH_121212:
601 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
602 REG_UPDATE_2(HDMI_CONTROL,
603 HDMI_DEEP_COLOR_DEPTH, 2,
604 HDMI_DEEP_COLOR_ENABLE, 0);
605 } else {
606 REG_UPDATE_2(HDMI_CONTROL,
607 HDMI_DEEP_COLOR_DEPTH, 2,
608 HDMI_DEEP_COLOR_ENABLE, 1);
609 }
610 break;
611 case COLOR_DEPTH_161616:
612 REG_UPDATE_2(HDMI_CONTROL,
613 HDMI_DEEP_COLOR_DEPTH, 3,
614 HDMI_DEEP_COLOR_ENABLE, 1);
615 break;
616 default:
617 break;
618 }
619
620 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
621 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
622 /* enable HDMI data scrambler
623 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
624 * Clock channel frequency is 1/4 of character rate.
625 */
626 REG_UPDATE_2(HDMI_CONTROL,
627 HDMI_DATA_SCRAMBLE_EN, 1,
628 HDMI_CLOCK_CHANNEL_RATE, 1);
629 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
630
631 /* TODO: New feature for DCE11, still need to implement */
632
633 /* enable HDMI data scrambler
634 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
635 * Clock channel frequency is the same
636 * as character rate
637 */
638 REG_UPDATE_2(HDMI_CONTROL,
639 HDMI_DATA_SCRAMBLE_EN, 1,
640 HDMI_CLOCK_CHANNEL_RATE, 0);
641 }
642 }
643
644 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
645 HDMI_GC_CONT, 1,
646 HDMI_GC_SEND, 1,
647 HDMI_NULL_SEND, 1);
648
649 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
650
651 /* following belongs to audio */
652 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
653
654 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
655
656 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
657 VBI_LINE_0 + 2);
658
659 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
660
661}
662
663/* setup stream encoder in dvi mode */
664static void dce110_stream_encoder_dvi_set_stream_attribute(
665 struct stream_encoder *enc,
666 struct dc_crtc_timing *crtc_timing,
667 bool is_dual_link)
668{
669 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
670 struct bp_encoder_control cntl = {0};
671
672 cntl.action = ENCODER_CONTROL_SETUP;
673 cntl.engine_id = enc110->base.id;
674 cntl.signal = is_dual_link ?
675 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
676 cntl.enable_dp_audio = false;
677 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
678 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
679
680 if (enc110->base.bp->funcs->encoder_control(
681 enc110->base.bp, &cntl) != BP_RESULT_OK)
682 return;
683
684 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
685 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
686 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
687}
688
689/* setup stream encoder in LVDS mode */
690static void dce110_stream_encoder_lvds_set_stream_attribute(
691 struct stream_encoder *enc,
692 struct dc_crtc_timing *crtc_timing)
693{
694 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
695 struct bp_encoder_control cntl = {0};
696
697 cntl.action = ENCODER_CONTROL_SETUP;
698 cntl.engine_id = enc110->base.id;
699 cntl.signal = SIGNAL_TYPE_LVDS;
700 cntl.enable_dp_audio = false;
701 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
702 cntl.lanes_number = LANE_COUNT_FOUR;
703
704 if (enc110->base.bp->funcs->encoder_control(
705 enc110->base.bp, &cntl) != BP_RESULT_OK)
706 return;
707
708 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
709}
710
711static void dce110_stream_encoder_set_throttled_vcp_size(
712 struct stream_encoder *enc,
713 struct fixed31_32 avg_time_slots_per_mtp)
714{
715 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
716 uint32_t x = dc_fixpt_floor(
717 avg_time_slots_per_mtp);
718 uint32_t y = dc_fixpt_ceil(
719 dc_fixpt_shl(
720 dc_fixpt_sub_int(
721 avg_time_slots_per_mtp,
722 x),
723 26));
724
725 {
726 REG_SET_2(DP_MSE_RATE_CNTL, 0,
727 DP_MSE_RATE_X, x,
728 DP_MSE_RATE_Y, y);
729 }
730
731 /* wait for update to be completed on the link */
732 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
733 /* is reset to 0 (not pending) */
734 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
735 0,
736 10, DP_MST_UPDATE_MAX_RETRY);
737}
738
739static void dce110_stream_encoder_update_hdmi_info_packets(
740 struct stream_encoder *enc,
741 const struct encoder_info_frame *info_frame)
742{
743 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
744
745 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
746 enc110->se_mask->HDMI_AVI_INFO_SEND) {
747
748 if (info_frame->avi.valid) {
749 const uint32_t *content =
750 (const uint32_t *) &info_frame->avi.sb[0];
751 /*we need turn on clock before programming AFMT block*/
752 if (REG(AFMT_CNTL))
753 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
754
755 REG_WRITE(AFMT_AVI_INFO0, content[0]);
756
757 REG_WRITE(AFMT_AVI_INFO1, content[1]);
758
759 REG_WRITE(AFMT_AVI_INFO2, content[2]);
760
761 REG_WRITE(AFMT_AVI_INFO3, content[3]);
762
763 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
764 info_frame->avi.hb1);
765
766 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
767 HDMI_AVI_INFO_SEND, 1,
768 HDMI_AVI_INFO_CONT, 1);
769
770 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
771 VBI_LINE_0 + 2);
772
773 } else {
774 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
775 HDMI_AVI_INFO_SEND, 0,
776 HDMI_AVI_INFO_CONT, 0);
777 }
778 }
779
780 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
781 enc110->se_mask->HDMI_AVI_INFO_SEND) {
782 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
783 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
784 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
785 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
786 }
787
788 if (enc110->se_mask->HDMI_DB_DISABLE) {
789 /* for bring up, disable dp double TODO */
790 if (REG(HDMI_DB_CONTROL))
791 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
792
793 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
794 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
795 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
796 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
797 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
798 }
799}
800
801static void dce110_stream_encoder_stop_hdmi_info_packets(
802 struct stream_encoder *enc)
803{
804 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
805
806 /* stop generic packets 0 & 1 on HDMI */
807 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
808 HDMI_GENERIC1_CONT, 0,
809 HDMI_GENERIC1_LINE, 0,
810 HDMI_GENERIC1_SEND, 0,
811 HDMI_GENERIC0_CONT, 0,
812 HDMI_GENERIC0_LINE, 0,
813 HDMI_GENERIC0_SEND, 0);
814
815 /* stop generic packets 2 & 3 on HDMI */
816 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
817 HDMI_GENERIC0_CONT, 0,
818 HDMI_GENERIC0_LINE, 0,
819 HDMI_GENERIC0_SEND, 0,
820 HDMI_GENERIC1_CONT, 0,
821 HDMI_GENERIC1_LINE, 0,
822 HDMI_GENERIC1_SEND, 0);
823
824 /* stop generic packets 2 & 3 on HDMI */
825 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
826 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
827 HDMI_GENERIC0_CONT, 0,
828 HDMI_GENERIC0_LINE, 0,
829 HDMI_GENERIC0_SEND, 0,
830 HDMI_GENERIC1_CONT, 0,
831 HDMI_GENERIC1_LINE, 0,
832 HDMI_GENERIC1_SEND, 0);
833
834 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
835 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
836 HDMI_GENERIC0_CONT, 0,
837 HDMI_GENERIC0_LINE, 0,
838 HDMI_GENERIC0_SEND, 0,
839 HDMI_GENERIC1_CONT, 0,
840 HDMI_GENERIC1_LINE, 0,
841 HDMI_GENERIC1_SEND, 0);
842}
843
844static void dce110_stream_encoder_update_dp_info_packets(
845 struct stream_encoder *enc,
846 const struct encoder_info_frame *info_frame)
847{
848 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
849 uint32_t value = 0;
850
851 if (info_frame->vsc.valid)
852 dce110_update_generic_info_packet(
853 enc110,
854 0, /* packetIndex */
855 &info_frame->vsc);
856
857 if (info_frame->spd.valid)
858 dce110_update_generic_info_packet(
859 enc110,
860 2, /* packetIndex */
861 &info_frame->spd);
862
863 if (info_frame->hdrsmd.valid)
864 dce110_update_generic_info_packet(
865 enc110,
866 3, /* packetIndex */
867 &info_frame->hdrsmd);
868
869 /* enable/disable transmission of packet(s).
870 * If enabled, packet transmission begins on the next frame
871 */
872 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
873 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
874 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
875
876 /* This bit is the master enable bit.
877 * When enabling secondary stream engine,
878 * this master bit must also be set.
879 * This register shared with audio info frame.
880 * Therefore we need to enable master bit
881 * if at least on of the fields is not 0
882 */
883 value = REG_READ(DP_SEC_CNTL);
884 if (value)
885 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
886}
887
888static void dce110_stream_encoder_stop_dp_info_packets(
889 struct stream_encoder *enc)
890{
891 /* stop generic packets on DP */
892 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
893 uint32_t value = 0;
894
895 if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
896 REG_SET_7(DP_SEC_CNTL, 0,
897 DP_SEC_GSP0_ENABLE, 0,
898 DP_SEC_GSP1_ENABLE, 0,
899 DP_SEC_GSP2_ENABLE, 0,
900 DP_SEC_GSP3_ENABLE, 0,
901 DP_SEC_AVI_ENABLE, 0,
902 DP_SEC_MPG_ENABLE, 0,
903 DP_SEC_STREAM_ENABLE, 0);
904 }
905
906 /* this register shared with audio info frame.
907 * therefore we need to keep master enabled
908 * if at least one of the fields is not 0 */
909 value = REG_READ(DP_SEC_CNTL);
910 if (value)
911 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
912
913}
914
915static void dce110_stream_encoder_dp_blank(
916 struct dc_link *link,
917 struct stream_encoder *enc)
918{
919 (void)link;
920 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
921 uint32_t reg1 = 0;
922 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
923
924 /* Note: For CZ, we are changing driver default to disable
925 * stream deferred to next VBLANK. If results are positive, we
926 * will make the same change to all DCE versions. There are a
927 * handful of panels that cannot handle disable stream at
928 * HBLANK and will result in a white line flash across the
929 * screen on stream disable. */
930 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
931 if ((reg1 & 0x1) == 0)
932 /*stream not enabled*/
933 return;
934 /* Specify the video stream disable point
935 * (2 = start of the next vertical blank) */
936 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
937 /* Larger delay to wait until VBLANK - use max retry of
938 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
939 * a little more because we may not trust delay accuracy.
940 */
941 max_retries = DP_BLANK_MAX_RETRY * 150;
942
943 /* disable DP stream */
944 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
945
946 /* the encoder stops sending the video stream
947 * at the start of the vertical blanking.
948 * Poll for DP_VID_STREAM_STATUS == 0
949 */
950
951 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
952 0,
953 10, max_retries);
954
955 /* Tell the DP encoder to ignore timing from CRTC, must be done after
956 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
957 * complete, stream status will be stuck in video stream enabled state,
958 * i.e. DP_VID_STREAM_STATUS stuck at 1.
959 */
960
961 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
962}
963
964/* output video stream to link encoder */
965static void dce110_stream_encoder_dp_unblank(
966 struct dc_link *link,
967 struct stream_encoder *enc,
968 const struct encoder_unblank_param *param)
969{
970 (void)link;
971 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
972
973 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
974 uint32_t n_vid = 0x8000;
975 uint32_t m_vid;
976
977 /* M / N = Fstream / Flink
978 * m_vid / n_vid = pixel rate / link rate
979 */
980
981 uint64_t m_vid_l = n_vid;
982
983 m_vid_l *= param->timing.pix_clk_100hz / 10;
984 m_vid_l = div_u64(m_vid_l,
985 param->link_settings.link_rate
986 * LINK_RATE_REF_FREQ_IN_KHZ);
987
988 m_vid = (uint32_t) m_vid_l;
989
990 /* enable auto measurement */
991
992 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
993
994 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
995 * therefore program initial value for Mvid and Nvid
996 */
997
998 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
999
1000 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
1001
1002 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
1003 }
1004
1005 /* set DIG_START to 0x1 to resync FIFO */
1006
1007 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1008
1009 /* switch DP encoder to CRTC data */
1010
1011 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1012
1013 /* wait 100us for DIG/DP logic to prime
1014 * (i.e. a few video lines)
1015 */
1016 udelay(100);
1017
1018 /* the hardware would start sending video at the start of the next DP
1019 * frame (i.e. rising edge of the vblank).
1020 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1021 * register has no effect on enable transition! HW always guarantees
1022 * VID_STREAM enable at start of next frame, and this is not
1023 * programmable
1024 */
1025
1026 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1027}
1028
1029static void dce110_stream_encoder_set_avmute(
1030 struct stream_encoder *enc,
1031 bool enable)
1032{
1033 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1034 unsigned int value = enable ? 1 : 0;
1035
1036 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1037}
1038
1039
1040static void dce110_reset_hdmi_stream_attribute(
1041 struct stream_encoder *enc)
1042{
1043 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1044
1045 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
1046 REG_UPDATE_5(HDMI_CONTROL,
1047 HDMI_PACKET_GEN_VERSION, 1,
1048 HDMI_KEEPOUT_MODE, 1,
1049 HDMI_DEEP_COLOR_ENABLE, 0,
1050 HDMI_DATA_SCRAMBLE_EN, 0,
1051 HDMI_CLOCK_CHANNEL_RATE, 0);
1052 else
1053 REG_UPDATE_3(HDMI_CONTROL,
1054 HDMI_PACKET_GEN_VERSION, 1,
1055 HDMI_KEEPOUT_MODE, 1,
1056 HDMI_DEEP_COLOR_ENABLE, 0);
1057}
1058
1059#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1060#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1061
1062#include "include/audio_types.h"
1063
1064
1065/* 25.2MHz/1.001*/
1066/* 25.2MHz/1.001*/
1067/* 25.2MHz*/
1068/* 27MHz */
1069/* 27MHz*1.001*/
1070/* 27MHz*1.001*/
1071/* 54MHz*/
1072/* 54MHz*1.001*/
1073/* 74.25MHz/1.001*/
1074/* 74.25MHz*/
1075/* 148.5MHz/1.001*/
1076/* 148.5MHz*/
1077
1078static const struct audio_clock_info audio_clock_info_table[16] = {
1079 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1080 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1081 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1082 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1083 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1084 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1085 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1086 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1087 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1088 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1089 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1090 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1091 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1092 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1093 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1094 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1095};
1096
1097static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1098 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1099 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1100 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1101 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1102 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1103 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1104 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1105 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1106 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1107 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1108 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1109 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1110 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1111 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1112};
1113
1114static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1115 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1116 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1117 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1118 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1119 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1120 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1121 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1122 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1123 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1124 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1125 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1126 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1127 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1128 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1129
1130
1131};
1132
1133static union audio_cea_channels speakers_to_channels(
1134 struct audio_speaker_flags speaker_flags)
1135{
1136 union audio_cea_channels cea_channels = {0};
1137
1138 /* these are one to one */
1139 cea_channels.channels.FL = speaker_flags.FL_FR;
1140 cea_channels.channels.FR = speaker_flags.FL_FR;
1141 cea_channels.channels.LFE = speaker_flags.LFE;
1142 cea_channels.channels.FC = speaker_flags.FC;
1143
1144 /* if Rear Left and Right exist move RC speaker to channel 7
1145 * otherwise to channel 5
1146 */
1147 if (speaker_flags.RL_RR) {
1148 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1149 cea_channels.channels.RR = speaker_flags.RL_RR;
1150 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1151 } else {
1152 cea_channels.channels.RL_RC = speaker_flags.RC;
1153 }
1154
1155 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1156 if (speaker_flags.FLC_FRC) {
1157 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1158 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1159 } else {
1160 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1161 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1162 }
1163
1164 return cea_channels;
1165}
1166
1167static uint32_t calc_max_audio_packets_per_line(
1168 const struct audio_crtc_info *crtc_info)
1169{
1170 uint32_t max_packets_per_line;
1171
1172 max_packets_per_line =
1173 crtc_info->h_total - crtc_info->h_active;
1174
1175 if (crtc_info->pixel_repetition)
1176 max_packets_per_line *= crtc_info->pixel_repetition;
1177
1178 /* for other hdmi features */
1179 max_packets_per_line -= 58;
1180 /* for Control Period */
1181 max_packets_per_line -= 16;
1182 /* Number of Audio Packets per Line */
1183 max_packets_per_line /= 32;
1184
1185 return max_packets_per_line;
1186}
1187
1188static void get_audio_clock_info(
1189 enum dc_color_depth color_depth,
1190 uint32_t crtc_pixel_clock_100Hz,
1191 uint32_t actual_pixel_clock_100Hz,
1192 struct audio_clock_info *audio_clock_info)
1193{
1194 const struct audio_clock_info *clock_info;
1195 uint32_t index;
1196 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1197 uint32_t audio_array_size;
1198
1199 switch (color_depth) {
1200 case COLOR_DEPTH_161616:
1201 clock_info = audio_clock_info_table_48bpc;
1202 audio_array_size = ARRAY_SIZE(
1203 audio_clock_info_table_48bpc);
1204 break;
1205 case COLOR_DEPTH_121212:
1206 clock_info = audio_clock_info_table_36bpc;
1207 audio_array_size = ARRAY_SIZE(
1208 audio_clock_info_table_36bpc);
1209 break;
1210 default:
1211 clock_info = audio_clock_info_table;
1212 audio_array_size = ARRAY_SIZE(
1213 audio_clock_info_table);
1214 break;
1215 }
1216
1217 if (clock_info != NULL) {
1218 /* search for exact pixel clock in table */
1219 for (index = 0; index < audio_array_size; index++) {
1220 if (clock_info[index].pixel_clock_in_10khz >
1221 crtc_pixel_clock_in_10khz)
1222 break; /* not match */
1223 else if (clock_info[index].pixel_clock_in_10khz ==
1224 crtc_pixel_clock_in_10khz) {
1225 /* match found */
1226 *audio_clock_info = clock_info[index];
1227 return;
1228 }
1229 }
1230 }
1231
1232 /* not found */
1233 if (actual_pixel_clock_100Hz == 0)
1234 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1235
1236 /* See HDMI spec the table entry under
1237 * pixel clock of "Other". */
1238 audio_clock_info->pixel_clock_in_10khz =
1239 actual_pixel_clock_100Hz / 100;
1240 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1241 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1242 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1243
1244 audio_clock_info->n_32khz = 4096;
1245 audio_clock_info->n_44khz = 6272;
1246 audio_clock_info->n_48khz = 6144;
1247}
1248
1249static void dce110_se_audio_setup(
1250 struct stream_encoder *enc,
1251 unsigned int az_inst,
1252 struct audio_info *audio_info)
1253{
1254 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1255
1256 uint32_t channels = 0;
1257
1258 ASSERT(audio_info);
1259 if (audio_info == NULL)
1260 /* This should not happen.it does so we don't get BSOD*/
1261 return;
1262
1263 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1264
1265 /* setup the audio stream source select (audio -> dig mapping) */
1266 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1267
1268 /* Channel allocation */
1269 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1270}
1271
1272static void dce110_se_setup_hdmi_audio(
1273 struct stream_encoder *enc,
1274 const struct audio_crtc_info *crtc_info)
1275{
1276 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1277
1278 struct audio_clock_info audio_clock_info = {0};
1279 uint32_t max_packets_per_line;
1280
1281 /* For now still do calculation, although this field is ignored when
1282 above HDMI_PACKET_GEN_VERSION set to 1 */
1283 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1284
1285 /* HDMI_AUDIO_PACKET_CONTROL */
1286 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1287 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1288 HDMI_AUDIO_DELAY_EN, 1);
1289
1290 /* AFMT_AUDIO_PACKET_CONTROL */
1291 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1292
1293 /* AFMT_AUDIO_PACKET_CONTROL2 */
1294 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1295 AFMT_AUDIO_LAYOUT_OVRD, 0,
1296 AFMT_60958_OSF_OVRD, 0);
1297
1298 /* HDMI_ACR_PACKET_CONTROL */
1299 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1300 HDMI_ACR_AUTO_SEND, 1,
1301 HDMI_ACR_SOURCE, 0,
1302 HDMI_ACR_AUDIO_PRIORITY, 0);
1303
1304 /* Program audio clock sample/regeneration parameters */
1305 get_audio_clock_info(crtc_info->color_depth,
1306 crtc_info->requested_pixel_clock_100Hz,
1307 crtc_info->calculated_pixel_clock_100Hz,
1308 &audio_clock_info);
1309 DC_LOG_HW_AUDIO(
1310 "\n%s:Input::requested_pixel_clock_100Hz = %d" \
1311 "calculated_pixel_clock_100Hz = %d \n", __func__, \
1312 crtc_info->requested_pixel_clock_100Hz, \
1313 crtc_info->calculated_pixel_clock_100Hz);
1314
1315 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1316 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1317
1318 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1319 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1320
1321 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1322 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1323
1324 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1325 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1326
1327 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1328 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1329
1330 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1331 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1332
1333 /* Video driver cannot know in advance which sample rate will
1334 be used by HD Audio driver
1335 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1336 programmed below in interruppt callback */
1337
1338 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1339 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1340 REG_UPDATE_2(AFMT_60958_0,
1341 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1342 AFMT_60958_CS_CLOCK_ACCURACY, 0);
1343
1344 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1345 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1346
1347 /*AFMT_60958_2 now keep this settings until
1348 * Programming guide comes out*/
1349 REG_UPDATE_6(AFMT_60958_2,
1350 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1351 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1352 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1353 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1354 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1355 AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1356}
1357
1358static void dce110_se_setup_dp_audio(
1359 struct stream_encoder *enc)
1360{
1361 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1362
1363 /* --- DP Audio packet configurations --- */
1364
1365 /* ATP Configuration */
1366 REG_SET(DP_SEC_AUD_N, 0,
1367 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1368
1369 /* Async/auto-calc timestamp mode */
1370 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1371 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1372
1373 /* --- The following are the registers
1374 * copied from the SetupHDMI --- */
1375
1376 /* AFMT_AUDIO_PACKET_CONTROL */
1377 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1378
1379 /* AFMT_AUDIO_PACKET_CONTROL2 */
1380 /* Program the ATP and AIP next */
1381 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1382 AFMT_AUDIO_LAYOUT_OVRD, 0,
1383 AFMT_60958_OSF_OVRD, 0);
1384
1385 /* AFMT_INFOFRAME_CONTROL0 */
1386 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1387
1388 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1389 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1390}
1391
1392static void dce110_se_enable_audio_clock(
1393 struct stream_encoder *enc,
1394 bool enable)
1395{
1396 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1397
1398 if (REG(AFMT_CNTL) == 0)
1399 return; /* DCE8/10 does not have this register */
1400
1401 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1402
1403 /* wait for AFMT clock to turn on,
1404 * expectation: this should complete in 1-2 reads
1405 *
1406 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1407 *
1408 * TODO: wait for clock_on does not work well. May need HW
1409 * program sequence. But audio seems work normally even without wait
1410 * for clock_on status change
1411 */
1412}
1413
1414static void dce110_se_enable_dp_audio(
1415 struct stream_encoder *enc)
1416{
1417 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1418
1419 /* Enable Audio packets */
1420 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1421
1422 /* Program the ATP and AIP next */
1423 REG_UPDATE_2(DP_SEC_CNTL,
1424 DP_SEC_ATP_ENABLE, 1,
1425 DP_SEC_AIP_ENABLE, 1);
1426
1427 /* Program STREAM_ENABLE after all the other enables. */
1428 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1429}
1430
1431static void dce110_se_disable_dp_audio(
1432 struct stream_encoder *enc)
1433{
1434 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1435 uint32_t value = 0;
1436
1437 /* Disable Audio packets */
1438 REG_UPDATE_5(DP_SEC_CNTL,
1439 DP_SEC_ASP_ENABLE, 0,
1440 DP_SEC_ATP_ENABLE, 0,
1441 DP_SEC_AIP_ENABLE, 0,
1442 DP_SEC_ACM_ENABLE, 0,
1443 DP_SEC_STREAM_ENABLE, 0);
1444
1445 /* This register shared with encoder info frame. Therefore we need to
1446 keep master enabled if at least on of the fields is not 0 */
1447 value = REG_READ(DP_SEC_CNTL);
1448 if (value != 0)
1449 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1450
1451}
1452
1453void dce110_se_audio_mute_control(
1454 struct stream_encoder *enc,
1455 bool mute)
1456{
1457 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1458
1459 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1460}
1461
1462void dce110_se_dp_audio_setup(
1463 struct stream_encoder *enc,
1464 unsigned int az_inst,
1465 struct audio_info *info)
1466{
1467 dce110_se_audio_setup(enc, az_inst, info);
1468}
1469
1470void dce110_se_dp_audio_enable(
1471 struct stream_encoder *enc)
1472{
1473 dce110_se_enable_audio_clock(enc, true);
1474 dce110_se_setup_dp_audio(enc);
1475 dce110_se_enable_dp_audio(enc);
1476}
1477
1478void dce110_se_dp_audio_disable(
1479 struct stream_encoder *enc)
1480{
1481 dce110_se_disable_dp_audio(enc);
1482 dce110_se_enable_audio_clock(enc, false);
1483}
1484
1485void dce110_se_hdmi_audio_setup(
1486 struct stream_encoder *enc,
1487 unsigned int az_inst,
1488 struct audio_info *info,
1489 struct audio_crtc_info *audio_crtc_info)
1490{
1491 dce110_se_enable_audio_clock(enc, true);
1492 dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1493 dce110_se_audio_setup(enc, az_inst, info);
1494}
1495
1496void dce110_se_hdmi_audio_disable(
1497 struct stream_encoder *enc)
1498{
1499 dce110_se_enable_audio_clock(enc, false);
1500}
1501
1502
1503static void setup_stereo_sync(
1504 struct stream_encoder *enc,
1505 int tg_inst, bool enable)
1506{
1507 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1508 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1509 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1510}
1511
1512static void dig_connect_to_otg(
1513 struct stream_encoder *enc,
1514 int tg_inst)
1515{
1516 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1517
1518 if (enc->id == ENGINE_ID_DACA || enc->id == ENGINE_ID_DACB)
1519 REG_UPDATE(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, tg_inst);
1520 else
1521 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1522}
1523
1524static unsigned int dig_source_otg(
1525 struct stream_encoder *enc)
1526{
1527 uint32_t tg_inst = 0;
1528 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1529
1530 if (enc->id == ENGINE_ID_DACA || enc->id == ENGINE_ID_DACB)
1531 REG_GET(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, &tg_inst);
1532 else
1533 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1534
1535 return tg_inst;
1536}
1537
1538static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1539 .dp_set_stream_attribute =
1540 dce110_stream_encoder_dp_set_stream_attribute,
1541 .hdmi_set_stream_attribute =
1542 dce110_stream_encoder_hdmi_set_stream_attribute,
1543 .dvi_set_stream_attribute =
1544 dce110_stream_encoder_dvi_set_stream_attribute,
1545 .lvds_set_stream_attribute =
1546 dce110_stream_encoder_lvds_set_stream_attribute,
1547 .set_throttled_vcp_size =
1548 dce110_stream_encoder_set_throttled_vcp_size,
1549 .update_hdmi_info_packets =
1550 dce110_stream_encoder_update_hdmi_info_packets,
1551 .stop_hdmi_info_packets =
1552 dce110_stream_encoder_stop_hdmi_info_packets,
1553 .update_dp_info_packets =
1554 dce110_stream_encoder_update_dp_info_packets,
1555 .stop_dp_info_packets =
1556 dce110_stream_encoder_stop_dp_info_packets,
1557 .dp_blank =
1558 dce110_stream_encoder_dp_blank,
1559 .dp_unblank =
1560 dce110_stream_encoder_dp_unblank,
1561 .audio_mute_control = dce110_se_audio_mute_control,
1562
1563 .dp_audio_setup = dce110_se_dp_audio_setup,
1564 .dp_audio_enable = dce110_se_dp_audio_enable,
1565 .dp_audio_disable = dce110_se_dp_audio_disable,
1566
1567 .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1568 .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1569 .setup_stereo_sync = setup_stereo_sync,
1570 .set_avmute = dce110_stream_encoder_set_avmute,
1571 .dig_connect_to_otg = dig_connect_to_otg,
1572 .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
1573 .dig_source_otg = dig_source_otg,
1574};
1575
1576void dce110_stream_encoder_construct(
1577 struct dce110_stream_encoder *enc110,
1578 struct dc_context *ctx,
1579 struct dc_bios *bp,
1580 enum engine_id eng_id,
1581 const struct dce110_stream_enc_registers *regs,
1582 const struct dce_stream_encoder_shift *se_shift,
1583 const struct dce_stream_encoder_mask *se_mask)
1584{
1585 enc110->base.funcs = &dce110_str_enc_funcs;
1586 enc110->base.ctx = ctx;
1587 enc110->base.id = eng_id;
1588 enc110->base.bp = bp;
1589 enc110->regs = regs;
1590 enc110->se_shift = se_shift;
1591 enc110->se_mask = se_mask;
1592}
1593
1594static const struct stream_encoder_funcs dce110_an_str_enc_funcs = {
1595 .dig_connect_to_otg = dig_connect_to_otg,
1596 .dig_source_otg = dig_source_otg,
1597};
1598
1599void dce110_analog_stream_encoder_construct(
1600 struct dce110_stream_encoder *enc110,
1601 struct dc_context *ctx,
1602 struct dc_bios *bp,
1603 enum engine_id eng_id,
1604 const struct dce110_stream_enc_registers *regs,
1605 const struct dce_stream_encoder_shift *se_shift,
1606 const struct dce_stream_encoder_mask *se_mask)
1607{
1608 enc110->base.funcs = &dce110_an_str_enc_funcs;
1609 enc110->base.ctx = ctx;
1610 enc110->base.id = eng_id;
1611 enc110->base.bp = bp;
1612 enc110->regs = regs;
1613 enc110->se_shift = se_shift;
1614 enc110->se_mask = se_mask;
1615}