| 1 | |
| 2 | * Copyright 2012-15 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 | * Authors: AMD
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| 23 | *
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| 24 |
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| 25 |
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| 26 | #ifndef __DC_STREAM_ENCODER_DCE110_H__
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| 27 | #define __DC_STREAM_ENCODER_DCE110_H__
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| 28 |
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| 29 | #include "stream_encoder.h"
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| 30 |
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| 31 | #define DCE110STRENC_FROM_STRENC(stream_encoder)\
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| 32 | container_of(stream_encoder, struct dce110_stream_encoder, base)
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| 33 |
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| 34 | #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
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| 35 | #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
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| 36 | #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
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| 37 | #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
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| 38 | #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
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| 39 | #endif
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| 40 |
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| 41 |
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| 42 | #define SE_COMMON_REG_LIST_DCE_BASE(id) \
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| 43 | SE_COMMON_REG_LIST_BASE(id),\
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| 44 | SRI(AFMT_AVI_INFO0, DIG, id), \
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| 45 | SRI(AFMT_AVI_INFO1, DIG, id), \
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| 46 | SRI(AFMT_AVI_INFO2, DIG, id), \
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| 47 | SRI(AFMT_AVI_INFO3, DIG, id)
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| 48 |
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| 49 | #define SE_COMMON_REG_LIST_BASE(id) \
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| 50 | SRI(AFMT_GENERIC_0, DIG, id), \
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| 51 | SRI(AFMT_GENERIC_1, DIG, id), \
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| 52 | SRI(AFMT_GENERIC_2, DIG, id), \
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| 53 | SRI(AFMT_GENERIC_3, DIG, id), \
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| 54 | SRI(AFMT_GENERIC_4, DIG, id), \
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| 55 | SRI(AFMT_GENERIC_5, DIG, id), \
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| 56 | SRI(AFMT_GENERIC_6, DIG, id), \
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| 57 | SRI(AFMT_GENERIC_7, DIG, id), \
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| 58 | SRI(AFMT_GENERIC_HDR, DIG, id), \
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| 59 | SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
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| 60 | SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
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| 61 | SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
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| 62 | SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
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| 63 | SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
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| 64 | SRI(AFMT_60958_0, DIG, id), \
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| 65 | SRI(AFMT_60958_1, DIG, id), \
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| 66 | SRI(AFMT_60958_2, DIG, id), \
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| 67 | SRI(DIG_FE_CNTL, DIG, id), \
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| 68 | SR(DAC_SOURCE_SELECT), \
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| 69 | SRI(HDMI_CONTROL, DIG, id), \
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| 70 | SRI(HDMI_GC, DIG, id), \
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| 71 | SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
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| 72 | SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
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| 73 | SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
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| 74 | SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
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| 75 | SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
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| 76 | SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
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| 77 | SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
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| 78 | SRI(HDMI_ACR_32_0, DIG, id),\
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| 79 | SRI(HDMI_ACR_32_1, DIG, id),\
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| 80 | SRI(HDMI_ACR_44_0, DIG, id),\
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| 81 | SRI(HDMI_ACR_44_1, DIG, id),\
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| 82 | SRI(HDMI_ACR_48_0, DIG, id),\
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| 83 | SRI(HDMI_ACR_48_1, DIG, id),\
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| 84 | SRI(TMDS_CNTL, DIG, id), \
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| 85 | SRI(DP_MSE_RATE_CNTL, DP, id), \
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| 86 | SRI(DP_MSE_RATE_UPDATE, DP, id), \
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| 87 | SRI(DP_PIXEL_FORMAT, DP, id), \
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| 88 | SRI(DP_SEC_CNTL, DP, id), \
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| 89 | SRI(DP_STEER_FIFO, DP, id), \
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| 90 | SRI(DP_VID_M, DP, id), \
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| 91 | SRI(DP_VID_N, DP, id), \
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| 92 | SRI(DP_VID_STREAM_CNTL, DP, id), \
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| 93 | SRI(DP_VID_TIMING, DP, id), \
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| 94 | SRI(DP_SEC_AUD_N, DP, id), \
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| 95 | SRI(DP_SEC_TIMESTAMP, DP, id)
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| 96 |
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| 97 | #define SE_COMMON_REG_LIST(id)\
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| 98 | SE_COMMON_REG_LIST_DCE_BASE(id), \
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| 99 | SRI(AFMT_CNTL, DIG, id), \
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| 100 | SRI(DP_MSA_MISC, DP, id)
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| 101 |
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| 102 | #define SE_DCN_REG_LIST(id)\
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| 103 | SE_COMMON_REG_LIST_BASE(id),\
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| 104 | SRI(AFMT_CNTL, DIG, id),\
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| 105 | SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
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| 106 | SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
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| 107 | SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
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| 108 | SRI(DP_DB_CNTL, DP, id), \
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| 109 | SRI(DP_MSA_MISC, DP, id), \
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| 110 | SRI(DP_MSA_COLORIMETRY, DP, id), \
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| 111 | SRI(DP_MSA_TIMING_PARAM1, DP, id), \
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| 112 | SRI(DP_MSA_TIMING_PARAM2, DP, id), \
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| 113 | SRI(DP_MSA_TIMING_PARAM3, DP, id), \
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| 114 | SRI(DP_MSA_TIMING_PARAM4, DP, id), \
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| 115 | SRI(HDMI_DB_CONTROL, DIG, id)
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| 116 |
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| 117 | #define SE_SF(reg_name, field_name, post_fix)\
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| 118 | .field_name = reg_name ## __ ## field_name ## post_fix
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| 119 |
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| 120 | #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
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| 121 | SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
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| 122 | SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
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| 123 | SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
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| 124 | SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
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| 125 | SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
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| 126 | SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
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| 127 | SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
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| 128 | SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
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| 129 | SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
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| 130 | SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
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| 131 | SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
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| 132 | SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
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| 133 | SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
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| 134 | SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
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| 135 | SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
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| 136 | SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
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| 137 | SE_SF(DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
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| 138 | SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
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| 139 | SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
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| 140 | SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
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| 141 | SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
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| 142 | SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
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| 143 | SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
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| 144 | SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
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| 145 | SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\
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| 146 | SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
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| 147 | SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
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| 148 | SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
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| 149 | SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
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| 150 | SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
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| 151 | SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
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| 152 | SE_SF(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
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| 153 | SE_SF(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
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| 154 | SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
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| 155 | SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
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| 156 | SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
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| 157 | SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
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| 158 | SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
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| 159 | SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
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| 160 | SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
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| 161 | SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
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| 162 | SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
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| 163 | SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
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| 164 | SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
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| 165 | SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
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| 166 | SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
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| 167 | SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
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| 168 | SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
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| 169 | SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
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| 170 | SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
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| 171 | SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
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| 172 | SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
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| 173 | SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
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| 174 | SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
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| 175 | SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
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| 176 | SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
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| 177 | SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
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| 178 | SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
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| 179 | SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
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| 180 | SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
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| 181 | SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
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| 182 | SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
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| 183 | SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
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| 184 | SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
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| 185 | SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
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| 186 | SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
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| 187 | SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
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| 188 | SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
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| 189 | SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
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| 190 | SE_SF(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
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| 191 | SE_SF(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
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| 192 | SE_SF(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
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| 193 | SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
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| 194 | SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
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| 195 | SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
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| 196 | SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
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| 197 | SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
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| 198 | SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
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| 199 | SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
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| 200 | SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
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| 201 | SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
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| 202 | SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
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| 203 | SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
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| 204 | SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
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| 205 | SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
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| 206 | SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
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| 207 |
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| 208 | #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
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| 209 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
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| 210 | SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
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| 211 | SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
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| 212 | SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
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| 213 | SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
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| 214 | SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
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| 215 | SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
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| 216 | SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
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| 217 | SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
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| 218 | SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
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| 219 | SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
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| 220 | SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
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| 221 | SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
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| 222 | SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
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| 223 | SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
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| 224 | SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
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| 225 | SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
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| 226 | SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
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| 227 | SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
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| 228 | SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
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| 229 | SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
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| 230 | SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\
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| 231 | SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
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| 232 | SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
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| 233 | SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
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| 234 | SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
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| 235 | SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
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| 236 | SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
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| 237 | SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
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| 238 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
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| 239 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
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| 240 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
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| 241 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
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| 242 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
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| 243 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
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| 244 | SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
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| 245 | SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
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| 246 | SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
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| 247 | SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
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| 248 | SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
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| 249 | SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
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| 250 | SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
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| 251 | SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
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| 252 | SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
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| 253 | SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
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| 254 | SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
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| 255 | SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
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| 256 | SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
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| 257 | SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
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| 258 | SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
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| 259 | SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
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| 260 | SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
|
| 261 | SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
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| 262 | SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
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| 263 | SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
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| 264 | SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
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| 265 | SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
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| 266 | SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
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| 267 | SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
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| 268 | SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
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| 269 | SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
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| 270 | SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
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| 271 | SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
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| 272 | SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
|
| 273 | SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
|
| 274 | SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
|
| 275 | SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
|
| 276 | SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
|
| 277 | SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
|
| 278 | SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
|
| 279 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
|
| 280 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
|
| 281 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
|
| 282 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
|
| 283 | SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
|
| 284 | SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
|
| 285 | SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
|
| 286 | SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
|
| 287 | SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
|
| 288 | SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
|
| 289 | SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
|
| 290 | SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
|
| 291 |
|
| 292 | #define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\
|
| 293 | SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
|
| 294 | SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
|
| 295 | SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
|
| 296 | SE_SF(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, mask_sh)
|
| 297 |
|
| 298 | #define SE_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
|
| 299 | SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
|
| 300 | SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
|
| 301 | SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
|
| 302 | SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
|
| 303 | SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
|
| 304 | SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
|
| 305 | SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
|
| 306 | SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
|
| 307 |
|
| 308 | #define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\
|
| 309 | SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
|
| 310 | SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
|
| 311 | SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
|
| 312 | SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
|
| 313 | SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
|
| 314 | SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
|
| 315 | SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
|
| 316 |
|
| 317 | #define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\
|
| 318 | SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
|
| 319 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
|
| 320 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
|
| 321 | SE_SF(DP0_DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
|
| 322 | SE_SF(DP0_DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
|
| 323 | SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
|
| 324 | SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
|
| 325 | SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
|
| 326 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
|
| 327 | SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
|
| 328 | SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
|
| 329 |
|
| 330 | #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
|
| 331 | SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
|
| 332 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
|
| 333 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
|
| 334 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
|
| 335 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
|
| 336 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
|
| 337 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
|
| 338 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
|
| 339 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
|
| 340 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
|
| 341 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
|
| 342 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
|
| 343 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
|
| 344 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
|
| 345 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
|
| 346 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
|
| 347 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
|
| 348 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
|
| 349 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
|
| 350 | SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
|
| 351 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
|
| 352 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
|
| 353 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
|
| 354 | SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
|
| 355 | SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
|
| 356 | SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
|
| 357 | SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
|
| 358 | SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
|
| 359 | SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
|
| 360 | SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
|
| 361 | SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
|
| 362 | SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
|
| 363 | SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
|
| 364 | SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
|
| 365 | SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
|
| 366 | SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
|
| 367 | SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
|
| 368 | SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
|
| 369 |
|
| 370 | struct dce_stream_encoder_shift {
|
| 371 | uint8_t AFMT_GENERIC_INDEX;
|
| 372 | uint8_t AFMT_GENERIC0_UPDATE;
|
| 373 | uint8_t AFMT_GENERIC2_UPDATE;
|
| 374 | uint8_t AFMT_GENERIC_HB0;
|
| 375 | uint8_t AFMT_GENERIC_HB1;
|
| 376 | uint8_t AFMT_GENERIC_HB2;
|
| 377 | uint8_t AFMT_GENERIC_HB3;
|
| 378 | uint8_t AFMT_GENERIC_LOCK_STATUS;
|
| 379 | uint8_t AFMT_GENERIC_CONFLICT;
|
| 380 | uint8_t AFMT_GENERIC_CONFLICT_CLR;
|
| 381 | uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
|
| 382 | uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
|
| 383 | uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
|
| 384 | uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
|
| 385 | uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
|
| 386 | uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
|
| 387 | uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
|
| 388 | uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
|
| 389 | uint8_t AFMT_GENERIC0_FRAME_UPDATE;
|
| 390 | uint8_t AFMT_GENERIC1_FRAME_UPDATE;
|
| 391 | uint8_t AFMT_GENERIC2_FRAME_UPDATE;
|
| 392 | uint8_t AFMT_GENERIC3_FRAME_UPDATE;
|
| 393 | uint8_t AFMT_GENERIC4_FRAME_UPDATE;
|
| 394 | uint8_t AFMT_GENERIC5_FRAME_UPDATE;
|
| 395 | uint8_t AFMT_GENERIC6_FRAME_UPDATE;
|
| 396 | uint8_t AFMT_GENERIC7_FRAME_UPDATE;
|
| 397 | uint8_t HDMI_GENERIC0_CONT;
|
| 398 | uint8_t HDMI_GENERIC0_SEND;
|
| 399 | uint8_t HDMI_GENERIC0_LINE;
|
| 400 | uint8_t HDMI_GENERIC1_CONT;
|
| 401 | uint8_t HDMI_GENERIC1_SEND;
|
| 402 | uint8_t HDMI_GENERIC1_LINE;
|
| 403 | uint8_t DP_PIXEL_ENCODING;
|
| 404 | uint8_t DP_COMPONENT_DEPTH;
|
| 405 | uint8_t DP_DYN_RANGE;
|
| 406 | uint8_t DP_YCBCR_RANGE;
|
| 407 | uint8_t HDMI_PACKET_GEN_VERSION;
|
| 408 | uint8_t HDMI_KEEPOUT_MODE;
|
| 409 | uint8_t HDMI_DEEP_COLOR_ENABLE;
|
| 410 | uint8_t HDMI_CLOCK_CHANNEL_RATE;
|
| 411 | uint8_t HDMI_DEEP_COLOR_DEPTH;
|
| 412 | uint8_t HDMI_GC_CONT;
|
| 413 | uint8_t HDMI_GC_SEND;
|
| 414 | uint8_t HDMI_NULL_SEND;
|
| 415 | uint8_t HDMI_DATA_SCRAMBLE_EN;
|
| 416 | uint8_t HDMI_ACP_SEND;
|
| 417 | uint8_t HDMI_AUDIO_INFO_SEND;
|
| 418 | uint8_t AFMT_AUDIO_INFO_UPDATE;
|
| 419 | uint8_t HDMI_AUDIO_INFO_LINE;
|
| 420 | uint8_t HDMI_GC_AVMUTE;
|
| 421 | uint8_t DP_MSE_RATE_X;
|
| 422 | uint8_t DP_MSE_RATE_Y;
|
| 423 | uint8_t DP_MSE_RATE_UPDATE_PENDING;
|
| 424 | uint8_t AFMT_AVI_INFO_VERSION;
|
| 425 | uint8_t HDMI_AVI_INFO_SEND;
|
| 426 | uint8_t HDMI_AVI_INFO_CONT;
|
| 427 | uint8_t HDMI_AVI_INFO_LINE;
|
| 428 | uint8_t DP_SEC_GSP0_ENABLE;
|
| 429 | uint8_t DP_SEC_STREAM_ENABLE;
|
| 430 | uint8_t DP_SEC_GSP1_ENABLE;
|
| 431 | uint8_t DP_SEC_GSP2_ENABLE;
|
| 432 | uint8_t DP_SEC_GSP3_ENABLE;
|
| 433 | uint8_t DP_SEC_GSP4_ENABLE;
|
| 434 | uint8_t DP_SEC_GSP5_ENABLE;
|
| 435 | uint8_t DP_SEC_GSP6_ENABLE;
|
| 436 | uint8_t DP_SEC_GSP7_ENABLE;
|
| 437 | uint8_t DP_SEC_AVI_ENABLE;
|
| 438 | uint8_t DP_SEC_MPG_ENABLE;
|
| 439 | uint8_t DP_VID_STREAM_DIS_DEFER;
|
| 440 | uint8_t DP_VID_STREAM_ENABLE;
|
| 441 | uint8_t DP_VID_STREAM_STATUS;
|
| 442 | uint8_t DP_STEER_FIFO_RESET;
|
| 443 | uint8_t DP_VID_M_N_GEN_EN;
|
| 444 | uint8_t DP_VID_N;
|
| 445 | uint8_t DP_VID_M;
|
| 446 | uint8_t DIG_START;
|
| 447 | uint8_t AFMT_AUDIO_SRC_SELECT;
|
| 448 | uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
|
| 449 | uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
|
| 450 | uint8_t HDMI_AUDIO_DELAY_EN;
|
| 451 | uint8_t AFMT_60958_CS_UPDATE;
|
| 452 | uint8_t AFMT_AUDIO_LAYOUT_OVRD;
|
| 453 | uint8_t AFMT_60958_OSF_OVRD;
|
| 454 | uint8_t HDMI_ACR_AUTO_SEND;
|
| 455 | uint8_t HDMI_ACR_SOURCE;
|
| 456 | uint8_t HDMI_ACR_AUDIO_PRIORITY;
|
| 457 | uint8_t HDMI_ACR_CTS_32;
|
| 458 | uint8_t HDMI_ACR_N_32;
|
| 459 | uint8_t HDMI_ACR_CTS_44;
|
| 460 | uint8_t HDMI_ACR_N_44;
|
| 461 | uint8_t HDMI_ACR_CTS_48;
|
| 462 | uint8_t HDMI_ACR_N_48;
|
| 463 | uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
|
| 464 | uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
|
| 465 | uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
|
| 466 | uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
|
| 467 | uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
|
| 468 | uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
|
| 469 | uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
|
| 470 | uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
|
| 471 | uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
|
| 472 | uint8_t DP_SEC_AUD_N;
|
| 473 | uint8_t DP_SEC_TIMESTAMP_MODE;
|
| 474 | uint8_t DP_SEC_ASP_ENABLE;
|
| 475 | uint8_t DP_SEC_ATP_ENABLE;
|
| 476 | uint8_t DP_SEC_AIP_ENABLE;
|
| 477 | uint8_t DP_SEC_ACM_ENABLE;
|
| 478 | uint8_t AFMT_AUDIO_SAMPLE_SEND;
|
| 479 | uint8_t AFMT_AUDIO_CLOCK_EN;
|
| 480 | uint8_t TMDS_PIXEL_ENCODING;
|
| 481 | uint8_t TMDS_COLOR_FORMAT;
|
| 482 | uint8_t DIG_STEREOSYNC_SELECT;
|
| 483 | uint8_t DIG_STEREOSYNC_GATE_EN;
|
| 484 | uint8_t DP_DB_DISABLE;
|
| 485 | uint8_t DP_MSA_MISC0;
|
| 486 | uint8_t DP_MSA_HTOTAL;
|
| 487 | uint8_t DP_MSA_VTOTAL;
|
| 488 | uint8_t DP_MSA_HSTART;
|
| 489 | uint8_t DP_MSA_VSTART;
|
| 490 | uint8_t DP_MSA_HSYNCWIDTH;
|
| 491 | uint8_t DP_MSA_HSYNCPOLARITY;
|
| 492 | uint8_t DP_MSA_VSYNCWIDTH;
|
| 493 | uint8_t DP_MSA_VSYNCPOLARITY;
|
| 494 | uint8_t DP_MSA_HWIDTH;
|
| 495 | uint8_t DP_MSA_VHEIGHT;
|
| 496 | uint8_t HDMI_DB_DISABLE;
|
| 497 | uint8_t DP_VID_N_MUL;
|
| 498 | uint8_t DP_VID_M_DOUBLE_VALUE_EN;
|
| 499 | uint8_t DIG_SOURCE_SELECT;
|
| 500 | uint8_t DAC_SOURCE_SELECT;
|
| 501 | };
|
| 502 |
|
| 503 | struct dce_stream_encoder_mask {
|
| 504 | uint32_t AFMT_GENERIC_INDEX;
|
| 505 | uint32_t AFMT_GENERIC0_UPDATE;
|
| 506 | uint32_t AFMT_GENERIC2_UPDATE;
|
| 507 | uint32_t AFMT_GENERIC_HB0;
|
| 508 | uint32_t AFMT_GENERIC_HB1;
|
| 509 | uint32_t AFMT_GENERIC_HB2;
|
| 510 | uint32_t AFMT_GENERIC_HB3;
|
| 511 | uint32_t AFMT_GENERIC_LOCK_STATUS;
|
| 512 | uint32_t AFMT_GENERIC_CONFLICT;
|
| 513 | uint32_t AFMT_GENERIC_CONFLICT_CLR;
|
| 514 | uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
|
| 515 | uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
|
| 516 | uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
|
| 517 | uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
|
| 518 | uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
|
| 519 | uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
|
| 520 | uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
|
| 521 | uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
|
| 522 | uint32_t AFMT_GENERIC0_FRAME_UPDATE;
|
| 523 | uint32_t AFMT_GENERIC1_FRAME_UPDATE;
|
| 524 | uint32_t AFMT_GENERIC2_FRAME_UPDATE;
|
| 525 | uint32_t AFMT_GENERIC3_FRAME_UPDATE;
|
| 526 | uint32_t AFMT_GENERIC4_FRAME_UPDATE;
|
| 527 | uint32_t AFMT_GENERIC5_FRAME_UPDATE;
|
| 528 | uint32_t AFMT_GENERIC6_FRAME_UPDATE;
|
| 529 | uint32_t AFMT_GENERIC7_FRAME_UPDATE;
|
| 530 | uint32_t HDMI_GENERIC0_CONT;
|
| 531 | uint32_t HDMI_GENERIC0_SEND;
|
| 532 | uint32_t HDMI_GENERIC0_LINE;
|
| 533 | uint32_t HDMI_GENERIC1_CONT;
|
| 534 | uint32_t HDMI_GENERIC1_SEND;
|
| 535 | uint32_t HDMI_GENERIC1_LINE;
|
| 536 | uint32_t DP_PIXEL_ENCODING;
|
| 537 | uint32_t DP_COMPONENT_DEPTH;
|
| 538 | uint32_t DP_DYN_RANGE;
|
| 539 | uint32_t DP_YCBCR_RANGE;
|
| 540 | uint32_t HDMI_PACKET_GEN_VERSION;
|
| 541 | uint32_t HDMI_KEEPOUT_MODE;
|
| 542 | uint32_t HDMI_DEEP_COLOR_ENABLE;
|
| 543 | uint32_t HDMI_CLOCK_CHANNEL_RATE;
|
| 544 | uint32_t HDMI_DEEP_COLOR_DEPTH;
|
| 545 | uint32_t HDMI_GC_CONT;
|
| 546 | uint32_t HDMI_GC_SEND;
|
| 547 | uint32_t HDMI_NULL_SEND;
|
| 548 | uint32_t HDMI_DATA_SCRAMBLE_EN;
|
| 549 | uint32_t HDMI_ACP_SEND;
|
| 550 | uint32_t HDMI_AUDIO_INFO_SEND;
|
| 551 | uint32_t AFMT_AUDIO_INFO_UPDATE;
|
| 552 | uint32_t HDMI_AUDIO_INFO_LINE;
|
| 553 | uint32_t HDMI_GC_AVMUTE;
|
| 554 | uint32_t DP_MSE_RATE_X;
|
| 555 | uint32_t DP_MSE_RATE_Y;
|
| 556 | uint32_t DP_MSE_RATE_UPDATE_PENDING;
|
| 557 | uint32_t AFMT_AVI_INFO_VERSION;
|
| 558 | uint32_t HDMI_AVI_INFO_SEND;
|
| 559 | uint32_t HDMI_AVI_INFO_CONT;
|
| 560 | uint32_t HDMI_AVI_INFO_LINE;
|
| 561 | uint32_t DP_SEC_GSP0_ENABLE;
|
| 562 | uint32_t DP_SEC_STREAM_ENABLE;
|
| 563 | uint32_t DP_SEC_GSP1_ENABLE;
|
| 564 | uint32_t DP_SEC_GSP2_ENABLE;
|
| 565 | uint32_t DP_SEC_GSP3_ENABLE;
|
| 566 | uint32_t DP_SEC_GSP4_ENABLE;
|
| 567 | uint32_t DP_SEC_GSP5_ENABLE;
|
| 568 | uint32_t DP_SEC_GSP6_ENABLE;
|
| 569 | uint32_t DP_SEC_GSP7_ENABLE;
|
| 570 | uint32_t DP_SEC_AVI_ENABLE;
|
| 571 | uint32_t DP_SEC_MPG_ENABLE;
|
| 572 | uint32_t DP_VID_STREAM_DIS_DEFER;
|
| 573 | uint32_t DP_VID_STREAM_ENABLE;
|
| 574 | uint32_t DP_VID_STREAM_STATUS;
|
| 575 | uint32_t DP_STEER_FIFO_RESET;
|
| 576 | uint32_t DP_VID_M_N_GEN_EN;
|
| 577 | uint32_t DP_VID_N;
|
| 578 | uint32_t DP_VID_M;
|
| 579 | uint32_t DIG_START;
|
| 580 | uint32_t AFMT_AUDIO_SRC_SELECT;
|
| 581 | uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
|
| 582 | uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
|
| 583 | uint32_t HDMI_AUDIO_DELAY_EN;
|
| 584 | uint32_t AFMT_60958_CS_UPDATE;
|
| 585 | uint32_t AFMT_AUDIO_LAYOUT_OVRD;
|
| 586 | uint32_t AFMT_60958_OSF_OVRD;
|
| 587 | uint32_t HDMI_ACR_AUTO_SEND;
|
| 588 | uint32_t HDMI_ACR_SOURCE;
|
| 589 | uint32_t HDMI_ACR_AUDIO_PRIORITY;
|
| 590 | uint32_t HDMI_ACR_CTS_32;
|
| 591 | uint32_t HDMI_ACR_N_32;
|
| 592 | uint32_t HDMI_ACR_CTS_44;
|
| 593 | uint32_t HDMI_ACR_N_44;
|
| 594 | uint32_t HDMI_ACR_CTS_48;
|
| 595 | uint32_t HDMI_ACR_N_48;
|
| 596 | uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
|
| 597 | uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
|
| 598 | uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
|
| 599 | uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
|
| 600 | uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
|
| 601 | uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
|
| 602 | uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
|
| 603 | uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
|
| 604 | uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
|
| 605 | uint32_t DP_SEC_AUD_N;
|
| 606 | uint32_t DP_SEC_TIMESTAMP_MODE;
|
| 607 | uint32_t DP_SEC_ASP_ENABLE;
|
| 608 | uint32_t DP_SEC_ATP_ENABLE;
|
| 609 | uint32_t DP_SEC_AIP_ENABLE;
|
| 610 | uint32_t DP_SEC_ACM_ENABLE;
|
| 611 | uint32_t AFMT_AUDIO_SAMPLE_SEND;
|
| 612 | uint32_t AFMT_AUDIO_CLOCK_EN;
|
| 613 | uint32_t TMDS_PIXEL_ENCODING;
|
| 614 | uint32_t DIG_STEREOSYNC_SELECT;
|
| 615 | uint32_t DIG_STEREOSYNC_GATE_EN;
|
| 616 | uint32_t TMDS_COLOR_FORMAT;
|
| 617 | uint32_t DP_DB_DISABLE;
|
| 618 | uint32_t DP_MSA_MISC0;
|
| 619 | uint32_t DP_MSA_HTOTAL;
|
| 620 | uint32_t DP_MSA_VTOTAL;
|
| 621 | uint32_t DP_MSA_HSTART;
|
| 622 | uint32_t DP_MSA_VSTART;
|
| 623 | uint32_t DP_MSA_HSYNCWIDTH;
|
| 624 | uint32_t DP_MSA_HSYNCPOLARITY;
|
| 625 | uint32_t DP_MSA_VSYNCWIDTH;
|
| 626 | uint32_t DP_MSA_VSYNCPOLARITY;
|
| 627 | uint32_t DP_MSA_HWIDTH;
|
| 628 | uint32_t DP_MSA_VHEIGHT;
|
| 629 | uint32_t HDMI_DB_DISABLE;
|
| 630 | uint32_t DP_VID_N_MUL;
|
| 631 | uint32_t DP_VID_M_DOUBLE_VALUE_EN;
|
| 632 | uint32_t DIG_SOURCE_SELECT;
|
| 633 | uint32_t DAC_SOURCE_SELECT;
|
| 634 | };
|
| 635 |
|
| 636 | struct dce110_stream_enc_registers {
|
| 637 | uint32_t AFMT_CNTL;
|
| 638 | uint32_t AFMT_AVI_INFO0;
|
| 639 | uint32_t AFMT_AVI_INFO1;
|
| 640 | uint32_t AFMT_AVI_INFO2;
|
| 641 | uint32_t AFMT_AVI_INFO3;
|
| 642 | uint32_t AFMT_GENERIC_0;
|
| 643 | uint32_t AFMT_GENERIC_1;
|
| 644 | uint32_t AFMT_GENERIC_2;
|
| 645 | uint32_t AFMT_GENERIC_3;
|
| 646 | uint32_t AFMT_GENERIC_4;
|
| 647 | uint32_t AFMT_GENERIC_5;
|
| 648 | uint32_t AFMT_GENERIC_6;
|
| 649 | uint32_t AFMT_GENERIC_7;
|
| 650 | uint32_t AFMT_GENERIC_HDR;
|
| 651 | uint32_t AFMT_INFOFRAME_CONTROL0;
|
| 652 | uint32_t AFMT_VBI_PACKET_CONTROL;
|
| 653 | uint32_t AFMT_VBI_PACKET_CONTROL1;
|
| 654 | uint32_t AFMT_AUDIO_PACKET_CONTROL;
|
| 655 | uint32_t AFMT_AUDIO_PACKET_CONTROL2;
|
| 656 | uint32_t AFMT_AUDIO_SRC_CONTROL;
|
| 657 | uint32_t AFMT_60958_0;
|
| 658 | uint32_t AFMT_60958_1;
|
| 659 | uint32_t AFMT_60958_2;
|
| 660 | uint32_t DIG_FE_CNTL;
|
| 661 | uint32_t DAC_SOURCE_SELECT;
|
| 662 | uint32_t DP_MSE_RATE_CNTL;
|
| 663 | uint32_t DP_MSE_RATE_UPDATE;
|
| 664 | uint32_t DP_PIXEL_FORMAT;
|
| 665 | uint32_t DP_SEC_CNTL;
|
| 666 | uint32_t DP_STEER_FIFO;
|
| 667 | uint32_t DP_VID_M;
|
| 668 | uint32_t DP_VID_N;
|
| 669 | uint32_t DP_VID_STREAM_CNTL;
|
| 670 | uint32_t DP_VID_TIMING;
|
| 671 | uint32_t DP_SEC_AUD_N;
|
| 672 | uint32_t DP_SEC_TIMESTAMP;
|
| 673 | uint32_t HDMI_CONTROL;
|
| 674 | uint32_t HDMI_GC;
|
| 675 | uint32_t HDMI_GENERIC_PACKET_CONTROL0;
|
| 676 | uint32_t HDMI_GENERIC_PACKET_CONTROL1;
|
| 677 | uint32_t HDMI_GENERIC_PACKET_CONTROL2;
|
| 678 | uint32_t HDMI_GENERIC_PACKET_CONTROL3;
|
| 679 | uint32_t HDMI_INFOFRAME_CONTROL0;
|
| 680 | uint32_t HDMI_INFOFRAME_CONTROL1;
|
| 681 | uint32_t HDMI_VBI_PACKET_CONTROL;
|
| 682 | uint32_t HDMI_AUDIO_PACKET_CONTROL;
|
| 683 | uint32_t HDMI_ACR_PACKET_CONTROL;
|
| 684 | uint32_t HDMI_ACR_32_0;
|
| 685 | uint32_t HDMI_ACR_32_1;
|
| 686 | uint32_t HDMI_ACR_44_0;
|
| 687 | uint32_t HDMI_ACR_44_1;
|
| 688 | uint32_t HDMI_ACR_48_0;
|
| 689 | uint32_t HDMI_ACR_48_1;
|
| 690 | uint32_t TMDS_CNTL;
|
| 691 | uint32_t DP_DB_CNTL;
|
| 692 | uint32_t DP_MSA_MISC;
|
| 693 | uint32_t DP_MSA_COLORIMETRY;
|
| 694 | uint32_t DP_MSA_TIMING_PARAM1;
|
| 695 | uint32_t DP_MSA_TIMING_PARAM2;
|
| 696 | uint32_t DP_MSA_TIMING_PARAM3;
|
| 697 | uint32_t DP_MSA_TIMING_PARAM4;
|
| 698 | uint32_t HDMI_DB_CONTROL;
|
| 699 | };
|
| 700 |
|
| 701 | struct dce110_stream_encoder {
|
| 702 | struct stream_encoder base;
|
| 703 | const struct dce110_stream_enc_registers *regs;
|
| 704 | const struct dce_stream_encoder_shift *se_shift;
|
| 705 | const struct dce_stream_encoder_mask *se_mask;
|
| 706 | };
|
| 707 |
|
| 708 | void dce110_stream_encoder_construct(
|
| 709 | struct dce110_stream_encoder *enc110,
|
| 710 | struct dc_context *ctx,
|
| 711 | struct dc_bios *bp,
|
| 712 | enum engine_id eng_id,
|
| 713 | const struct dce110_stream_enc_registers *regs,
|
| 714 | const struct dce_stream_encoder_shift *se_shift,
|
| 715 | const struct dce_stream_encoder_mask *se_mask);
|
| 716 |
|
| 717 | void dce110_analog_stream_encoder_construct(
|
| 718 | struct dce110_stream_encoder *enc110,
|
| 719 | struct dc_context *ctx,
|
| 720 | struct dc_bios *bp,
|
| 721 | enum engine_id eng_id,
|
| 722 | const struct dce110_stream_enc_registers *regs,
|
| 723 | const struct dce_stream_encoder_shift *se_shift,
|
| 724 | const struct dce_stream_encoder_mask *se_mask);
|
| 725 |
|
| 726 | void dce110_se_audio_mute_control(
|
| 727 | struct stream_encoder *enc, bool mute);
|
| 728 |
|
| 729 | void dce110_se_dp_audio_setup(
|
| 730 | struct stream_encoder *enc,
|
| 731 | unsigned int az_inst,
|
| 732 | struct audio_info *info);
|
| 733 |
|
| 734 | void dce110_se_dp_audio_enable(
|
| 735 | struct stream_encoder *enc);
|
| 736 |
|
| 737 | void dce110_se_dp_audio_disable(
|
| 738 | struct stream_encoder *enc);
|
| 739 |
|
| 740 | void dce110_se_hdmi_audio_setup(
|
| 741 | struct stream_encoder *enc,
|
| 742 | unsigned int az_inst,
|
| 743 | struct audio_info *info,
|
| 744 | struct audio_crtc_info *audio_crtc_info);
|
| 745 |
|
| 746 | void dce110_se_hdmi_audio_disable(
|
| 747 | struct stream_encoder *enc);
|
| 748 |
|
| 749 | #endif
|