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1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26/**
27 * This file defines helper functions provided by the Display Manager to
28 * Display Core.
29 */
30#ifndef __DM_HELPERS__
31#define __DM_HELPERS__
32
33#include "modules/inc/mod_info_packet_types.h"
34#include "dc_types.h"
35#include "dc.h"
36
37struct dc_dp_mst_stream_allocation_table;
38struct aux_payload;
39enum aux_return_code_type;
40enum set_config_status;
41
42/*
43 * Allocate memory accessible by the GPU
44 *
45 * frame buffer allocations must be aligned to a 4096-byte boundary
46 *
47 * Returns virtual address, sets addr to physical address
48 */
49void *dm_helpers_allocate_gpu_mem(
50 struct dc_context *ctx,
51 enum dc_gpu_mem_alloc_type type,
52 size_t size,
53 long long *addr);
54
55/*
56 * Free the GPU-accessible memory at the virtual address pvMem
57 */
58void dm_helpers_free_gpu_mem(
59 struct dc_context *ctx,
60 enum dc_gpu_mem_alloc_type type,
61 void *pvMem);
62
63enum dc_edid_status dm_helpers_parse_edid_caps(
64 struct dc_link *link,
65 const struct dc_edid *edid,
66 struct dc_edid_caps *edid_caps);
67
68
69/*
70 * Update DP branch info
71 */
72void dm_helpers_dp_update_branch_info(
73 struct dc_context *ctx,
74 const struct dc_link *link);
75
76/*
77 * Writes payload allocation table in immediate downstream device.
78 */
79bool dm_helpers_dp_mst_write_payload_allocation_table(
80 struct dc_context *ctx,
81 const struct dc_stream_state *stream,
82 struct dc_dp_mst_stream_allocation_table *proposed_table,
83 bool enable);
84
85/*
86 * poll pending down reply
87 */
88void dm_helpers_dp_mst_poll_pending_down_reply(
89 struct dc_context *ctx,
90 const struct dc_link *link);
91
92/*
93 * Clear payload allocation table before enable MST DP link.
94 */
95void dm_helpers_dp_mst_clear_payload_allocation_table(
96 struct dc_context *ctx,
97 const struct dc_link *link);
98
99/*
100 * Polls for ACT (allocation change trigger) handled and
101 */
102enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
103 struct dc_context *ctx,
104 const struct dc_stream_state *stream);
105/*
106 * Sends ALLOCATE_PAYLOAD message.
107 */
108void dm_helpers_dp_mst_send_payload_allocation(
109 struct dc_context *ctx,
110 const struct dc_stream_state *stream);
111
112/*
113 * Update mst manager relevant variables
114 */
115void dm_helpers_dp_mst_update_mst_mgr_for_deallocation(
116 struct dc_context *ctx,
117 const struct dc_stream_state *stream);
118
119bool dm_helpers_dp_mst_start_top_mgr(
120 struct dc_context *ctx,
121 const struct dc_link *link,
122 bool boot);
123
124bool dm_helpers_dp_mst_stop_top_mgr(
125 struct dc_context *ctx,
126 struct dc_link *link);
127
128void dm_helpers_dp_mst_update_branch_bandwidth(
129 struct dc_context *ctx,
130 struct dc_link *link);
131
132/**
133 * OS specific aux read callback.
134 */
135bool dm_helpers_dp_read_dpcd(
136 struct dc_context *ctx,
137 const struct dc_link *link,
138 uint32_t address,
139 uint8_t *data,
140 uint32_t size);
141
142/**
143 * OS specific aux write callback.
144 */
145bool dm_helpers_dp_write_dpcd(
146 struct dc_context *ctx,
147 const struct dc_link *link,
148 uint32_t address,
149 const uint8_t *data,
150 uint32_t size);
151
152bool dm_helpers_submit_i2c(
153 struct dc_context *ctx,
154 const struct dc_link *link,
155 struct i2c_command *cmd);
156
157bool dm_helpers_execute_fused_io(
158 struct dc_context *ctx,
159 struct dc_link *link,
160 union dmub_rb_cmd *commands,
161 uint8_t count,
162 uint32_t timeout_us
163);
164
165bool dm_helpers_dp_write_dsc_enable(
166 struct dc_context *ctx,
167 const struct dc_stream_state *stream,
168 bool enable
169);
170
171bool dm_helpers_dp_write_hblank_reduction(
172 struct dc_context *ctx,
173 const struct dc_stream_state *stream);
174
175bool dm_helpers_is_dp_sink_present(
176 struct dc_link *link);
177
178void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream);
179
180enum dc_edid_status dm_helpers_read_local_edid(
181 struct dc_context *ctx,
182 struct dc_link *link,
183 struct dc_sink *sink);
184
185void dm_helpers_read_mccs_caps(
186 struct dc_context *ctx,
187 struct dc_link *link,
188 struct dc_sink *sink);
189
190void dm_helpers_mccs_vcp_set(
191 struct dc_context *ctx,
192 struct dc_link *link,
193 struct dc_sink *sink);
194
195#if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST)
196#define STATIC_IFN_KUNIT
197#define INLINE_IFN_KUNIT inline
198#define EXPORT_IF_KUNIT(symbol) EXPORT_SYMBOL(symbol)
199
200#else
201#define STATIC_IFN_KUNIT static
202#define INLINE_IFN_KUNIT
203#define EXPORT_IF_KUNIT(symbol)
204#endif
205
206bool dm_helpers_submit_i2c_over_aux(
207 struct ddc_service *ddc,
208 uint32_t address,
209 uint8_t offset,
210 uint8_t *cmdBuffer,
211 uint32_t len,
212 bool read);
213
214bool dm_helpers_dp_handle_test_pattern_request(
215 struct dc_context *ctx,
216 const struct dc_link *link,
217 union link_test_pattern dpcd_test_pattern,
218 union test_misc dpcd_test_params);
219
220void dm_set_dcn_clocks(
221 struct dc_context *ctx,
222 struct dc_clocks *clks);
223
224void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable);
225
226void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz);
227
228bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable);
229
230void dm_helpers_dmu_timeout(struct dc_context *ctx);
231void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us);
232
233// 0x1 = Result_OK, 0xFE = Result_UnkmownCmd, 0x0 = Status_Busy
234#define IS_SMU_TIMEOUT(result) \
235 (result == 0x0)
236void dm_helpers_init_panel_settings(
237 struct dc_context *ctx,
238 struct dc_panel_config *config,
239 struct dc_sink *sink);
240void dm_helpers_override_panel_settings(
241 struct dc_context *ctx,
242 struct dc_link *link);
243int dm_helper_dmub_aux_transfer_sync(
244 struct dc_context *ctx,
245 const struct dc_link *link,
246 struct aux_payload *payload,
247 enum aux_return_code_type *operation_result);
248
249int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
250 const struct dc_link *link,
251 struct set_config_cmd_payload *payload,
252 enum set_config_status *operation_result);
253enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link);
254
255enum dc_edid_status dm_helpers_get_sbios_edid(struct dc_link *link, struct dc_edid *edid);
256
257bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream);
258bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream);
259
260#endif /* __DM_HELPERS__ */