| 1 | |
| 2 | * Copyright 2012-15 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 | * Authors: AMD
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| 23 | *
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| 24 |
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| 25 |
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| 26 | #ifndef __DAL_DPCD_DEFS_H__
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| 27 | #define __DAL_DPCD_DEFS_H__
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| 28 |
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| 29 | #include <drm/display/drm_dp_helper.h>
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| 30 | #ifndef DP_SINK_HW_REVISION_START
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| 31 | #define DP_SINK_HW_REVISION_START 0x409
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| 32 | #endif
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| 33 |
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| 34 | #ifndef DP_PANEL_REPLAY_CAPABILITY_SUPPORT
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| 35 | #define DP_PANEL_REPLAY_CAPABILITY_SUPPORT 0x0b0
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| 36 | #endif
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| 37 | #ifndef DP_PANEL_REPLAY_CAPABILITY
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| 38 | #define DP_PANEL_REPLAY_CAPABILITY 0x0b1
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| 39 | #endif
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| 40 | #ifndef DP_PR_SU_X_GRANULARITY_LOW
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| 41 | #define DP_PR_SU_X_GRANULARITY_LOW 0x0b2
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| 42 | #endif
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| 43 | #ifndef DP_PR_SU_X_GRANULARITY_HIGH
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| 44 | #define DP_PR_SU_X_GRANULARITY_HIGH 0x0b3
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| 45 | #endif
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| 46 | #ifndef DP_PR_SU_Y_GRANULARITY
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| 47 | #define DP_PR_SU_Y_GRANULARITY 0x0b4
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| 48 | #endif
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| 49 | #ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW
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| 50 | #define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW 0x0b5
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| 51 | #endif
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| 52 | #ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH
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| 53 | #define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH 0x0b6
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| 54 | #endif
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| 55 | #ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1
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| 56 | #define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 0x1b0
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| 57 | #endif
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| 58 | #ifndef DP_PANEL_REPLAY_ENABLE
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| 59 | #define DP_PANEL_REPLAY_ENABLE (1 << 0)
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| 60 | #endif
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| 61 | #ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2
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| 62 | #define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 0x1b1
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| 63 | #endif
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| 64 | #ifndef DP_PR_ERROR_STATUS
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| 65 | #define DP_PR_ERROR_STATUS 0x2020
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| 66 | #endif
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| 67 | #ifndef DP_PR_REPLAY_SINK_STATUS
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| 68 | #define DP_PR_REPLAY_SINK_STATUS 0x2022
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| 69 | #endif
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| 70 | #ifndef DP_PR_LINK_CRC_ERROR
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| 71 | #define DP_PR_LINK_CRC_ERROR (1 << 0)
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| 72 | #endif
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| 73 | #ifndef DP_PR_RFB_STORAGE_ERROR
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| 74 | #define DP_PR_RFB_STORAGE_ERROR (1 << 1)
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| 75 | #endif
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| 76 | #ifndef DP_PR_VSC_SDP_UNCORRECTABLE_ERROR
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| 77 | #define DP_PR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2)
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| 78 | #endif
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| 79 | #ifndef DP_PR_ASSDP_MISSING_ERROR
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| 80 | #define DP_PR_ASSDP_MISSING_ERROR (1 << 3)
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| 81 | #endif
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| 82 |
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| 83 | enum dpcd_revision {
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| 84 | DPCD_REV_10 = 0x10,
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| 85 | DPCD_REV_11 = 0x11,
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| 86 | DPCD_REV_12 = 0x12,
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| 87 | DPCD_REV_13 = 0x13,
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| 88 | DPCD_REV_14 = 0x14
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| 89 | };
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| 90 |
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| 91 |
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| 92 | enum dpcd_downstream_port_type {
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| 93 | DOWNSTREAM_DP = 0,
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| 94 | DOWNSTREAM_VGA,
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| 95 | DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,
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| 96 | DOWNSTREAM_NONDDC
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| 97 | };
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| 98 |
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| 99 | enum dpcd_link_test_patterns {
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| 100 | LINK_TEST_PATTERN_NONE = 0,
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| 101 | LINK_TEST_PATTERN_COLOR_RAMP,
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| 102 | LINK_TEST_PATTERN_VERTICAL_BARS,
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| 103 | LINK_TEST_PATTERN_COLOR_SQUARES
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| 104 | };
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| 105 |
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| 106 | enum dpcd_test_color_format {
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| 107 | TEST_COLOR_FORMAT_RGB = 0,
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| 108 | TEST_COLOR_FORMAT_YCBCR422,
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| 109 | TEST_COLOR_FORMAT_YCBCR444
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| 110 | };
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| 111 |
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| 112 | enum dpcd_test_bit_depth {
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| 113 | TEST_BIT_DEPTH_6 = 0,
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| 114 | TEST_BIT_DEPTH_8,
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| 115 | TEST_BIT_DEPTH_10,
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| 116 | TEST_BIT_DEPTH_12,
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| 117 | TEST_BIT_DEPTH_16
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| 118 | };
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| 119 |
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| 120 | |
| 121 | The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
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| 122 |
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| 123 | enum dpcd_phy_test_patterns {
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| 124 | PHY_TEST_PATTERN_NONE = 0,
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| 125 | PHY_TEST_PATTERN_D10_2,
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| 126 | PHY_TEST_PATTERN_SYMBOL_ERROR,
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| 127 | PHY_TEST_PATTERN_PRBS7,
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| 128 | PHY_TEST_PATTERN_80BIT_CUSTOM,
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| 129 | PHY_TEST_PATTERN_CP2520_1,
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| 130 | PHY_TEST_PATTERN_CP2520_2,
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| 131 | PHY_TEST_PATTERN_CP2520_3,
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| 132 | PHY_TEST_PATTERN_128b_132b_TPS1 = 0x8,
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| 133 | PHY_TEST_PATTERN_128b_132b_TPS2 = 0x10,
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| 134 | PHY_TEST_PATTERN_PRBS9 = 0x18,
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| 135 | PHY_TEST_PATTERN_PRBS11 = 0x20,
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| 136 | PHY_TEST_PATTERN_PRBS15 = 0x28,
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| 137 | PHY_TEST_PATTERN_PRBS23 = 0x30,
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| 138 | PHY_TEST_PATTERN_PRBS31 = 0x38,
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| 139 | PHY_TEST_PATTERN_264BIT_CUSTOM = 0x40,
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| 140 | PHY_TEST_PATTERN_SQUARE = 0x48,
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| 141 | PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED = 0x49,
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| 142 | PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED = 0x4A,
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| 143 | PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED = 0x4B,
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| 144 | };
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| 145 |
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| 146 | enum dpcd_test_dyn_range {
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| 147 | TEST_DYN_RANGE_VESA = 0,
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| 148 | TEST_DYN_RANGE_CEA
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| 149 | };
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| 150 |
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| 151 | enum dpcd_audio_test_pattern {
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| 152 | AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,
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| 153 | AUDIO_TEST_PATTERN_SAWTOOTH
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| 154 | };
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| 155 |
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| 156 | enum dpcd_audio_sampling_rate {
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| 157 | AUDIO_SAMPLING_RATE_32KHZ = 0,
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| 158 | AUDIO_SAMPLING_RATE_44_1KHZ,
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| 159 | AUDIO_SAMPLING_RATE_48KHZ,
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| 160 | AUDIO_SAMPLING_RATE_88_2KHZ,
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| 161 | AUDIO_SAMPLING_RATE_96KHZ,
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| 162 | AUDIO_SAMPLING_RATE_176_4KHZ,
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| 163 | AUDIO_SAMPLING_RATE_192KHZ
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| 164 | };
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| 165 |
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| 166 | enum dpcd_audio_channels {
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| 167 | AUDIO_CHANNELS_1 = 0,
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| 168 | AUDIO_CHANNELS_2,
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| 169 | AUDIO_CHANNELS_3,
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| 170 | AUDIO_CHANNELS_4,
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| 171 | AUDIO_CHANNELS_5,
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| 172 | AUDIO_CHANNELS_6,
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| 173 | AUDIO_CHANNELS_7,
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| 174 | AUDIO_CHANNELS_8,
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| 175 |
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| 176 | AUDIO_CHANNELS_COUNT
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| 177 | };
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| 178 |
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| 179 | enum dpcd_audio_test_pattern_periods {
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| 180 | DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,
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| 181 | DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
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| 182 | DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
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| 183 | DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
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| 184 | DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
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| 185 | DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
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| 186 | DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
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| 187 | DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
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| 188 | DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
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| 189 | DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
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| 190 | DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
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| 191 | };
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| 192 |
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| 193 |
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| 194 | enum dpcd_training_patterns {
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| 195 | DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,
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| 196 | DPCD_TRAINING_PATTERN_1,
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| 197 | DPCD_TRAINING_PATTERN_2,
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| 198 | DPCD_TRAINING_PATTERN_3,
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| 199 | DPCD_TRAINING_PATTERN_4 = 7,
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| 200 | DPCD_128b_132b_TPS1 = 1,
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| 201 | DPCD_128b_132b_TPS2 = 2,
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| 202 | DPCD_128b_132b_TPS2_CDS = 3,
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| 203 | };
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| 204 |
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| 205 | |
| 206 | It defines the possible PSR states.
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| 207 | enum dpcd_psr_sink_states {
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| 208 | PSR_SINK_STATE_INACTIVE = 0,
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| 209 | PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
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| 210 | PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
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| 211 | PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
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| 212 | PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
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| 213 | PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
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| 214 | };
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| 215 |
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| 216 | #define DP_SOURCE_SEQUENCE 0x30C
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| 217 | #define DP_SOURCE_TABLE_REVISION 0x310
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| 218 | #define DP_SOURCE_PAYLOAD_SIZE 0x311
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| 219 | #define DP_SOURCE_SINK_CAP 0x317
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| 220 | #define DP_SOURCE_BACKLIGHT_LEVEL 0x320
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| 221 | #define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326
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| 222 | #define DP_SOURCE_BACKLIGHT_CONTROL 0x32E
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| 223 | #define DP_SOURCE_BACKLIGHT_ENABLE 0x32F
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| 224 | #define DP_SINK_DRR_GRANULARITY 0x33B
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| 225 | #define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED 0x340
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| 226 | #define DP_SINK_PR_REPLAY_STATUS 0x378
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| 227 | #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE 0x379
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| 228 | #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A
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| 229 | #define DP_SINK_EMISSION_RATE 0x37E
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| 230 | #define DP_SINK_PR_FRAME_SKIP_COUNT 0x337
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| 231 |
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| 232 |
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| 233 | #ifndef DP_TOTAL_LTTPR_CNT
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| 234 | #define DP_TOTAL_LTTPR_CNT 0xF000A
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| 235 | #endif
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| 236 |
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| 237 | #endif
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