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1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__
27#define __DAL_GRPH_OBJECT_CTRL_DEFS_H__
28
29#include "grph_object_defs.h"
30
31/*
32 * #####################################################
33 * #####################################################
34 *
35 * These defines shared between asic_control/bios_parser and other
36 * DAL components
37 *
38 * #####################################################
39 * #####################################################
40 */
41
42enum display_output_bit_depth {
43 PANEL_UNDEFINE = 0,
44 PANEL_6BIT_COLOR = 1,
45 PANEL_8BIT_COLOR = 2,
46 PANEL_10BIT_COLOR = 3,
47 PANEL_12BIT_COLOR = 4,
48 PANEL_16BIT_COLOR = 5,
49};
50
51
52/* Device type as abstracted by ATOM BIOS */
53enum dal_device_type {
54 DEVICE_TYPE_UNKNOWN = 0,
55 DEVICE_TYPE_LCD,
56 DEVICE_TYPE_CRT,
57 DEVICE_TYPE_DFP,
58 DEVICE_TYPE_CV,
59 DEVICE_TYPE_TV,
60 DEVICE_TYPE_CF,
61 DEVICE_TYPE_WIRELESS
62};
63
64/* Device ID as abstracted by ATOM BIOS */
65struct device_id {
66 enum dal_device_type device_type:16;
67 uint32_t enum_id:16; /* 1 based enum */
68 uint16_t raw_device_tag;
69};
70
71struct graphics_object_i2c_info {
72 struct gpio_info {
73 uint32_t clk_mask_register_index;
74 uint32_t clk_en_register_index;
75 uint32_t clk_y_register_index;
76 uint32_t clk_a_register_index;
77 uint32_t data_mask_register_index;
78 uint32_t data_en_register_index;
79 uint32_t data_y_register_index;
80 uint32_t data_a_register_index;
81
82 uint32_t clk_mask_shift;
83 uint32_t clk_en_shift;
84 uint32_t clk_y_shift;
85 uint32_t clk_a_shift;
86 uint32_t data_mask_shift;
87 uint32_t data_en_shift;
88 uint32_t data_y_shift;
89 uint32_t data_a_shift;
90 } gpio_info;
91
92 bool i2c_hw_assist;
93 uint32_t i2c_line;
94 uint32_t i2c_engine_id;
95 uint32_t i2c_slave_address;
96};
97
98struct graphics_object_hpd_info {
99 uint8_t hpd_int_gpio_uid;
100 uint8_t hpd_active;
101};
102
103struct connector_device_tag_info {
104 uint32_t acpi_device;
105 struct device_id dev_id;
106};
107
108struct device_timing {
109 struct misc_info {
110 uint32_t HORIZONTAL_CUT_OFF:1;
111 /* 0=Active High, 1=Active Low */
112 uint32_t H_SYNC_POLARITY:1;
113 /* 0=Active High, 1=Active Low */
114 uint32_t V_SYNC_POLARITY:1;
115 uint32_t VERTICAL_CUT_OFF:1;
116 uint32_t H_REPLICATION_BY2:1;
117 uint32_t V_REPLICATION_BY2:1;
118 uint32_t COMPOSITE_SYNC:1;
119 uint32_t INTERLACE:1;
120 uint32_t DOUBLE_CLOCK:1;
121 uint32_t RGB888:1;
122 uint32_t GREY_LEVEL:2;
123 uint32_t SPATIAL:1;
124 uint32_t TEMPORAL:1;
125 uint32_t API_ENABLED:1;
126 } misc_info;
127
128 uint32_t pixel_clk; /* in KHz */
129 uint32_t horizontal_addressable;
130 uint32_t horizontal_blanking_time;
131 uint32_t vertical_addressable;
132 uint32_t vertical_blanking_time;
133 uint32_t horizontal_sync_offset;
134 uint32_t horizontal_sync_width;
135 uint32_t vertical_sync_offset;
136 uint32_t vertical_sync_width;
137 uint32_t horizontal_border;
138 uint32_t vertical_border;
139};
140
141struct supported_refresh_rate {
142 uint32_t REFRESH_RATE_30HZ:1;
143 uint32_t REFRESH_RATE_40HZ:1;
144 uint32_t REFRESH_RATE_48HZ:1;
145 uint32_t REFRESH_RATE_50HZ:1;
146 uint32_t REFRESH_RATE_60HZ:1;
147};
148
149struct embedded_panel_info {
150 struct device_timing lcd_timing;
151 uint32_t ss_id;
152 struct supported_refresh_rate supported_rr;
153 uint32_t drr_enabled;
154 uint32_t min_drr_refresh_rate;
155 bool realtek_eDPToLVDS;
156 uint16_t panel_width_mm;
157 uint16_t panel_height_mm;
158 uint16_t fake_edid_size;
159 const uint8_t *fake_edid;
160};
161
162struct dc_firmware_info {
163 struct pll_info {
164 uint32_t crystal_frequency; /* in KHz */
165 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
166 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
167 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
168 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
169 } pll_info;
170
171 struct firmware_feature {
172 uint32_t memory_clk_ss_percentage;
173 uint32_t engine_clk_ss_percentage;
174 } feature;
175
176 uint32_t max_pixel_clock; /* in KHz */
177 uint32_t default_display_engine_pll_frequency; /* in KHz */
178 uint32_t external_clock_source_frequency_for_dp; /* in KHz */
179 uint32_t smu_gpu_pll_output_freq; /* in KHz */
180 uint8_t min_allowed_bl_level;
181 uint8_t remote_display_config;
182 uint32_t default_memory_clk; /* in KHz */
183 uint32_t default_engine_clk; /* in KHz */
184 uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */
185 uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */
186 bool oem_i2c_present;
187 uint8_t oem_i2c_obj_id;
188
189};
190
191struct dc_vram_info {
192 unsigned int num_chans;
193 unsigned int dram_channel_width_bytes;
194};
195
196struct step_and_delay_info {
197 uint32_t step;
198 uint32_t delay;
199 uint32_t recommended_ref_div;
200};
201
202struct spread_spectrum_info {
203 struct spread_spectrum_type {
204 bool CENTER_MODE:1;
205 bool EXTERNAL:1;
206 bool STEP_AND_DELAY_INFO:1;
207 } type;
208
209 /* in unit of 0.01% (spreadPercentageDivider = 100),
210 otherwise in 0.001% units (spreadPercentageDivider = 1000); */
211 uint32_t spread_spectrum_percentage;
212 uint32_t spread_percentage_divider; /* 100 or 1000 */
213 uint32_t spread_spectrum_range; /* modulation freq (HZ)*/
214
215 union {
216 struct step_and_delay_info step_and_delay_info;
217 /* For mem/engine/uvd, Clock Out frequence (VCO ),
218 in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock,
219 for DP, it is link clock ( 270000 or 162000 ) */
220 uint32_t target_clock_range; /* in KHz */
221 };
222
223};
224
225struct graphics_object_encoder_cap_info {
226 uint32_t dp_hbr2_cap:1;
227 uint32_t dp_hbr2_validated:1;
228 /*
229 * TODO: added MST and HDMI 6G capable flags
230 */
231 uint32_t reserved:15;
232};
233
234struct din_connector_info {
235 uint32_t gpio_id;
236 bool gpio_tv_active_state;
237};
238
239/* Invalid channel mapping */
240enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 };
241
242/**
243 * DDI PHY channel mapping reflecting XBAR setting
244 */
245union ddi_channel_mapping {
246 struct mapping {
247 uint8_t lane0:2; /* Mapping for lane 0 */
248 uint8_t lane1:2; /* Mapping for lane 1 */
249 uint8_t lane2:2; /* Mapping for lane 2 */
250 uint8_t lane3:2; /* Mapping for lane 3 */
251 } mapping;
252 uint8_t raw;
253};
254
255/**
256* Transmitter output configuration description
257*/
258struct transmitter_configuration_info {
259 /* DDI PHY ID for the transmitter */
260 enum transmitter transmitter_phy_id;
261 /* DDI PHY channel mapping reflecting crossbar setting */
262 union ddi_channel_mapping output_channel_mapping;
263};
264
265struct transmitter_configuration {
266 /* Configuration for the primary transmitter */
267 struct transmitter_configuration_info primary_transmitter_config;
268 /* Secondary transmitter configuration for Dual-link DVI */
269 struct transmitter_configuration_info secondary_transmitter_config;
270};
271
272/* These size should be sufficient to store info coming from BIOS */
273#define NUMBER_OF_UCHAR_FOR_GUID 16
274#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
275#define NUMBER_OF_CSR_M3_ARB 10
276#define NUMBER_OF_AVAILABLE_SCLK 5
277
278struct i2c_reg_info {
279 unsigned char i2c_reg_index;
280 unsigned char i2c_reg_val;
281};
282
283struct ext_hdmi_settings {
284 unsigned char slv_addr;
285 unsigned char reg_num;
286 struct i2c_reg_info reg_settings[9];
287 unsigned char reg_num_6g;
288 struct i2c_reg_info reg_settings_6g[3];
289};
290
291struct edp_info {
292 uint16_t edp_backlight_pwm_hz;
293 uint16_t edp_ss_percentage;
294 uint16_t edp_ss_rate_10hz;
295 uint8_t edp_pwr_on_off_delay;
296 uint8_t edp_pwr_on_vary_bl_to_blon;
297 uint8_t edp_pwr_down_bloff_to_vary_bloff;
298 uint8_t edp_panel_bpc;
299 uint8_t edp_bootup_bl_level;
300};
301
302/* V6 */
303struct integrated_info {
304 struct display_connection_info {
305 struct external_display_path {
306 /* A bit vector to show what devices are supported */
307 uint32_t device_tag;
308 /* 16bit device ACPI id. */
309 uint32_t device_acpi_enum;
310 /* A physical connector for displays to plug in,
311 using object connector definitions */
312 struct graphics_object_id device_connector_id;
313 /* An index into external AUX/DDC channel LUT */
314 uint8_t ext_aux_ddc_lut_index;
315 /* An index into external HPD pin LUT */
316 uint8_t ext_hpd_pin_lut_index;
317 /* external encoder object id */
318 struct graphics_object_id ext_encoder_obj_id;
319 /* XBAR mapping of the PHY channels */
320 union ddi_channel_mapping channel_mapping;
321
322 unsigned short caps;
323 } path[MAX_NUMBER_OF_EXT_DISPLAY_PATH];
324
325 uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];
326 uint8_t checksum;
327 uint8_t fixdpvoltageswing;
328 } ext_disp_conn_info; /* exiting long long time */
329
330 struct available_s_clk_list {
331 /* Maximum clock supported with specified voltage index */
332 uint32_t supported_s_clk; /* in KHz */
333 /* The Voltage Index indicated by FUSE for specified SCLK */
334 uint32_t voltage_index;
335 /* The Voltage ID indicated by FUSE for specified SCLK */
336 uint32_t voltage_id;
337 } avail_s_clk[NUMBER_OF_AVAILABLE_SCLK];
338
339 uint8_t memory_type;
340 uint8_t ma_channel_number;
341 uint32_t boot_up_engine_clock; /* in KHz */
342 uint32_t dentist_vco_freq; /* in KHz */
343 uint32_t boot_up_uma_clock; /* in KHz */
344 uint32_t boot_up_req_display_vector;
345 uint32_t other_display_misc;
346 uint32_t gpu_cap_info;
347 uint32_t sb_mmio_base_addr;
348 uint32_t system_config;
349 uint32_t cpu_cap_info;
350 uint32_t max_nb_voltage;
351 uint32_t min_nb_voltage;
352 uint32_t boot_up_nb_voltage;
353 uint32_t ext_disp_conn_info_offset;
354 uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB];
355 uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB];
356 uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB];
357 uint32_t gmc_restore_reset_time;
358 uint32_t minimum_n_clk;
359 uint32_t idle_n_clk;
360 uint32_t ddr_dll_power_up_time;
361 uint32_t ddr_pll_power_up_time;
362 /* start for V6 */
363 uint32_t pcie_clk_ss_type;
364 uint32_t lvds_ss_percentage;
365 uint32_t lvds_sspread_rate_in_10hz;
366 uint32_t hdmi_ss_percentage;
367 uint32_t hdmi_sspread_rate_in_10hz;
368 uint32_t dvi_ss_percentage;
369 uint32_t dvi_sspread_rate_in_10_hz;
370 uint32_t sclk_dpm_boost_margin;
371 uint32_t sclk_dpm_throttle_margin;
372 uint32_t sclk_dpm_tdp_limit_pg;
373 uint32_t sclk_dpm_tdp_limit_boost;
374 uint32_t boost_engine_clock;
375 uint32_t boost_vid_2bit;
376 uint32_t enable_boost;
377 uint32_t gnb_tdp_limit;
378 /* Start from V7 */
379 uint32_t max_lvds_pclk_freq_in_single_link;
380 uint32_t lvds_misc;
381 uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms;
382 uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms;
383 uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms;
384 uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms;
385 uint32_t lvds_off_to_on_delay_in_4ms;
386 uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms;
387 uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms;
388 uint32_t lvds_reserved1;
389 uint32_t lvds_bit_depth_control_val;
390 //Start from V9
391 unsigned char dp0_ext_hdmi_slv_addr;
392 unsigned char dp0_ext_hdmi_reg_num;
393 struct i2c_reg_info dp0_ext_hdmi_reg_settings[9];
394 unsigned char dp0_ext_hdmi_6g_reg_num;
395 struct i2c_reg_info dp0_ext_hdmi_6g_reg_settings[3];
396 unsigned char dp1_ext_hdmi_slv_addr;
397 unsigned char dp1_ext_hdmi_reg_num;
398 struct i2c_reg_info dp1_ext_hdmi_reg_settings[9];
399 unsigned char dp1_ext_hdmi_6g_reg_num;
400 struct i2c_reg_info dp1_ext_hdmi_6g_reg_settings[3];
401 unsigned char dp2_ext_hdmi_slv_addr;
402 unsigned char dp2_ext_hdmi_reg_num;
403 struct i2c_reg_info dp2_ext_hdmi_reg_settings[9];
404 unsigned char dp2_ext_hdmi_6g_reg_num;
405 struct i2c_reg_info dp2_ext_hdmi_6g_reg_settings[3];
406 unsigned char dp3_ext_hdmi_slv_addr;
407 unsigned char dp3_ext_hdmi_reg_num;
408 struct i2c_reg_info dp3_ext_hdmi_reg_settings[9];
409 unsigned char dp3_ext_hdmi_6g_reg_num;
410 struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3];
411 /* V11 */
412 uint32_t dp_ss_control;
413 /* V2.1 */
414 struct edp_info edp1_info;
415 struct edp_info edp2_info;
416 uint32_t gpuclk_ss_percentage;
417 uint32_t gpuclk_ss_type;
418};
419
420/*
421 * DFS-bypass flag
422 */
423/* Copy of SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS from atombios.h */
424enum {
425 DFS_BYPASS_ENABLE = 0x10
426};
427
428enum {
429 INVALID_BACKLIGHT = -1
430};
431
432struct panel_backlight_boundaries {
433 uint32_t min_signal_level;
434 uint32_t max_signal_level;
435};
436
437
438#endif