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1/*
2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "dc.h"
28#include "mod_freesync.h"
29#include "core_types.h"
30
31#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32
32
33#define MIN_REFRESH_RANGE 10
34/* Refresh rate ramp at a fixed rate of 65 Hz/second */
35#define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
36/* Number of elements in the render times cache array */
37#define RENDER_TIMES_MAX_COUNT 10
38/* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
39#define BTR_MAX_MARGIN 2500
40/* Threshold to change BTR multiplier (to avoid frequent changes) */
41#define BTR_DRIFT_MARGIN 2000
42/* Threshold to exit fixed refresh rate */
43#define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 1
44/* Number of consecutive frames to check before entering/exiting fixed refresh */
45#define FIXED_REFRESH_ENTER_FRAME_COUNT 5
46#define FIXED_REFRESH_EXIT_FRAME_COUNT 10
47/* Flip interval workaround constants */
48#define VSYNCS_BETWEEN_FLIP_THRESHOLD 2
49#define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5
50#define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500
51#define MICRO_HZ_TO_HZ(x) (x / 1000000)
52
53struct core_freesync {
54 struct mod_freesync public;
55 struct dc *dc;
56};
57
58#define MOD_FREESYNC_TO_CORE(mod_freesync)\
59 container_of(mod_freesync, struct core_freesync, public)
60
61struct mod_freesync *mod_freesync_create(struct dc *dc)
62{
63 struct core_freesync *core_freesync =
64 kzalloc_obj(struct core_freesync);
65
66 if (core_freesync == NULL)
67 goto fail_alloc_context;
68
69 if (dc == NULL)
70 goto fail_construct;
71
72 core_freesync->dc = dc;
73 return &core_freesync->public;
74
75fail_construct:
76 kfree(core_freesync);
77
78fail_alloc_context:
79 return NULL;
80}
81
82void mod_freesync_destroy(struct mod_freesync *mod_freesync)
83{
84 struct core_freesync *core_freesync = NULL;
85
86 if (mod_freesync == NULL)
87 return;
88 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
89 kfree(core_freesync);
90}
91
92#if 0 /* Unused currently */
93static unsigned int calc_refresh_in_uhz_from_duration(
94 unsigned int duration_in_ns)
95{
96 unsigned int refresh_in_uhz =
97 ((unsigned int)(div64_u64((1000000000ULL * 1000000),
98 duration_in_ns)));
99 return refresh_in_uhz;
100}
101#endif
102
103static unsigned int calc_duration_in_us_from_refresh_in_uhz(
104 unsigned int refresh_in_uhz)
105{
106 unsigned int duration_in_us =
107 ((unsigned int)(div64_u64((1000000000ULL * 1000),
108 refresh_in_uhz)));
109 return duration_in_us;
110}
111
112static unsigned int calc_duration_in_us_from_v_total(
113 const struct dc_stream_state *stream,
114 const struct mod_vrr_params *in_vrr,
115 unsigned int v_total)
116{
117 (void)in_vrr;
118 unsigned int duration_in_us =
119 (unsigned int)(div64_u64(((unsigned long long)(v_total)
120 * 10000) * stream->timing.h_total,
121 stream->timing.pix_clk_100hz));
122
123 return duration_in_us;
124}
125
126static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)
127{
128 unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;
129
130 if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {
131 max_hw_v_total -= stream->timing.v_front_porch + 1;
132 }
133
134 return max_hw_v_total;
135}
136
137unsigned int mod_freesync_calc_v_total_from_refresh(
138 const struct dc_stream_state *stream,
139 unsigned int refresh_in_uhz)
140{
141 unsigned int v_total;
142 unsigned int frame_duration_in_ns;
143
144 if (refresh_in_uhz == 0)
145 return stream->timing.v_total;
146
147 frame_duration_in_ns =
148 ((unsigned int)(div64_u64((1000000000ULL * 1000000),
149 refresh_in_uhz)));
150
151 if (refresh_in_uhz <= stream->timing.min_refresh_in_uhz) {
152 /* When the target refresh rate is the minimum panel refresh rate,
153 * round down the vtotal value to avoid stretching vblank over
154 * panel's vtotal boundary.
155 */
156 v_total = (unsigned int)div64_u64(div64_u64(((unsigned long long)(
157 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
158 stream->timing.h_total), 1000000);
159 } else if (refresh_in_uhz >= stream->timing.max_refresh_in_uhz) {
160 /* When the target refresh rate is the maximum panel refresh rate
161 * round up the vtotal value to prevent off-by-one error causing
162 * v_total_min to be below the panel's lower bound
163 */
164 v_total = (unsigned int)div64_u64(div64_u64(((unsigned long long)(
165 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
166 stream->timing.h_total) + (1000000 - 1), 1000000);
167 } else {
168 v_total = (unsigned int)div64_u64(div64_u64(((unsigned long long)(
169 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
170 stream->timing.h_total) + 500000, 1000000);
171 }
172
173 /* v_total cannot be less than nominal */
174 if (v_total < stream->timing.v_total) {
175 ASSERT(v_total < stream->timing.v_total);
176 v_total = stream->timing.v_total;
177 }
178
179 return v_total;
180}
181
182static unsigned int calc_v_total_from_duration(
183 const struct dc_stream_state *stream,
184 const struct mod_vrr_params *vrr,
185 unsigned int duration_in_us)
186{
187 unsigned int v_total = 0;
188
189 if (duration_in_us < vrr->min_duration_in_us)
190 duration_in_us = vrr->min_duration_in_us;
191
192 if (duration_in_us > vrr->max_duration_in_us)
193 duration_in_us = vrr->max_duration_in_us;
194
195 if (dc_is_hdmi_signal(stream->signal)) { // change for HDMI to comply with spec
196 uint32_t h_total_up_scaled;
197
198 h_total_up_scaled = stream->timing.h_total * 10000;
199 v_total = (unsigned int)div_u64((unsigned long long)duration_in_us
200 * stream->timing.pix_clk_100hz + (h_total_up_scaled - 1),
201 h_total_up_scaled); //ceiling for MMax and MMin for MVRR
202 } else {
203 v_total = (unsigned int)div64_u64(div64_u64(((unsigned long long)(
204 duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
205 stream->timing.h_total), 1000);
206 }
207
208 /* v_total cannot be less than nominal */
209 if (v_total < stream->timing.v_total) {
210 ASSERT(v_total < stream->timing.v_total);
211 v_total = stream->timing.v_total;
212 }
213
214 return v_total;
215}
216
217static void update_v_total_for_static_ramp(
218 struct core_freesync *core_freesync,
219 const struct dc_stream_state *stream,
220 struct mod_vrr_params *in_out_vrr)
221{
222 (void)core_freesync;
223 unsigned int v_total = 0;
224 unsigned int current_duration_in_us =
225 calc_duration_in_us_from_v_total(
226 stream, in_out_vrr,
227 in_out_vrr->adjust.v_total_max);
228 unsigned int target_duration_in_us =
229 calc_duration_in_us_from_refresh_in_uhz(
230 in_out_vrr->fixed.target_refresh_in_uhz);
231 bool ramp_direction_is_up = current_duration_in_us >
232 target_duration_in_us;
233
234 /* Calculate ratio between new and current frame duration with 3 digit */
235 uint64_t frame_duration_ratio_u64 = div64_u64(1000000,
236 (1000 + div64_u64(((unsigned long long)(
237 STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
238 current_duration_in_us),
239 1000000)));
240 ASSERT(frame_duration_ratio_u64 <= 0xFFFFFFFF);
241 unsigned int frame_duration_ratio = (unsigned int)frame_duration_ratio_u64;
242
243 /* Calculate delta between new and current frame duration in us */
244 uint64_t frame_duration_delta_u64 = div64_u64(((unsigned long long)(
245 current_duration_in_us) *
246 (1000 - frame_duration_ratio)), 1000);
247 ASSERT(frame_duration_delta_u64 <= 0xFFFFFFFF);
248 unsigned int frame_duration_delta = (unsigned int)frame_duration_delta_u64;
249
250 /* Adjust frame duration delta based on ratio between current and
251 * standard frame duration (frame duration at 60 Hz refresh rate).
252 */
253 uint64_t ramp_rate_interpolated_u64 = div64_u64(((unsigned long long)(
254 frame_duration_delta) * current_duration_in_us), 16666);
255 ASSERT(ramp_rate_interpolated_u64 <= 0xFFFFFFFF);
256 unsigned int ramp_rate_interpolated = (unsigned int)ramp_rate_interpolated_u64;
257
258 /* Going to a higher refresh rate (lower frame duration) */
259 if (ramp_direction_is_up) {
260 /* Reduce frame duration */
261 current_duration_in_us -= ramp_rate_interpolated;
262
263 /* Adjust for frame duration below min */
264 if (current_duration_in_us <= target_duration_in_us) {
265 in_out_vrr->fixed.ramping_active = false;
266 in_out_vrr->fixed.ramping_done = true;
267 current_duration_in_us =
268 calc_duration_in_us_from_refresh_in_uhz(
269 in_out_vrr->fixed.target_refresh_in_uhz);
270 }
271 /* Going to a lower refresh rate (larger frame duration) */
272 } else {
273 /* Increase frame duration */
274 current_duration_in_us += ramp_rate_interpolated;
275
276 /* Adjust for frame duration above max */
277 if (current_duration_in_us >= target_duration_in_us) {
278 in_out_vrr->fixed.ramping_active = false;
279 in_out_vrr->fixed.ramping_done = true;
280 current_duration_in_us =
281 calc_duration_in_us_from_refresh_in_uhz(
282 in_out_vrr->fixed.target_refresh_in_uhz);
283 }
284 }
285
286 v_total = (unsigned int)div64_u64(div64_u64(((unsigned long long)(
287 current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
288 stream->timing.h_total), 1000);
289
290 /* v_total cannot be less than nominal */
291 if (v_total < stream->timing.v_total)
292 v_total = stream->timing.v_total;
293
294 in_out_vrr->adjust.v_total_min = v_total;
295 in_out_vrr->adjust.v_total_max = v_total;
296}
297
298static void apply_below_the_range(struct core_freesync *core_freesync,
299 const struct dc_stream_state *stream,
300 unsigned int last_render_time_in_us,
301 struct mod_vrr_params *in_out_vrr)
302{
303 (void)core_freesync;
304 unsigned int inserted_frame_duration_in_us = 0;
305 unsigned int mid_point_frames_ceil = 0;
306 unsigned int mid_point_frames_floor = 0;
307 unsigned int frame_time_in_us = 0;
308 unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
309 unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
310 unsigned int frames_to_insert = 0;
311 unsigned int delta_from_mid_point_delta_in_us;
312 unsigned int max_render_time_in_us =
313 in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;
314
315 /* Program BTR */
316 if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {
317 /* Exit Below the Range */
318 if (in_out_vrr->btr.btr_active) {
319 in_out_vrr->btr.frame_counter = 0;
320 in_out_vrr->btr.btr_active = false;
321 }
322 } else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {
323 /* Enter Below the Range */
324 if (!in_out_vrr->btr.btr_active)
325 in_out_vrr->btr.btr_active = true;
326 }
327
328 /* BTR set to "not active" so disengage */
329 if (!in_out_vrr->btr.btr_active) {
330 in_out_vrr->btr.inserted_duration_in_us = 0;
331 in_out_vrr->btr.frames_to_insert = 0;
332 in_out_vrr->btr.frame_counter = 0;
333
334 /* Restore FreeSync */
335 in_out_vrr->adjust.v_total_min =
336 mod_freesync_calc_v_total_from_refresh(stream,
337 in_out_vrr->max_refresh_in_uhz);
338 in_out_vrr->adjust.v_total_max =
339 mod_freesync_calc_v_total_from_refresh(stream,
340 in_out_vrr->min_refresh_in_uhz);
341 /* BTR set to "active" so engage */
342 } else {
343
344 /* Calculate number of midPoint frames that could fit within
345 * the render time interval - take ceil of this value
346 */
347 mid_point_frames_ceil = (last_render_time_in_us +
348 in_out_vrr->btr.mid_point_in_us - 1) /
349 in_out_vrr->btr.mid_point_in_us;
350
351 if (mid_point_frames_ceil > 0) {
352 frame_time_in_us = last_render_time_in_us /
353 mid_point_frames_ceil;
354 delta_from_mid_point_in_us_1 =
355 (in_out_vrr->btr.mid_point_in_us >
356 frame_time_in_us) ?
357 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
358 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
359 }
360
361 /* Calculate number of midPoint frames that could fit within
362 * the render time interval - take floor of this value
363 */
364 mid_point_frames_floor = last_render_time_in_us /
365 in_out_vrr->btr.mid_point_in_us;
366
367 if (mid_point_frames_floor > 0) {
368
369 frame_time_in_us = last_render_time_in_us /
370 mid_point_frames_floor;
371 delta_from_mid_point_in_us_2 =
372 (in_out_vrr->btr.mid_point_in_us >
373 frame_time_in_us) ?
374 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
375 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
376 }
377
378 /* Choose number of frames to insert based on how close it
379 * can get to the mid point of the variable range.
380 * - Delta for CEIL: delta_from_mid_point_in_us_1
381 * - Delta for FLOOR: delta_from_mid_point_in_us_2
382 */
383 if (mid_point_frames_ceil &&
384 (last_render_time_in_us / mid_point_frames_ceil) <
385 in_out_vrr->min_duration_in_us) {
386 /* Check for out of range.
387 * If using CEIL produces a value that is out of range,
388 * then we are forced to use FLOOR.
389 */
390 frames_to_insert = mid_point_frames_floor;
391 } else if (mid_point_frames_floor < 2) {
392 /* Check if FLOOR would result in non-LFC. In this case
393 * choose to use CEIL
394 */
395 frames_to_insert = mid_point_frames_ceil;
396 } else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
397 /* If choosing CEIL results in a frame duration that is
398 * closer to the mid point of the range.
399 * Choose CEIL
400 */
401 frames_to_insert = mid_point_frames_ceil;
402 } else {
403 /* If choosing FLOOR results in a frame duration that is
404 * closer to the mid point of the range.
405 * Choose FLOOR
406 */
407 frames_to_insert = mid_point_frames_floor;
408 }
409
410 /* Prefer current frame multiplier when BTR is enabled unless it drifts
411 * too far from the midpoint
412 */
413 if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
414 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
415 delta_from_mid_point_in_us_1;
416 } else {
417 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
418 delta_from_mid_point_in_us_2;
419 }
420 if (in_out_vrr->btr.frames_to_insert != 0 &&
421 delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
422 if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
423 max_render_time_in_us) &&
424 ((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >
425 in_out_vrr->min_duration_in_us))
426 frames_to_insert = in_out_vrr->btr.frames_to_insert;
427 }
428
429 /* Either we've calculated the number of frames to insert,
430 * or we need to insert min duration frames
431 */
432 if (frames_to_insert &&
433 (last_render_time_in_us / frames_to_insert) <
434 in_out_vrr->min_duration_in_us){
435 frames_to_insert -= (frames_to_insert > 1) ?
436 1 : 0;
437 }
438
439 if (frames_to_insert > 0)
440 inserted_frame_duration_in_us = last_render_time_in_us /
441 frames_to_insert;
442
443 if (inserted_frame_duration_in_us < in_out_vrr->min_duration_in_us)
444 inserted_frame_duration_in_us = in_out_vrr->min_duration_in_us;
445
446 /* Cache the calculated variables */
447 in_out_vrr->btr.inserted_duration_in_us =
448 inserted_frame_duration_in_us;
449 in_out_vrr->btr.frames_to_insert = frames_to_insert;
450 in_out_vrr->btr.frame_counter = frames_to_insert;
451 }
452}
453
454static void apply_fixed_refresh(struct core_freesync *core_freesync,
455 const struct dc_stream_state *stream,
456 unsigned int last_render_time_in_us,
457 struct mod_vrr_params *in_out_vrr)
458{
459 (void)core_freesync;
460 bool update = false;
461 unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
462
463 /* Compute the exit refresh rate and exit frame duration */
464 unsigned int exit_refresh_rate_in_milli_hz = ((1000000000/max_render_time_in_us)
465 + (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ));
466 unsigned int exit_frame_duration_in_us = 1000000000/exit_refresh_rate_in_milli_hz;
467
468 if (last_render_time_in_us < exit_frame_duration_in_us) {
469 /* Exit Fixed Refresh mode */
470 if (in_out_vrr->fixed.fixed_active) {
471 in_out_vrr->fixed.frame_counter++;
472
473 if (in_out_vrr->fixed.frame_counter >
474 FIXED_REFRESH_EXIT_FRAME_COUNT) {
475 in_out_vrr->fixed.frame_counter = 0;
476 in_out_vrr->fixed.fixed_active = false;
477 in_out_vrr->fixed.target_refresh_in_uhz = 0;
478 update = true;
479 }
480 } else
481 in_out_vrr->fixed.frame_counter = 0;
482 } else if (last_render_time_in_us > max_render_time_in_us) {
483 /* Enter Fixed Refresh mode */
484 if (!in_out_vrr->fixed.fixed_active) {
485 in_out_vrr->fixed.frame_counter++;
486
487 if (in_out_vrr->fixed.frame_counter >
488 FIXED_REFRESH_ENTER_FRAME_COUNT) {
489 in_out_vrr->fixed.frame_counter = 0;
490 in_out_vrr->fixed.fixed_active = true;
491 in_out_vrr->fixed.target_refresh_in_uhz =
492 in_out_vrr->max_refresh_in_uhz;
493 update = true;
494 }
495 } else
496 in_out_vrr->fixed.frame_counter = 0;
497 }
498
499 if (update) {
500 if (in_out_vrr->fixed.fixed_active) {
501 in_out_vrr->adjust.v_total_min =
502 mod_freesync_calc_v_total_from_refresh(
503 stream, in_out_vrr->max_refresh_in_uhz);
504 in_out_vrr->adjust.v_total_max =
505 in_out_vrr->adjust.v_total_min;
506 } else {
507 in_out_vrr->adjust.v_total_min =
508 mod_freesync_calc_v_total_from_refresh(stream,
509 in_out_vrr->max_refresh_in_uhz);
510 in_out_vrr->adjust.v_total_max =
511 mod_freesync_calc_v_total_from_refresh(stream,
512 in_out_vrr->min_refresh_in_uhz);
513 }
514 }
515}
516
517static void determine_flip_interval_workaround_req(struct mod_vrr_params *in_vrr,
518 unsigned int curr_time_stamp_in_us)
519{
520 in_vrr->flip_interval.vsync_to_flip_in_us = curr_time_stamp_in_us -
521 in_vrr->flip_interval.v_update_timestamp_in_us;
522
523 /* Determine conditions for stopping workaround */
524 if (in_vrr->flip_interval.flip_interval_workaround_active &&
525 in_vrr->flip_interval.vsyncs_between_flip < VSYNCS_BETWEEN_FLIP_THRESHOLD &&
526 in_vrr->flip_interval.vsync_to_flip_in_us > FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
527 in_vrr->flip_interval.flip_interval_detect_counter = 0;
528 in_vrr->flip_interval.program_flip_interval_workaround = true;
529 in_vrr->flip_interval.flip_interval_workaround_active = false;
530 } else {
531 /* Determine conditions for starting workaround */
532 if (in_vrr->flip_interval.vsyncs_between_flip >= VSYNCS_BETWEEN_FLIP_THRESHOLD &&
533 in_vrr->flip_interval.vsync_to_flip_in_us < FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
534 /* Increase flip interval counter we have 2 vsyncs between flips and
535 * vsync to flip interval is less than 500us
536 */
537 in_vrr->flip_interval.flip_interval_detect_counter++;
538 if (in_vrr->flip_interval.flip_interval_detect_counter > FREESYNC_CONSEC_FLIP_AFTER_VSYNC) {
539 /* Start workaround if we detect 5 consecutive instances of the above case */
540 in_vrr->flip_interval.program_flip_interval_workaround = true;
541 in_vrr->flip_interval.flip_interval_workaround_active = true;
542 }
543 } else {
544 /* Reset the flip interval counter if we condition is no longer met */
545 in_vrr->flip_interval.flip_interval_detect_counter = 0;
546 }
547 }
548
549 in_vrr->flip_interval.vsyncs_between_flip = 0;
550}
551
552static bool vrr_settings_require_update(struct core_freesync *core_freesync,
553 struct mod_freesync_config *in_config,
554 unsigned int min_refresh_in_uhz,
555 unsigned int max_refresh_in_uhz,
556 struct mod_vrr_params *in_vrr)
557{
558 (void)core_freesync;
559 if (in_vrr->state != in_config->state) {
560 return true;
561 } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&
562 in_vrr->fixed.target_refresh_in_uhz !=
563 in_config->fixed_refresh_in_uhz) {
564 return true;
565 } else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {
566 return true;
567 } else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) {
568 return true;
569 }
570
571 return false;
572}
573
574static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
575 struct dc_info_packet *infopacket,
576 bool freesync_on_desktop)
577{
578 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
579 infopacket->sb[1] = 0x1A;
580
581 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
582 infopacket->sb[2] = 0x00;
583
584 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
585 infopacket->sb[3] = 0x00;
586
587 /* PB4 = Reserved */
588
589 /* PB5 = Reserved */
590
591 /* PB6 = [Bits 7:3 = Reserved] */
592
593 /* PB6 = [Bit 0 = FreeSync Supported] */
594 if (vrr->state != VRR_STATE_UNSUPPORTED)
595 infopacket->sb[6] |= 0x01;
596
597 /* PB6 = [Bit 1 = FreeSync Enabled] */
598 if (vrr->state != VRR_STATE_DISABLED &&
599 vrr->state != VRR_STATE_UNSUPPORTED)
600 infopacket->sb[6] |= 0x02;
601
602 if (freesync_on_desktop) {
603 /* PB6 = [Bit 2 = FreeSync Active] */
604 if (vrr->state != VRR_STATE_DISABLED &&
605 vrr->state != VRR_STATE_UNSUPPORTED)
606 infopacket->sb[6] |= 0x04;
607 } else {
608 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
609 vrr->state == VRR_STATE_ACTIVE_FIXED)
610 infopacket->sb[6] |= 0x04;
611 }
612
613 // For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range
614 /* PB7 = FreeSync Minimum refresh rate (Hz) */
615 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
616 vrr->state == VRR_STATE_ACTIVE_FIXED) {
617 infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 500000) / 1000000);
618 } else {
619 infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
620 }
621
622 /* PB8 = FreeSync Maximum refresh rate (Hz)
623 * Note: We should never go above the field rate of the mode timing set.
624 */
625 infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
626}
627
628static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
629 struct dc_info_packet *infopacket,
630 bool freesync_on_desktop)
631{
632 unsigned int min_refresh;
633 unsigned int max_refresh;
634 unsigned int fixed_refresh;
635 unsigned int min_programmed;
636
637 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
638 infopacket->sb[1] = 0x1A;
639
640 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
641 infopacket->sb[2] = 0x00;
642
643 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
644 infopacket->sb[3] = 0x00;
645
646 /* PB4 = Reserved */
647
648 /* PB5 = Reserved */
649
650 /* PB6 = [Bits 7:3 = Reserved] */
651
652 /* PB6 = [Bit 0 = FreeSync Supported] */
653 if (vrr->state != VRR_STATE_UNSUPPORTED)
654 infopacket->sb[6] |= 0x01;
655
656 /* PB6 = [Bit 1 = FreeSync Enabled] */
657 if (vrr->state != VRR_STATE_DISABLED &&
658 vrr->state != VRR_STATE_UNSUPPORTED)
659 infopacket->sb[6] |= 0x02;
660
661 /* PB6 = [Bit 2 = FreeSync Active] */
662 if (freesync_on_desktop) {
663 if (vrr->state != VRR_STATE_DISABLED &&
664 vrr->state != VRR_STATE_UNSUPPORTED)
665 infopacket->sb[6] |= 0x04;
666 } else {
667 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
668 vrr->state == VRR_STATE_ACTIVE_FIXED)
669 infopacket->sb[6] |= 0x04;
670 }
671
672 min_refresh = (vrr->min_refresh_in_uhz + 500000) / 1000000;
673 max_refresh = (vrr->max_refresh_in_uhz + 500000) / 1000000;
674 fixed_refresh = (vrr->fixed_refresh_in_uhz + 500000) / 1000000;
675
676 min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :
677 (vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh :
678 (vrr->state == VRR_STATE_INACTIVE) ? min_refresh :
679 max_refresh; // Non-fs case, program nominal range
680
681 /* PB7 = FreeSync Minimum refresh rate (Hz) */
682 infopacket->sb[7] = min_programmed & 0xFF;
683
684 /* PB8 = FreeSync Maximum refresh rate (Hz) */
685 infopacket->sb[8] = max_refresh & 0xFF;
686
687 /* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 11:8 */
688 infopacket->sb[11] = (min_programmed >> 8) & 0x0F;
689
690 /* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 11:8 */
691 infopacket->sb[12] = (max_refresh >> 8) & 0x0F;
692
693 /* PB16 : Reserved bits 7:1, FixedRate bit 0 */
694 infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;
695}
696
697static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
698 struct dc_info_packet *infopacket)
699{
700 if (app_tf != TRANSFER_FUNC_UNKNOWN) {
701 infopacket->valid = true;
702
703 if (app_tf == TRANSFER_FUNC_PQ2084)
704 infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]
705 else {
706 infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active]
707 if (app_tf == TRANSFER_FUNC_GAMMA_22)
708 infopacket->sb[9] |= 0x04; // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]
709 }
710 }
711}
712
713static void build_vrr_infopacket_header_v1(enum signal_type signal,
714 struct dc_info_packet *infopacket,
715 unsigned int *payload_size)
716{
717 if (dc_is_hdmi_signal(signal)) {
718
719 /* HEADER */
720
721 /* HB0 = Packet Type = 0x83 (Source Product
722 * Descriptor InfoFrame)
723 */
724 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
725
726 /* HB1 = Version = 0x01 */
727 infopacket->hb1 = 0x01;
728
729 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
730 infopacket->hb2 = 0x08;
731
732 *payload_size = 0x08;
733
734 } else if (dc_is_dp_signal(signal)) {
735
736 /* HEADER */
737
738 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
739 * when used to associate audio related info packets
740 */
741 infopacket->hb0 = 0x00;
742
743 /* HB1 = Packet Type = 0x83 (Source Product
744 * Descriptor InfoFrame)
745 */
746 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
747
748 /* HB2 = [Bits 7:0 = Least significant eight bits -
749 * For INFOFRAME, the value must be 1Bh]
750 */
751 infopacket->hb2 = 0x1B;
752
753 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
754 * [Bits 1:0 = Most significant two bits = 0x00]
755 */
756 infopacket->hb3 = 0x04;
757
758 *payload_size = 0x1B;
759 }
760}
761
762static void build_vrr_infopacket_header_v2(enum signal_type signal,
763 struct dc_info_packet *infopacket,
764 unsigned int *payload_size)
765{
766 if (dc_is_hdmi_signal(signal)) {
767
768 /* HEADER */
769
770 /* HB0 = Packet Type = 0x83 (Source Product
771 * Descriptor InfoFrame)
772 */
773 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
774
775 /* HB1 = Version = 0x02 */
776 infopacket->hb1 = 0x02;
777
778 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */
779 infopacket->hb2 = 0x09;
780
781 *payload_size = 0x09;
782 } else if (dc_is_dp_signal(signal)) {
783
784 /* HEADER */
785
786 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
787 * when used to associate audio related info packets
788 */
789 infopacket->hb0 = 0x00;
790
791 /* HB1 = Packet Type = 0x83 (Source Product
792 * Descriptor InfoFrame)
793 */
794 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
795
796 /* HB2 = [Bits 7:0 = Least significant eight bits -
797 * For INFOFRAME, the value must be 1Bh]
798 */
799 infopacket->hb2 = 0x1B;
800
801 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
802 * [Bits 1:0 = Most significant two bits = 0x00]
803 */
804 infopacket->hb3 = 0x08;
805
806 *payload_size = 0x1B;
807 }
808}
809
810static void build_vrr_infopacket_header_v3(enum signal_type signal,
811 struct dc_info_packet *infopacket,
812 unsigned int *payload_size)
813{
814 unsigned char version;
815
816 version = 3;
817 if (dc_is_hdmi_signal(signal)) {
818
819 /* HEADER */
820
821 /* HB0 = Packet Type = 0x83 (Source Product
822 * Descriptor InfoFrame)
823 */
824 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
825
826 /* HB1 = Version = 0x03 */
827 infopacket->hb1 = version;
828
829 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length] */
830 infopacket->hb2 = 0x10;
831
832 *payload_size = 0x10;
833 } else if (dc_is_dp_signal(signal)) {
834
835 /* HEADER */
836
837 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
838 * when used to associate audio related info packets
839 */
840 infopacket->hb0 = 0x00;
841
842 /* HB1 = Packet Type = 0x83 (Source Product
843 * Descriptor InfoFrame)
844 */
845 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
846
847 /* HB2 = [Bits 7:0 = Least significant eight bits -
848 * For INFOFRAME, the value must be 1Bh]
849 */
850 infopacket->hb2 = 0x1B;
851
852 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
853 * [Bits 1:0 = Most significant two bits = 0x00]
854 */
855
856 infopacket->hb3 = (version & 0x3F) << 2;
857
858 *payload_size = 0x1B;
859 }
860}
861
862static void build_vrr_infopacket_checksum(unsigned int *payload_size,
863 struct dc_info_packet *infopacket)
864{
865 /* Calculate checksum */
866 unsigned int idx = 0;
867 unsigned char checksum = 0;
868
869 checksum += infopacket->hb0;
870 checksum += infopacket->hb1;
871 checksum += infopacket->hb2;
872 checksum += infopacket->hb3;
873
874 for (idx = 1; idx <= *payload_size; idx++)
875 checksum += infopacket->sb[idx];
876
877 /* PB0 = Checksum (one byte complement) */
878 infopacket->sb[0] = (unsigned char)(0x100 - checksum);
879
880 infopacket->valid = true;
881}
882
883static void build_vrr_infopacket_v1(enum signal_type signal,
884 const struct mod_vrr_params *vrr,
885 struct dc_info_packet *infopacket,
886 bool freesync_on_desktop)
887{
888 /* SPD info packet for FreeSync */
889 unsigned int payload_size = 0;
890
891 build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);
892 build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
893 build_vrr_infopacket_checksum(&payload_size, infopacket);
894
895 infopacket->valid = true;
896}
897
898static void build_vrr_infopacket_v2(enum signal_type signal,
899 const struct mod_vrr_params *vrr,
900 enum color_transfer_func app_tf,
901 struct dc_info_packet *infopacket,
902 bool freesync_on_desktop)
903{
904 unsigned int payload_size = 0;
905
906 build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
907 build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
908
909 build_vrr_infopacket_fs2_data(app_tf, infopacket);
910
911 build_vrr_infopacket_checksum(&payload_size, infopacket);
912
913 infopacket->valid = true;
914}
915
916static void build_vrr_infopacket_v3(enum signal_type signal,
917 const struct mod_vrr_params *vrr,
918 enum color_transfer_func app_tf,
919 struct dc_info_packet *infopacket,
920 bool freesync_on_desktop)
921{
922 unsigned int payload_size = 0;
923
924 build_vrr_infopacket_header_v3(signal, infopacket, &payload_size);
925 build_vrr_infopacket_data_v3(vrr, infopacket, freesync_on_desktop);
926
927 build_vrr_infopacket_fs2_data(app_tf, infopacket);
928
929 build_vrr_infopacket_checksum(&payload_size, infopacket);
930
931 infopacket->valid = true;
932}
933
934static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type,
935 struct dc_info_packet *infopacket)
936{
937 uint8_t idx = 0, size = 0;
938
939 size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 :
940 (packet_type == PACKET_TYPE_FS_V3) ? 0x10 :
941 0x09);
942
943 for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B
944 infopacket->sb[idx] = infopacket->sb[idx-1];
945
946 infopacket->sb[1] = size; // Length
947 infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version
948 infopacket->hb3 = (0x13 << 2); // Header,SDP 1.3
949 infopacket->hb2 = 0x1D;
950}
951
952void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
953 const struct dc_stream_state *stream,
954 const struct mod_vrr_params *vrr,
955 enum vrr_packet_type packet_type,
956 enum color_transfer_func app_tf,
957 struct dc_info_packet *infopacket,
958 bool pack_sdp_v1_3)
959{
960 (void)mod_freesync;
961 /* SPD info packet for FreeSync
962 * VTEM info packet for HdmiVRR
963 * Check if Freesync is supported. Return if false. If true,
964 * set the corresponding bit in the info packet
965 */
966 if (!vrr->send_info_frame)
967 return;
968
969 switch (packet_type) {
970 case PACKET_TYPE_FS_V3:
971 build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
972 break;
973 case PACKET_TYPE_FS_V2:
974 build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
975 break;
976 case PACKET_TYPE_VRR:
977 case PACKET_TYPE_FS_V1:
978 default:
979 build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop);
980 }
981
982 if (true == pack_sdp_v1_3 &&
983 true == dc_is_dp_signal(stream->signal) &&
984 packet_type != PACKET_TYPE_VRR &&
985 packet_type != PACKET_TYPE_VTEM)
986 build_vrr_infopacket_sdp_v1_3(packet_type, infopacket);
987}
988
989void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
990 const struct dc_stream_state *stream,
991 struct mod_freesync_config *in_config,
992 struct mod_vrr_params *in_out_vrr)
993{
994 struct core_freesync *core_freesync = NULL;
995 unsigned long long nominal_field_rate_in_uhz = 0;
996 unsigned long long rounded_nominal_in_uhz = 0;
997 unsigned int refresh_range = 0;
998 unsigned long long min_refresh_in_uhz = 0;
999 unsigned long long max_refresh_in_uhz = 0;
1000 unsigned long long min_hardware_refresh_in_uhz = 0;
1001
1002 if (mod_freesync == NULL)
1003 return;
1004
1005 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1006
1007 /* Calculate nominal field rate for stream */
1008 nominal_field_rate_in_uhz =
1009 mod_freesync_calc_nominal_field_rate(stream);
1010
1011 if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
1012 min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
1013 (stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));
1014 }
1015 /* Limit minimum refresh rate to what can be supported by hardware */
1016 min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?
1017 min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz;
1018 max_refresh_in_uhz = in_config->max_refresh_in_uhz;
1019
1020 /* Full range may be larger than current video timing, so cap at nominal */
1021 if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
1022 max_refresh_in_uhz = nominal_field_rate_in_uhz;
1023
1024 /* Full range may be larger than current video timing, so cap at nominal */
1025 if (min_refresh_in_uhz > max_refresh_in_uhz)
1026 min_refresh_in_uhz = max_refresh_in_uhz;
1027
1028 /* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */
1029 rounded_nominal_in_uhz =
1030 div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000;
1031 if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) &&
1032 in_config->max_refresh_in_uhz == rounded_nominal_in_uhz)
1033 min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2);
1034
1035 if (!vrr_settings_require_update(core_freesync,
1036 in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz,
1037 in_out_vrr))
1038 return;
1039
1040 in_out_vrr->state = in_config->state;
1041 in_out_vrr->send_info_frame = in_config->vsif_supported;
1042
1043 if (in_config->state == VRR_STATE_UNSUPPORTED) {
1044 in_out_vrr->state = VRR_STATE_UNSUPPORTED;
1045 in_out_vrr->supported = false;
1046 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1047 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1048
1049 return;
1050
1051 } else {
1052 in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz;
1053 in_out_vrr->max_duration_in_us =
1054 calc_duration_in_us_from_refresh_in_uhz(
1055 (unsigned int)min_refresh_in_uhz);
1056
1057 in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz;
1058 in_out_vrr->min_duration_in_us =
1059 calc_duration_in_us_from_refresh_in_uhz(
1060 (unsigned int)max_refresh_in_uhz);
1061
1062 if (in_config->state == VRR_STATE_ACTIVE_FIXED)
1063 in_out_vrr->fixed_refresh_in_uhz = in_config->fixed_refresh_in_uhz;
1064 else
1065 in_out_vrr->fixed_refresh_in_uhz = 0;
1066
1067 {
1068 uint64_t rr_tmp = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) -
1069 div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000);
1070 ASSERT(rr_tmp <= 0xFFFFFFFF);
1071 refresh_range = (unsigned int)rr_tmp;
1072 }
1073
1074 in_out_vrr->supported = true;
1075 }
1076
1077 in_out_vrr->fixed.ramping_active = in_config->ramping;
1078
1079 in_out_vrr->btr.btr_enabled = in_config->btr;
1080
1081 if (in_out_vrr->max_refresh_in_uhz < (2 * in_out_vrr->min_refresh_in_uhz))
1082 in_out_vrr->btr.btr_enabled = false;
1083 else {
1084 in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
1085 2 * in_out_vrr->min_duration_in_us;
1086 if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
1087 in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
1088 }
1089
1090 in_out_vrr->btr.btr_active = false;
1091 in_out_vrr->btr.inserted_duration_in_us = 0;
1092 in_out_vrr->btr.frames_to_insert = 0;
1093 in_out_vrr->btr.frame_counter = 0;
1094 in_out_vrr->fixed.fixed_active = false;
1095 in_out_vrr->fixed.target_refresh_in_uhz = 0;
1096
1097 in_out_vrr->btr.mid_point_in_us =
1098 (in_out_vrr->min_duration_in_us +
1099 in_out_vrr->max_duration_in_us) / 2;
1100
1101 if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
1102 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1103 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1104 } else if (in_out_vrr->state == VRR_STATE_DISABLED) {
1105 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1106 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1107 } else if (in_out_vrr->state == VRR_STATE_INACTIVE) {
1108 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1109 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1110 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1111 refresh_range >= MIN_REFRESH_RANGE) {
1112
1113 in_out_vrr->adjust.v_total_min =
1114 mod_freesync_calc_v_total_from_refresh(stream,
1115 in_out_vrr->max_refresh_in_uhz);
1116 in_out_vrr->adjust.v_total_max =
1117 mod_freesync_calc_v_total_from_refresh(stream,
1118 in_out_vrr->min_refresh_in_uhz);
1119 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) {
1120 in_out_vrr->fixed.target_refresh_in_uhz =
1121 in_out_vrr->fixed_refresh_in_uhz;
1122 if (in_out_vrr->fixed.ramping_active &&
1123 in_out_vrr->fixed.fixed_active) {
1124 /* Do not update vtotals if ramping is already active
1125 * in order to continue ramp from current refresh.
1126 */
1127 in_out_vrr->fixed.fixed_active = true;
1128 } else {
1129 in_out_vrr->fixed.fixed_active = true;
1130 in_out_vrr->adjust.v_total_min =
1131 mod_freesync_calc_v_total_from_refresh(stream,
1132 in_out_vrr->fixed.target_refresh_in_uhz);
1133 in_out_vrr->adjust.v_total_max =
1134 in_out_vrr->adjust.v_total_min;
1135 }
1136 } else {
1137 in_out_vrr->state = VRR_STATE_INACTIVE;
1138 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1139 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1140 }
1141
1142 in_out_vrr->adjust.allow_otg_v_count_halt = (in_config->state == VRR_STATE_ACTIVE_FIXED) ? true : false;
1143}
1144
1145void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
1146 const struct dc_plane_state *plane,
1147 const struct dc_stream_state *stream,
1148 unsigned int curr_time_stamp_in_us,
1149 struct mod_vrr_params *in_out_vrr)
1150{
1151 struct core_freesync *core_freesync = NULL;
1152 unsigned int last_render_time_in_us = 0;
1153
1154 if (mod_freesync == NULL)
1155 return;
1156
1157 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1158
1159 if (in_out_vrr->supported &&
1160 in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
1161
1162 last_render_time_in_us = curr_time_stamp_in_us -
1163 plane->time.prev_update_time_in_us;
1164
1165 if (in_out_vrr->btr.btr_enabled) {
1166 apply_below_the_range(core_freesync,
1167 stream,
1168 last_render_time_in_us,
1169 in_out_vrr);
1170 } else {
1171 apply_fixed_refresh(core_freesync,
1172 stream,
1173 last_render_time_in_us,
1174 in_out_vrr);
1175 }
1176
1177 determine_flip_interval_workaround_req(in_out_vrr,
1178 curr_time_stamp_in_us);
1179
1180 }
1181}
1182
1183void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
1184 const struct dc_stream_state *stream,
1185 struct mod_vrr_params *in_out_vrr)
1186{
1187 struct core_freesync *core_freesync = NULL;
1188 unsigned int cur_timestamp_in_us;
1189 unsigned long long cur_tick;
1190
1191 if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
1192 return;
1193
1194 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1195
1196 if (in_out_vrr->supported == false)
1197 return;
1198
1199 cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
1200 cur_timestamp_in_us = (unsigned int)
1201 div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
1202
1203 in_out_vrr->flip_interval.vsyncs_between_flip++;
1204 in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
1205
1206 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1207 (in_out_vrr->flip_interval.flip_interval_workaround_active ||
1208 (!in_out_vrr->flip_interval.flip_interval_workaround_active &&
1209 in_out_vrr->flip_interval.program_flip_interval_workaround))) {
1210 // set freesync vmin vmax to nominal for workaround
1211 in_out_vrr->adjust.v_total_min =
1212 mod_freesync_calc_v_total_from_refresh(
1213 stream, in_out_vrr->max_refresh_in_uhz);
1214 in_out_vrr->adjust.v_total_max =
1215 in_out_vrr->adjust.v_total_min;
1216 in_out_vrr->flip_interval.program_flip_interval_workaround = false;
1217 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true;
1218 return;
1219 }
1220
1221 if (in_out_vrr->state != VRR_STATE_ACTIVE_VARIABLE &&
1222 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup) {
1223 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false;
1224 in_out_vrr->flip_interval.flip_interval_detect_counter = 0;
1225 in_out_vrr->flip_interval.vsyncs_between_flip = 0;
1226 in_out_vrr->flip_interval.vsync_to_flip_in_us = 0;
1227 }
1228
1229 /* Below the Range Logic */
1230
1231 /* Only execute if in fullscreen mode */
1232 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1233 in_out_vrr->btr.btr_active) {
1234 /* TODO: pass in flag for Pre-DCE12 ASIC
1235 * in order for frame variable duration to take affect,
1236 * it needs to be done one VSYNC early, which is at
1237 * frameCounter == 1.
1238 * For DCE12 and newer updates to V_TOTAL_MIN/MAX
1239 * will take affect on current frame
1240 */
1241 if (in_out_vrr->btr.frames_to_insert ==
1242 in_out_vrr->btr.frame_counter) {
1243 in_out_vrr->adjust.v_total_min =
1244 calc_v_total_from_duration(stream,
1245 in_out_vrr,
1246 in_out_vrr->btr.inserted_duration_in_us);
1247 in_out_vrr->adjust.v_total_max =
1248 in_out_vrr->adjust.v_total_min;
1249 }
1250
1251 if (in_out_vrr->btr.frame_counter > 0)
1252 in_out_vrr->btr.frame_counter--;
1253
1254 /* Restore FreeSync */
1255 if (in_out_vrr->btr.frame_counter == 0) {
1256 in_out_vrr->adjust.v_total_min =
1257 mod_freesync_calc_v_total_from_refresh(stream,
1258 in_out_vrr->max_refresh_in_uhz);
1259 in_out_vrr->adjust.v_total_max =
1260 mod_freesync_calc_v_total_from_refresh(stream,
1261 in_out_vrr->min_refresh_in_uhz);
1262 }
1263 }
1264
1265 /* If in fullscreen freesync mode or in video, do not program
1266 * static screen ramp values
1267 */
1268 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)
1269 in_out_vrr->fixed.ramping_active = false;
1270
1271 /* Gradual Static Screen Ramping Logic
1272 * Execute if ramp is active and user enabled freesync static screen
1273 */
1274 if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&
1275 in_out_vrr->fixed.ramping_active) {
1276 update_v_total_for_static_ramp(
1277 core_freesync, stream, in_out_vrr);
1278 }
1279
1280 /*
1281 * If VRR is inactive, set vtotal min and max to nominal vtotal
1282 */
1283 if (in_out_vrr->state == VRR_STATE_INACTIVE) {
1284 in_out_vrr->adjust.v_total_min =
1285 mod_freesync_calc_v_total_from_refresh(stream,
1286 in_out_vrr->max_refresh_in_uhz);
1287 in_out_vrr->adjust.v_total_max = in_out_vrr->adjust.v_total_min;
1288 return;
1289 }
1290}
1291
1292unsigned long long mod_freesync_calc_nominal_field_rate(
1293 const struct dc_stream_state *stream)
1294{
1295 unsigned long long nominal_field_rate_in_uhz = 0;
1296 unsigned int total = stream->timing.h_total * stream->timing.v_total;
1297
1298 /* Calculate nominal field rate for stream, rounded up to nearest integer */
1299 nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;
1300 nominal_field_rate_in_uhz *= 100000000ULL;
1301
1302 nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, total);
1303
1304 return nominal_field_rate_in_uhz;
1305}
1306
1307bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)
1308{
1309 return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);
1310}