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| 2 | * Copyright 2015 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 |
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| 22 |
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| 23 | #ifndef __AMD_PCIE_H__
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| 24 | #define __AMD_PCIE_H__
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| 25 |
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| 26 |
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| 27 | #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
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| 28 | #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
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| 29 | #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
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| 30 | #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
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| 31 | #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00100000
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| 32 | #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
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| 33 | #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
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| 34 |
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| 35 |
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| 36 | #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
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| 37 | #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
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| 38 | #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
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| 39 | #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
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| 40 | #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5 0x00000010
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| 41 | #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
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| 42 | #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
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| 43 |
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| 44 |
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| 45 | #define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \
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| 46 | | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \
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| 47 | | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \
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| 48 | | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \
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| 49 | | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
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| 50 |
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| 51 |
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| 52 |
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| 53 | #define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1 0x00000001
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| 54 | #define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 0x00000002
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| 55 | #define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 0x00000004
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| 56 | #define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 0x00000008
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| 57 | #define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 0x00000010
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| 58 | #define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 0x00000020
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| 59 | #define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 0x00000040
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| 60 | #define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_MASK 0x0000FFFF
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| 61 | #define CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_SHIFT 0
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| 62 |
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| 63 | #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000
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| 64 | #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000
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| 65 | #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000
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| 66 | #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000
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| 67 | #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000
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| 68 | #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000
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| 69 | #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000
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| 70 | #define CAIL_PCIE_LINK_WIDTH_SUPPORT_MASK 0xFFFF0000
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| 71 | #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16
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| 72 |
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| 73 |
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| 74 | #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
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| 75 | | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \
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| 76 | | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \
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| 77 | | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
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| 78 | | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
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| 79 |
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| 80 | #define AMDGPU_DEFAULT_ASIC_PCIE_MLW_MASK (CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X1 \
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| 81 | | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 \
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| 82 | | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 \
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| 83 | | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 \
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| 84 | | CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16)
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| 85 |
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| 86 | #endif
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