| 1 | |
| 2 | * Copyright (C) 2018 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included
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| 12 | * in all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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| 20 |
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| 21 | #ifndef _arct_ip_offset_HEADER
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| 22 | #define _arct_ip_offset_HEADER
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| 23 |
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| 24 | #define MAX_INSTANCE 8
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| 25 | #define MAX_SEGMENT 6
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| 26 |
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| 27 |
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| 28 | struct IP_BASE_INSTANCE {
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| 29 | unsigned int segment[MAX_SEGMENT];
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| 30 | } __maybe_unused;
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| 31 |
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| 32 | struct IP_BASE {
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| 33 | struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
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| 34 | } __maybe_unused;
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| 35 |
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| 36 |
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| 37 | static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } },
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| 38 | { { 0, 0, 0, 0, 0, 0 } },
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| 39 | { { 0, 0, 0, 0, 0, 0 } },
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| 40 | { { 0, 0, 0, 0, 0, 0 } },
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| 41 | { { 0, 0, 0, 0, 0, 0 } },
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| 42 | { { 0, 0, 0, 0, 0, 0 } },
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| 43 | { { 0, 0, 0, 0, 0, 0 } },
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| 44 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 45 | static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } },
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| 46 | { { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } },
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| 47 | { { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } },
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| 48 | { { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } },
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| 49 | { { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } },
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| 50 | { { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } },
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| 51 | { { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } },
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| 52 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 53 | static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } },
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| 54 | { { 0, 0, 0, 0, 0, 0 } },
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| 55 | { { 0, 0, 0, 0, 0, 0 } },
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| 56 | { { 0, 0, 0, 0, 0, 0 } },
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| 57 | { { 0, 0, 0, 0, 0, 0 } },
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| 58 | { { 0, 0, 0, 0, 0, 0 } },
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| 59 | { { 0, 0, 0, 0, 0, 0 } },
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| 60 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 61 | static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } },
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| 62 | { { 0, 0, 0, 0, 0, 0 } },
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| 63 | { { 0, 0, 0, 0, 0, 0 } },
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| 64 | { { 0, 0, 0, 0, 0, 0 } },
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| 65 | { { 0, 0, 0, 0, 0, 0 } },
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| 66 | { { 0, 0, 0, 0, 0, 0 } },
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| 67 | { { 0, 0, 0, 0, 0, 0 } },
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| 68 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 69 | static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } },
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| 70 | { { 0, 0, 0, 0, 0, 0 } },
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| 71 | { { 0, 0, 0, 0, 0, 0 } },
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| 72 | { { 0, 0, 0, 0, 0, 0 } },
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| 73 | { { 0, 0, 0, 0, 0, 0 } },
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| 74 | { { 0, 0, 0, 0, 0, 0 } },
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| 75 | { { 0, 0, 0, 0, 0, 0 } },
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| 76 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 77 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } },
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| 78 | { { 0, 0, 0, 0, 0, 0 } },
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| 79 | { { 0, 0, 0, 0, 0, 0 } },
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| 80 | { { 0, 0, 0, 0, 0, 0 } },
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| 81 | { { 0, 0, 0, 0, 0, 0 } },
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| 82 | { { 0, 0, 0, 0, 0, 0 } },
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| 83 | { { 0, 0, 0, 0, 0, 0 } },
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| 84 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 85 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } },
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| 86 | { { 0, 0, 0, 0, 0, 0 } },
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| 87 | { { 0, 0, 0, 0, 0, 0 } },
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| 88 | { { 0, 0, 0, 0, 0, 0 } },
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| 89 | { { 0, 0, 0, 0, 0, 0 } },
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| 90 | { { 0, 0, 0, 0, 0, 0 } },
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| 91 | { { 0, 0, 0, 0, 0, 0 } },
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| 92 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 93 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
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| 94 | { { 0, 0, 0, 0, 0, 0 } },
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| 95 | { { 0, 0, 0, 0, 0, 0 } },
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| 96 | { { 0, 0, 0, 0, 0, 0 } },
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| 97 | { { 0, 0, 0, 0, 0, 0 } },
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| 98 | { { 0, 0, 0, 0, 0, 0 } },
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| 99 | { { 0, 0, 0, 0, 0, 0 } },
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| 100 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 101 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
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| 102 | { { 0, 0, 0, 0, 0, 0 } },
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| 103 | { { 0, 0, 0, 0, 0, 0 } },
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| 104 | { { 0, 0, 0, 0, 0, 0 } },
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| 105 | { { 0, 0, 0, 0, 0, 0 } },
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| 106 | { { 0, 0, 0, 0, 0, 0 } },
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| 107 | { { 0, 0, 0, 0, 0, 0 } },
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| 108 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 109 | static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } },
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| 110 | { { 0, 0, 0, 0, 0, 0 } },
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| 111 | { { 0, 0, 0, 0, 0, 0 } },
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| 112 | { { 0, 0, 0, 0, 0, 0 } },
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| 113 | { { 0, 0, 0, 0, 0, 0 } },
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| 114 | { { 0, 0, 0, 0, 0, 0 } },
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| 115 | { { 0, 0, 0, 0, 0, 0 } },
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| 116 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 117 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } },
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| 118 | { { 0, 0, 0, 0, 0, 0 } },
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| 119 | { { 0, 0, 0, 0, 0, 0 } },
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| 120 | { { 0, 0, 0, 0, 0, 0 } },
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| 121 | { { 0, 0, 0, 0, 0, 0 } },
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| 122 | { { 0, 0, 0, 0, 0, 0 } },
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| 123 | { { 0, 0, 0, 0, 0, 0 } },
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| 124 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 125 | static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } },
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| 126 | { { 0, 0, 0, 0, 0, 0 } },
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| 127 | { { 0, 0, 0, 0, 0, 0 } },
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| 128 | { { 0, 0, 0, 0, 0, 0 } },
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| 129 | { { 0, 0, 0, 0, 0, 0 } },
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| 130 | { { 0, 0, 0, 0, 0, 0 } },
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| 131 | { { 0, 0, 0, 0, 0, 0 } },
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| 132 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 133 | static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },
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| 134 | { { 0, 0, 0, 0, 0, 0 } },
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| 135 | { { 0, 0, 0, 0, 0, 0 } },
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| 136 | { { 0, 0, 0, 0, 0, 0 } },
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| 137 | { { 0, 0, 0, 0, 0, 0 } },
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| 138 | { { 0, 0, 0, 0, 0, 0 } },
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| 139 | { { 0, 0, 0, 0, 0, 0 } },
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| 140 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 141 | static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },
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| 142 | { { 0, 0, 0, 0, 0, 0 } },
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| 143 | { { 0, 0, 0, 0, 0, 0 } },
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| 144 | { { 0, 0, 0, 0, 0, 0 } },
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| 145 | { { 0, 0, 0, 0, 0, 0 } },
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| 146 | { { 0, 0, 0, 0, 0, 0 } },
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| 147 | { { 0, 0, 0, 0, 0, 0 } },
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| 148 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 149 | static const struct IP_BASE SDMA2_BASE ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },
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| 150 | { { 0, 0, 0, 0, 0, 0 } },
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| 151 | { { 0, 0, 0, 0, 0, 0 } },
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| 152 | { { 0, 0, 0, 0, 0, 0 } },
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| 153 | { { 0, 0, 0, 0, 0, 0 } },
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| 154 | { { 0, 0, 0, 0, 0, 0 } },
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| 155 | { { 0, 0, 0, 0, 0, 0 } },
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| 156 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 157 | static const struct IP_BASE SDMA3_BASE ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },
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| 158 | { { 0, 0, 0, 0, 0, 0 } },
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| 159 | { { 0, 0, 0, 0, 0, 0 } },
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| 160 | { { 0, 0, 0, 0, 0, 0 } },
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| 161 | { { 0, 0, 0, 0, 0, 0 } },
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| 162 | { { 0, 0, 0, 0, 0, 0 } },
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| 163 | { { 0, 0, 0, 0, 0, 0 } },
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| 164 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 165 | static const struct IP_BASE SDMA4_BASE ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },
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| 166 | { { 0, 0, 0, 0, 0, 0 } },
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| 167 | { { 0, 0, 0, 0, 0, 0 } },
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| 168 | { { 0, 0, 0, 0, 0, 0 } },
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| 169 | { { 0, 0, 0, 0, 0, 0 } },
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| 170 | { { 0, 0, 0, 0, 0, 0 } },
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| 171 | { { 0, 0, 0, 0, 0, 0 } },
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| 172 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 173 | static const struct IP_BASE SDMA5_BASE ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } },
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| 174 | { { 0, 0, 0, 0, 0, 0 } },
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| 175 | { { 0, 0, 0, 0, 0, 0 } },
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| 176 | { { 0, 0, 0, 0, 0, 0 } },
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| 177 | { { 0, 0, 0, 0, 0, 0 } },
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| 178 | { { 0, 0, 0, 0, 0, 0 } },
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| 179 | { { 0, 0, 0, 0, 0, 0 } },
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| 180 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 181 | static const struct IP_BASE SDMA6_BASE ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } },
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| 182 | { { 0, 0, 0, 0, 0, 0 } },
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| 183 | { { 0, 0, 0, 0, 0, 0 } },
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| 184 | { { 0, 0, 0, 0, 0, 0 } },
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| 185 | { { 0, 0, 0, 0, 0, 0 } },
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| 186 | { { 0, 0, 0, 0, 0, 0 } },
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| 187 | { { 0, 0, 0, 0, 0, 0 } },
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| 188 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 189 | static const struct IP_BASE SDMA7_BASE ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } },
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| 190 | { { 0, 0, 0, 0, 0, 0 } },
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| 191 | { { 0, 0, 0, 0, 0, 0 } },
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| 192 | { { 0, 0, 0, 0, 0, 0 } },
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| 193 | { { 0, 0, 0, 0, 0, 0 } },
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| 194 | { { 0, 0, 0, 0, 0, 0 } },
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| 195 | { { 0, 0, 0, 0, 0, 0 } },
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| 196 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 197 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
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| 198 | { { 0, 0, 0, 0, 0, 0 } },
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| 199 | { { 0, 0, 0, 0, 0, 0 } },
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| 200 | { { 0, 0, 0, 0, 0, 0 } },
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| 201 | { { 0, 0, 0, 0, 0, 0 } },
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| 202 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 203 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
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| 204 | { { 0, 0, 0, 0, 0, 0 } },
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| 205 | { { 0, 0, 0, 0, 0, 0 } },
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| 206 | { { 0, 0, 0, 0, 0, 0 } },
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| 207 | { { 0, 0, 0, 0, 0, 0 } },
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| 208 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 209 | static const struct IP_BASE UMC_BASE ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } },
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| 210 | { { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } },
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| 211 | { { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } },
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| 212 | { { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } },
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| 213 | { { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } },
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| 214 | { { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } },
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| 215 | { { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } },
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| 216 | { { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } };
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| 217 | static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } },
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| 218 | { { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } },
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| 219 | { { 0, 0, 0, 0, 0, 0 } },
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| 220 | { { 0, 0, 0, 0, 0, 0 } },
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| 221 | { { 0, 0, 0, 0, 0, 0 } },
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| 222 | { { 0, 0, 0, 0, 0, 0 } },
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| 223 | { { 0, 0, 0, 0, 0, 0 } },
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| 224 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 225 | static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } },
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| 226 | { { 0, 0, 0, 0, 0, 0 } },
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| 227 | { { 0, 0, 0, 0, 0, 0 } },
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| 228 | { { 0, 0, 0, 0, 0, 0 } },
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| 229 | { { 0, 0, 0, 0, 0, 0 } },
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| 230 | { { 0, 0, 0, 0, 0, 0 } },
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| 231 | { { 0, 0, 0, 0, 0, 0 } },
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| 232 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 233 | static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } },
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| 234 | { { 0, 0, 0, 0, 0, 0 } },
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| 235 | { { 0, 0, 0, 0, 0, 0 } },
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| 236 | { { 0, 0, 0, 0, 0, 0 } },
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| 237 | { { 0, 0, 0, 0, 0, 0 } },
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| 238 | { { 0, 0, 0, 0, 0, 0 } },
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| 239 | { { 0, 0, 0, 0, 0, 0 } },
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| 240 | { { 0, 0, 0, 0, 0, 0 } } } };
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| 241 |
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| 242 |
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| 243 |
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| 244 | #define ATHUB_BASE__INST0_SEG0 0x00000C20
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| 245 | #define ATHUB_BASE__INST0_SEG1 0x00012460
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| 246 | #define ATHUB_BASE__INST0_SEG2 0x00408C00
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| 247 | #define ATHUB_BASE__INST0_SEG3 0
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| 248 | #define ATHUB_BASE__INST0_SEG4 0
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| 249 | #define ATHUB_BASE__INST0_SEG5 0
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| 250 |
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| 251 | #define ATHUB_BASE__INST1_SEG0 0
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| 252 | #define ATHUB_BASE__INST1_SEG1 0
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| 253 | #define ATHUB_BASE__INST1_SEG2 0
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| 254 | #define ATHUB_BASE__INST1_SEG3 0
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| 255 | #define ATHUB_BASE__INST1_SEG4 0
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| 256 | #define ATHUB_BASE__INST1_SEG5 0
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| 257 |
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| 258 | #define ATHUB_BASE__INST2_SEG0 0
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| 259 | #define ATHUB_BASE__INST2_SEG1 0
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| 260 | #define ATHUB_BASE__INST2_SEG2 0
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| 261 | #define ATHUB_BASE__INST2_SEG3 0
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| 262 | #define ATHUB_BASE__INST2_SEG4 0
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| 263 | #define ATHUB_BASE__INST2_SEG5 0
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| 264 |
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| 265 | #define ATHUB_BASE__INST3_SEG0 0
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| 266 | #define ATHUB_BASE__INST3_SEG1 0
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| 267 | #define ATHUB_BASE__INST3_SEG2 0
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| 268 | #define ATHUB_BASE__INST3_SEG3 0
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| 269 | #define ATHUB_BASE__INST3_SEG4 0
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| 270 | #define ATHUB_BASE__INST3_SEG5 0
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| 271 |
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| 272 | #define ATHUB_BASE__INST4_SEG0 0
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| 273 | #define ATHUB_BASE__INST4_SEG1 0
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| 274 | #define ATHUB_BASE__INST4_SEG2 0
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| 275 | #define ATHUB_BASE__INST4_SEG3 0
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| 276 | #define ATHUB_BASE__INST4_SEG4 0
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| 277 | #define ATHUB_BASE__INST4_SEG5 0
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| 278 |
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| 279 | #define ATHUB_BASE__INST5_SEG0 0
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| 280 | #define ATHUB_BASE__INST5_SEG1 0
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| 281 | #define ATHUB_BASE__INST5_SEG2 0
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| 282 | #define ATHUB_BASE__INST5_SEG3 0
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| 283 | #define ATHUB_BASE__INST5_SEG4 0
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| 284 | #define ATHUB_BASE__INST5_SEG5 0
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| 285 |
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| 286 | #define ATHUB_BASE__INST6_SEG0 0
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| 287 | #define ATHUB_BASE__INST6_SEG1 0
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| 288 | #define ATHUB_BASE__INST6_SEG2 0
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| 289 | #define ATHUB_BASE__INST6_SEG3 0
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| 290 | #define ATHUB_BASE__INST6_SEG4 0
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| 291 | #define ATHUB_BASE__INST6_SEG5 0
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| 292 |
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| 293 | #define ATHUB_BASE__INST7_SEG0 0
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| 294 | #define ATHUB_BASE__INST7_SEG1 0
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| 295 | #define ATHUB_BASE__INST7_SEG2 0
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| 296 | #define ATHUB_BASE__INST7_SEG3 0
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| 297 | #define ATHUB_BASE__INST7_SEG4 0
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| 298 | #define ATHUB_BASE__INST7_SEG5 0
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| 299 |
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| 300 | #define CLK_BASE__INST0_SEG0 0x000120C0
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| 301 | #define CLK_BASE__INST0_SEG1 0x00016C00
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| 302 | #define CLK_BASE__INST0_SEG2 0x00401800
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| 303 | #define CLK_BASE__INST0_SEG3 0
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| 304 | #define CLK_BASE__INST0_SEG4 0
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| 305 | #define CLK_BASE__INST0_SEG5 0
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| 306 |
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| 307 | #define CLK_BASE__INST1_SEG0 0x000120E0
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| 308 | #define CLK_BASE__INST1_SEG1 0x00016E00
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| 309 | #define CLK_BASE__INST1_SEG2 0x00401C00
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| 310 | #define CLK_BASE__INST1_SEG3 0
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| 311 | #define CLK_BASE__INST1_SEG4 0
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| 312 | #define CLK_BASE__INST1_SEG5 0
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| 313 |
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| 314 | #define CLK_BASE__INST2_SEG0 0x00012100
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| 315 | #define CLK_BASE__INST2_SEG1 0x00017000
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| 316 | #define CLK_BASE__INST2_SEG2 0x00402000
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| 317 | #define CLK_BASE__INST2_SEG3 0
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| 318 | #define CLK_BASE__INST2_SEG4 0
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| 319 | #define CLK_BASE__INST2_SEG5 0
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| 320 |
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| 321 | #define CLK_BASE__INST3_SEG0 0x00012120
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| 322 | #define CLK_BASE__INST3_SEG1 0x00017200
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| 323 | #define CLK_BASE__INST3_SEG2 0x00402400
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| 324 | #define CLK_BASE__INST3_SEG3 0
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| 325 | #define CLK_BASE__INST3_SEG4 0
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| 326 | #define CLK_BASE__INST3_SEG5 0
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| 327 |
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| 328 | #define CLK_BASE__INST4_SEG0 0x000136C0
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| 329 | #define CLK_BASE__INST4_SEG1 0x0001B000
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| 330 | #define CLK_BASE__INST4_SEG2 0x0042D800
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| 331 | #define CLK_BASE__INST4_SEG3 0
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| 332 | #define CLK_BASE__INST4_SEG4 0
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| 333 | #define CLK_BASE__INST4_SEG5 0
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| 334 |
|
| 335 | #define CLK_BASE__INST5_SEG0 0x00013720
|
| 336 | #define CLK_BASE__INST5_SEG1 0x0001B200
|
| 337 | #define CLK_BASE__INST5_SEG2 0x0042E400
|
| 338 | #define CLK_BASE__INST5_SEG3 0
|
| 339 | #define CLK_BASE__INST5_SEG4 0
|
| 340 | #define CLK_BASE__INST5_SEG5 0
|
| 341 |
|
| 342 | #define CLK_BASE__INST6_SEG0 0x000125E0
|
| 343 | #define CLK_BASE__INST6_SEG1 0x00017E00
|
| 344 | #define CLK_BASE__INST6_SEG2 0x0040BC00
|
| 345 | #define CLK_BASE__INST6_SEG3 0
|
| 346 | #define CLK_BASE__INST6_SEG4 0
|
| 347 | #define CLK_BASE__INST6_SEG5 0
|
| 348 |
|
| 349 | #define CLK_BASE__INST7_SEG0 0
|
| 350 | #define CLK_BASE__INST7_SEG1 0
|
| 351 | #define CLK_BASE__INST7_SEG2 0
|
| 352 | #define CLK_BASE__INST7_SEG3 0
|
| 353 | #define CLK_BASE__INST7_SEG4 0
|
| 354 | #define CLK_BASE__INST7_SEG5 0
|
| 355 |
|
| 356 | #define DF_BASE__INST0_SEG0 0x00007000
|
| 357 | #define DF_BASE__INST0_SEG1 0x000125C0
|
| 358 | #define DF_BASE__INST0_SEG2 0x0040B800
|
| 359 | #define DF_BASE__INST0_SEG3 0
|
| 360 | #define DF_BASE__INST0_SEG4 0
|
| 361 | #define DF_BASE__INST0_SEG5 0
|
| 362 |
|
| 363 | #define DF_BASE__INST1_SEG0 0
|
| 364 | #define DF_BASE__INST1_SEG1 0
|
| 365 | #define DF_BASE__INST1_SEG2 0
|
| 366 | #define DF_BASE__INST1_SEG3 0
|
| 367 | #define DF_BASE__INST1_SEG4 0
|
| 368 | #define DF_BASE__INST1_SEG5 0
|
| 369 |
|
| 370 | #define DF_BASE__INST2_SEG0 0
|
| 371 | #define DF_BASE__INST2_SEG1 0
|
| 372 | #define DF_BASE__INST2_SEG2 0
|
| 373 | #define DF_BASE__INST2_SEG3 0
|
| 374 | #define DF_BASE__INST2_SEG4 0
|
| 375 | #define DF_BASE__INST2_SEG5 0
|
| 376 |
|
| 377 | #define DF_BASE__INST3_SEG0 0
|
| 378 | #define DF_BASE__INST3_SEG1 0
|
| 379 | #define DF_BASE__INST3_SEG2 0
|
| 380 | #define DF_BASE__INST3_SEG3 0
|
| 381 | #define DF_BASE__INST3_SEG4 0
|
| 382 | #define DF_BASE__INST3_SEG5 0
|
| 383 |
|
| 384 | #define DF_BASE__INST4_SEG0 0
|
| 385 | #define DF_BASE__INST4_SEG1 0
|
| 386 | #define DF_BASE__INST4_SEG2 0
|
| 387 | #define DF_BASE__INST4_SEG3 0
|
| 388 | #define DF_BASE__INST4_SEG4 0
|
| 389 | #define DF_BASE__INST4_SEG5 0
|
| 390 |
|
| 391 | #define DF_BASE__INST5_SEG0 0
|
| 392 | #define DF_BASE__INST5_SEG1 0
|
| 393 | #define DF_BASE__INST5_SEG2 0
|
| 394 | #define DF_BASE__INST5_SEG3 0
|
| 395 | #define DF_BASE__INST5_SEG4 0
|
| 396 | #define DF_BASE__INST5_SEG5 0
|
| 397 |
|
| 398 | #define DF_BASE__INST6_SEG0 0
|
| 399 | #define DF_BASE__INST6_SEG1 0
|
| 400 | #define DF_BASE__INST6_SEG2 0
|
| 401 | #define DF_BASE__INST6_SEG3 0
|
| 402 | #define DF_BASE__INST6_SEG4 0
|
| 403 | #define DF_BASE__INST6_SEG5 0
|
| 404 |
|
| 405 | #define DF_BASE__INST7_SEG0 0
|
| 406 | #define DF_BASE__INST7_SEG1 0
|
| 407 | #define DF_BASE__INST7_SEG2 0
|
| 408 | #define DF_BASE__INST7_SEG3 0
|
| 409 | #define DF_BASE__INST7_SEG4 0
|
| 410 | #define DF_BASE__INST7_SEG5 0
|
| 411 |
|
| 412 | #define FUSE_BASE__INST0_SEG0 0x000120A0
|
| 413 | #define FUSE_BASE__INST0_SEG1 0x00017400
|
| 414 | #define FUSE_BASE__INST0_SEG2 0x00401400
|
| 415 | #define FUSE_BASE__INST0_SEG3 0
|
| 416 | #define FUSE_BASE__INST0_SEG4 0
|
| 417 | #define FUSE_BASE__INST0_SEG5 0
|
| 418 |
|
| 419 | #define FUSE_BASE__INST1_SEG0 0
|
| 420 | #define FUSE_BASE__INST1_SEG1 0
|
| 421 | #define FUSE_BASE__INST1_SEG2 0
|
| 422 | #define FUSE_BASE__INST1_SEG3 0
|
| 423 | #define FUSE_BASE__INST1_SEG4 0
|
| 424 | #define FUSE_BASE__INST1_SEG5 0
|
| 425 |
|
| 426 | #define FUSE_BASE__INST2_SEG0 0
|
| 427 | #define FUSE_BASE__INST2_SEG1 0
|
| 428 | #define FUSE_BASE__INST2_SEG2 0
|
| 429 | #define FUSE_BASE__INST2_SEG3 0
|
| 430 | #define FUSE_BASE__INST2_SEG4 0
|
| 431 | #define FUSE_BASE__INST2_SEG5 0
|
| 432 |
|
| 433 | #define FUSE_BASE__INST3_SEG0 0
|
| 434 | #define FUSE_BASE__INST3_SEG1 0
|
| 435 | #define FUSE_BASE__INST3_SEG2 0
|
| 436 | #define FUSE_BASE__INST3_SEG3 0
|
| 437 | #define FUSE_BASE__INST3_SEG4 0
|
| 438 | #define FUSE_BASE__INST3_SEG5 0
|
| 439 |
|
| 440 | #define FUSE_BASE__INST4_SEG0 0
|
| 441 | #define FUSE_BASE__INST4_SEG1 0
|
| 442 | #define FUSE_BASE__INST4_SEG2 0
|
| 443 | #define FUSE_BASE__INST4_SEG3 0
|
| 444 | #define FUSE_BASE__INST4_SEG4 0
|
| 445 | #define FUSE_BASE__INST4_SEG5 0
|
| 446 |
|
| 447 | #define FUSE_BASE__INST5_SEG0 0
|
| 448 | #define FUSE_BASE__INST5_SEG1 0
|
| 449 | #define FUSE_BASE__INST5_SEG2 0
|
| 450 | #define FUSE_BASE__INST5_SEG3 0
|
| 451 | #define FUSE_BASE__INST5_SEG4 0
|
| 452 | #define FUSE_BASE__INST5_SEG5 0
|
| 453 |
|
| 454 | #define FUSE_BASE__INST6_SEG0 0
|
| 455 | #define FUSE_BASE__INST6_SEG1 0
|
| 456 | #define FUSE_BASE__INST6_SEG2 0
|
| 457 | #define FUSE_BASE__INST6_SEG3 0
|
| 458 | #define FUSE_BASE__INST6_SEG4 0
|
| 459 | #define FUSE_BASE__INST6_SEG5 0
|
| 460 |
|
| 461 | #define FUSE_BASE__INST7_SEG0 0
|
| 462 | #define FUSE_BASE__INST7_SEG1 0
|
| 463 | #define FUSE_BASE__INST7_SEG2 0
|
| 464 | #define FUSE_BASE__INST7_SEG3 0
|
| 465 | #define FUSE_BASE__INST7_SEG4 0
|
| 466 | #define FUSE_BASE__INST7_SEG5 0
|
| 467 |
|
| 468 | #define GC_BASE__INST0_SEG0 0x00002000
|
| 469 | #define GC_BASE__INST0_SEG1 0x0000A000
|
| 470 | #define GC_BASE__INST0_SEG2 0x00012160
|
| 471 | #define GC_BASE__INST0_SEG3 0x00402C00
|
| 472 | #define GC_BASE__INST0_SEG4 0
|
| 473 | #define GC_BASE__INST0_SEG5 0
|
| 474 |
|
| 475 | #define GC_BASE__INST1_SEG0 0
|
| 476 | #define GC_BASE__INST1_SEG1 0
|
| 477 | #define GC_BASE__INST1_SEG2 0
|
| 478 | #define GC_BASE__INST1_SEG3 0
|
| 479 | #define GC_BASE__INST1_SEG4 0
|
| 480 | #define GC_BASE__INST1_SEG5 0
|
| 481 |
|
| 482 | #define GC_BASE__INST2_SEG0 0
|
| 483 | #define GC_BASE__INST2_SEG1 0
|
| 484 | #define GC_BASE__INST2_SEG2 0
|
| 485 | #define GC_BASE__INST2_SEG3 0
|
| 486 | #define GC_BASE__INST2_SEG4 0
|
| 487 | #define GC_BASE__INST2_SEG5 0
|
| 488 |
|
| 489 | #define GC_BASE__INST3_SEG0 0
|
| 490 | #define GC_BASE__INST3_SEG1 0
|
| 491 | #define GC_BASE__INST3_SEG2 0
|
| 492 | #define GC_BASE__INST3_SEG3 0
|
| 493 | #define GC_BASE__INST3_SEG4 0
|
| 494 | #define GC_BASE__INST3_SEG5 0
|
| 495 |
|
| 496 | #define GC_BASE__INST4_SEG0 0
|
| 497 | #define GC_BASE__INST4_SEG1 0
|
| 498 | #define GC_BASE__INST4_SEG2 0
|
| 499 | #define GC_BASE__INST4_SEG3 0
|
| 500 | #define GC_BASE__INST4_SEG4 0
|
| 501 | #define GC_BASE__INST4_SEG5 0
|
| 502 |
|
| 503 | #define GC_BASE__INST5_SEG0 0
|
| 504 | #define GC_BASE__INST5_SEG1 0
|
| 505 | #define GC_BASE__INST5_SEG2 0
|
| 506 | #define GC_BASE__INST5_SEG3 0
|
| 507 | #define GC_BASE__INST5_SEG4 0
|
| 508 | #define GC_BASE__INST5_SEG5 0
|
| 509 |
|
| 510 | #define GC_BASE__INST6_SEG0 0
|
| 511 | #define GC_BASE__INST6_SEG1 0
|
| 512 | #define GC_BASE__INST6_SEG2 0
|
| 513 | #define GC_BASE__INST6_SEG3 0
|
| 514 | #define GC_BASE__INST6_SEG4 0
|
| 515 | #define GC_BASE__INST6_SEG5 0
|
| 516 |
|
| 517 | #define GC_BASE__INST7_SEG0 0
|
| 518 | #define GC_BASE__INST7_SEG1 0
|
| 519 | #define GC_BASE__INST7_SEG2 0
|
| 520 | #define GC_BASE__INST7_SEG3 0
|
| 521 | #define GC_BASE__INST7_SEG4 0
|
| 522 | #define GC_BASE__INST7_SEG5 0
|
| 523 |
|
| 524 | #define HDP_BASE__INST0_SEG0 0x00000F20
|
| 525 | #define HDP_BASE__INST0_SEG1 0x00012520
|
| 526 | #define HDP_BASE__INST0_SEG2 0x0040A400
|
| 527 | #define HDP_BASE__INST0_SEG3 0
|
| 528 | #define HDP_BASE__INST0_SEG4 0
|
| 529 | #define HDP_BASE__INST0_SEG5 0
|
| 530 |
|
| 531 | #define HDP_BASE__INST1_SEG0 0
|
| 532 | #define HDP_BASE__INST1_SEG1 0
|
| 533 | #define HDP_BASE__INST1_SEG2 0
|
| 534 | #define HDP_BASE__INST1_SEG3 0
|
| 535 | #define HDP_BASE__INST1_SEG4 0
|
| 536 | #define HDP_BASE__INST1_SEG5 0
|
| 537 |
|
| 538 | #define HDP_BASE__INST2_SEG0 0
|
| 539 | #define HDP_BASE__INST2_SEG1 0
|
| 540 | #define HDP_BASE__INST2_SEG2 0
|
| 541 | #define HDP_BASE__INST2_SEG3 0
|
| 542 | #define HDP_BASE__INST2_SEG4 0
|
| 543 | #define HDP_BASE__INST2_SEG5 0
|
| 544 |
|
| 545 | #define HDP_BASE__INST3_SEG0 0
|
| 546 | #define HDP_BASE__INST3_SEG1 0
|
| 547 | #define HDP_BASE__INST3_SEG2 0
|
| 548 | #define HDP_BASE__INST3_SEG3 0
|
| 549 | #define HDP_BASE__INST3_SEG4 0
|
| 550 | #define HDP_BASE__INST3_SEG5 0
|
| 551 |
|
| 552 | #define HDP_BASE__INST4_SEG0 0
|
| 553 | #define HDP_BASE__INST4_SEG1 0
|
| 554 | #define HDP_BASE__INST4_SEG2 0
|
| 555 | #define HDP_BASE__INST4_SEG3 0
|
| 556 | #define HDP_BASE__INST4_SEG4 0
|
| 557 | #define HDP_BASE__INST4_SEG5 0
|
| 558 |
|
| 559 | #define HDP_BASE__INST5_SEG0 0
|
| 560 | #define HDP_BASE__INST5_SEG1 0
|
| 561 | #define HDP_BASE__INST5_SEG2 0
|
| 562 | #define HDP_BASE__INST5_SEG3 0
|
| 563 | #define HDP_BASE__INST5_SEG4 0
|
| 564 | #define HDP_BASE__INST5_SEG5 0
|
| 565 |
|
| 566 | #define HDP_BASE__INST6_SEG0 0
|
| 567 | #define HDP_BASE__INST6_SEG1 0
|
| 568 | #define HDP_BASE__INST6_SEG2 0
|
| 569 | #define HDP_BASE__INST6_SEG3 0
|
| 570 | #define HDP_BASE__INST6_SEG4 0
|
| 571 | #define HDP_BASE__INST6_SEG5 0
|
| 572 |
|
| 573 | #define HDP_BASE__INST7_SEG0 0
|
| 574 | #define HDP_BASE__INST7_SEG1 0
|
| 575 | #define HDP_BASE__INST7_SEG2 0
|
| 576 | #define HDP_BASE__INST7_SEG3 0
|
| 577 | #define HDP_BASE__INST7_SEG4 0
|
| 578 | #define HDP_BASE__INST7_SEG5 0
|
| 579 |
|
| 580 | #define MMHUB_BASE__INST0_SEG0 0x00012440
|
| 581 | #define MMHUB_BASE__INST0_SEG1 0x0001A000
|
| 582 | #define MMHUB_BASE__INST0_SEG2 0x00408800
|
| 583 | #define MMHUB_BASE__INST0_SEG3 0
|
| 584 | #define MMHUB_BASE__INST0_SEG4 0
|
| 585 | #define MMHUB_BASE__INST0_SEG5 0
|
| 586 |
|
| 587 | #define MMHUB_BASE__INST1_SEG0 0
|
| 588 | #define MMHUB_BASE__INST1_SEG1 0
|
| 589 | #define MMHUB_BASE__INST1_SEG2 0
|
| 590 | #define MMHUB_BASE__INST1_SEG3 0
|
| 591 | #define MMHUB_BASE__INST1_SEG4 0
|
| 592 | #define MMHUB_BASE__INST1_SEG5 0
|
| 593 |
|
| 594 | #define MMHUB_BASE__INST2_SEG0 0
|
| 595 | #define MMHUB_BASE__INST2_SEG1 0
|
| 596 | #define MMHUB_BASE__INST2_SEG2 0
|
| 597 | #define MMHUB_BASE__INST2_SEG3 0
|
| 598 | #define MMHUB_BASE__INST2_SEG4 0
|
| 599 | #define MMHUB_BASE__INST2_SEG5 0
|
| 600 |
|
| 601 | #define MMHUB_BASE__INST3_SEG0 0
|
| 602 | #define MMHUB_BASE__INST3_SEG1 0
|
| 603 | #define MMHUB_BASE__INST3_SEG2 0
|
| 604 | #define MMHUB_BASE__INST3_SEG3 0
|
| 605 | #define MMHUB_BASE__INST3_SEG4 0
|
| 606 | #define MMHUB_BASE__INST3_SEG5 0
|
| 607 |
|
| 608 | #define MMHUB_BASE__INST4_SEG0 0
|
| 609 | #define MMHUB_BASE__INST4_SEG1 0
|
| 610 | #define MMHUB_BASE__INST4_SEG2 0
|
| 611 | #define MMHUB_BASE__INST4_SEG3 0
|
| 612 | #define MMHUB_BASE__INST4_SEG4 0
|
| 613 | #define MMHUB_BASE__INST4_SEG5 0
|
| 614 |
|
| 615 | #define MMHUB_BASE__INST5_SEG0 0
|
| 616 | #define MMHUB_BASE__INST5_SEG1 0
|
| 617 | #define MMHUB_BASE__INST5_SEG2 0
|
| 618 | #define MMHUB_BASE__INST5_SEG3 0
|
| 619 | #define MMHUB_BASE__INST5_SEG4 0
|
| 620 | #define MMHUB_BASE__INST5_SEG5 0
|
| 621 |
|
| 622 | #define MMHUB_BASE__INST6_SEG0 0
|
| 623 | #define MMHUB_BASE__INST6_SEG1 0
|
| 624 | #define MMHUB_BASE__INST6_SEG2 0
|
| 625 | #define MMHUB_BASE__INST6_SEG3 0
|
| 626 | #define MMHUB_BASE__INST6_SEG4 0
|
| 627 | #define MMHUB_BASE__INST6_SEG5 0
|
| 628 |
|
| 629 | #define MMHUB_BASE__INST7_SEG0 0
|
| 630 | #define MMHUB_BASE__INST7_SEG1 0
|
| 631 | #define MMHUB_BASE__INST7_SEG2 0
|
| 632 | #define MMHUB_BASE__INST7_SEG3 0
|
| 633 | #define MMHUB_BASE__INST7_SEG4 0
|
| 634 | #define MMHUB_BASE__INST7_SEG5 0
|
| 635 |
|
| 636 | #define MP0_BASE__INST0_SEG0 0x00013FE0
|
| 637 | #define MP0_BASE__INST0_SEG1 0x00016000
|
| 638 | #define MP0_BASE__INST0_SEG2 0x0043FC00
|
| 639 | #define MP0_BASE__INST0_SEG3 0x00DC0000
|
| 640 | #define MP0_BASE__INST0_SEG4 0x00E00000
|
| 641 | #define MP0_BASE__INST0_SEG5 0x00E40000
|
| 642 |
|
| 643 | #define MP0_BASE__INST1_SEG0 0
|
| 644 | #define MP0_BASE__INST1_SEG1 0
|
| 645 | #define MP0_BASE__INST1_SEG2 0
|
| 646 | #define MP0_BASE__INST1_SEG3 0
|
| 647 | #define MP0_BASE__INST1_SEG4 0
|
| 648 | #define MP0_BASE__INST1_SEG5 0
|
| 649 |
|
| 650 | #define MP0_BASE__INST2_SEG0 0
|
| 651 | #define MP0_BASE__INST2_SEG1 0
|
| 652 | #define MP0_BASE__INST2_SEG2 0
|
| 653 | #define MP0_BASE__INST2_SEG3 0
|
| 654 | #define MP0_BASE__INST2_SEG4 0
|
| 655 | #define MP0_BASE__INST2_SEG5 0
|
| 656 |
|
| 657 | #define MP0_BASE__INST3_SEG0 0
|
| 658 | #define MP0_BASE__INST3_SEG1 0
|
| 659 | #define MP0_BASE__INST3_SEG2 0
|
| 660 | #define MP0_BASE__INST3_SEG3 0
|
| 661 | #define MP0_BASE__INST3_SEG4 0
|
| 662 | #define MP0_BASE__INST3_SEG5 0
|
| 663 |
|
| 664 | #define MP0_BASE__INST4_SEG0 0
|
| 665 | #define MP0_BASE__INST4_SEG1 0
|
| 666 | #define MP0_BASE__INST4_SEG2 0
|
| 667 | #define MP0_BASE__INST4_SEG3 0
|
| 668 | #define MP0_BASE__INST4_SEG4 0
|
| 669 | #define MP0_BASE__INST4_SEG5 0
|
| 670 |
|
| 671 | #define MP0_BASE__INST5_SEG0 0
|
| 672 | #define MP0_BASE__INST5_SEG1 0
|
| 673 | #define MP0_BASE__INST5_SEG2 0
|
| 674 | #define MP0_BASE__INST5_SEG3 0
|
| 675 | #define MP0_BASE__INST5_SEG4 0
|
| 676 | #define MP0_BASE__INST5_SEG5 0
|
| 677 |
|
| 678 | #define MP0_BASE__INST6_SEG0 0
|
| 679 | #define MP0_BASE__INST6_SEG1 0
|
| 680 | #define MP0_BASE__INST6_SEG2 0
|
| 681 | #define MP0_BASE__INST6_SEG3 0
|
| 682 | #define MP0_BASE__INST6_SEG4 0
|
| 683 | #define MP0_BASE__INST6_SEG5 0
|
| 684 |
|
| 685 | #define MP0_BASE__INST7_SEG0 0
|
| 686 | #define MP0_BASE__INST7_SEG1 0
|
| 687 | #define MP0_BASE__INST7_SEG2 0
|
| 688 | #define MP0_BASE__INST7_SEG3 0
|
| 689 | #define MP0_BASE__INST7_SEG4 0
|
| 690 | #define MP0_BASE__INST7_SEG5 0
|
| 691 |
|
| 692 | #define MP1_BASE__INST0_SEG0 0x00012020
|
| 693 | #define MP1_BASE__INST0_SEG1 0x00016200
|
| 694 | #define MP1_BASE__INST0_SEG2 0x00400400
|
| 695 | #define MP1_BASE__INST0_SEG3 0x00E80000
|
| 696 | #define MP1_BASE__INST0_SEG4 0x00EC0000
|
| 697 | #define MP1_BASE__INST0_SEG5 0x00F00000
|
| 698 |
|
| 699 | #define MP1_BASE__INST1_SEG0 0
|
| 700 | #define MP1_BASE__INST1_SEG1 0
|
| 701 | #define MP1_BASE__INST1_SEG2 0
|
| 702 | #define MP1_BASE__INST1_SEG3 0
|
| 703 | #define MP1_BASE__INST1_SEG4 0
|
| 704 | #define MP1_BASE__INST1_SEG5 0
|
| 705 |
|
| 706 | #define MP1_BASE__INST2_SEG0 0
|
| 707 | #define MP1_BASE__INST2_SEG1 0
|
| 708 | #define MP1_BASE__INST2_SEG2 0
|
| 709 | #define MP1_BASE__INST2_SEG3 0
|
| 710 | #define MP1_BASE__INST2_SEG4 0
|
| 711 | #define MP1_BASE__INST2_SEG5 0
|
| 712 |
|
| 713 | #define MP1_BASE__INST3_SEG0 0
|
| 714 | #define MP1_BASE__INST3_SEG1 0
|
| 715 | #define MP1_BASE__INST3_SEG2 0
|
| 716 | #define MP1_BASE__INST3_SEG3 0
|
| 717 | #define MP1_BASE__INST3_SEG4 0
|
| 718 | #define MP1_BASE__INST3_SEG5 0
|
| 719 |
|
| 720 | #define MP1_BASE__INST4_SEG0 0
|
| 721 | #define MP1_BASE__INST4_SEG1 0
|
| 722 | #define MP1_BASE__INST4_SEG2 0
|
| 723 | #define MP1_BASE__INST4_SEG3 0
|
| 724 | #define MP1_BASE__INST4_SEG4 0
|
| 725 | #define MP1_BASE__INST4_SEG5 0
|
| 726 |
|
| 727 | #define MP1_BASE__INST5_SEG0 0
|
| 728 | #define MP1_BASE__INST5_SEG1 0
|
| 729 | #define MP1_BASE__INST5_SEG2 0
|
| 730 | #define MP1_BASE__INST5_SEG3 0
|
| 731 | #define MP1_BASE__INST5_SEG4 0
|
| 732 | #define MP1_BASE__INST5_SEG5 0
|
| 733 |
|
| 734 | #define MP1_BASE__INST6_SEG0 0
|
| 735 | #define MP1_BASE__INST6_SEG1 0
|
| 736 | #define MP1_BASE__INST6_SEG2 0
|
| 737 | #define MP1_BASE__INST6_SEG3 0
|
| 738 | #define MP1_BASE__INST6_SEG4 0
|
| 739 | #define MP1_BASE__INST6_SEG5 0
|
| 740 |
|
| 741 | #define MP1_BASE__INST7_SEG0 0
|
| 742 | #define MP1_BASE__INST7_SEG1 0
|
| 743 | #define MP1_BASE__INST7_SEG2 0
|
| 744 | #define MP1_BASE__INST7_SEG3 0
|
| 745 | #define MP1_BASE__INST7_SEG4 0
|
| 746 | #define MP1_BASE__INST7_SEG5 0
|
| 747 |
|
| 748 | #define NBIF0_BASE__INST0_SEG0 0x00000000
|
| 749 | #define NBIF0_BASE__INST0_SEG1 0x00000014
|
| 750 | #define NBIF0_BASE__INST0_SEG2 0x00000D20
|
| 751 | #define NBIF0_BASE__INST0_SEG3 0x00010400
|
| 752 | #define NBIF0_BASE__INST0_SEG4 0x00012D80
|
| 753 | #define NBIF0_BASE__INST0_SEG5 0x0041B000
|
| 754 |
|
| 755 | #define NBIF0_BASE__INST1_SEG0 0
|
| 756 | #define NBIF0_BASE__INST1_SEG1 0
|
| 757 | #define NBIF0_BASE__INST1_SEG2 0
|
| 758 | #define NBIF0_BASE__INST1_SEG3 0
|
| 759 | #define NBIF0_BASE__INST1_SEG4 0
|
| 760 | #define NBIF0_BASE__INST1_SEG5 0
|
| 761 |
|
| 762 | #define NBIF0_BASE__INST2_SEG0 0
|
| 763 | #define NBIF0_BASE__INST2_SEG1 0
|
| 764 | #define NBIF0_BASE__INST2_SEG2 0
|
| 765 | #define NBIF0_BASE__INST2_SEG3 0
|
| 766 | #define NBIF0_BASE__INST2_SEG4 0
|
| 767 | #define NBIF0_BASE__INST2_SEG5 0
|
| 768 |
|
| 769 | #define NBIF0_BASE__INST3_SEG0 0
|
| 770 | #define NBIF0_BASE__INST3_SEG1 0
|
| 771 | #define NBIF0_BASE__INST3_SEG2 0
|
| 772 | #define NBIF0_BASE__INST3_SEG3 0
|
| 773 | #define NBIF0_BASE__INST3_SEG4 0
|
| 774 | #define NBIF0_BASE__INST3_SEG5 0
|
| 775 |
|
| 776 | #define NBIF0_BASE__INST4_SEG0 0
|
| 777 | #define NBIF0_BASE__INST4_SEG1 0
|
| 778 | #define NBIF0_BASE__INST4_SEG2 0
|
| 779 | #define NBIF0_BASE__INST4_SEG3 0
|
| 780 | #define NBIF0_BASE__INST4_SEG4 0
|
| 781 | #define NBIF0_BASE__INST4_SEG5 0
|
| 782 |
|
| 783 | #define NBIF0_BASE__INST5_SEG0 0
|
| 784 | #define NBIF0_BASE__INST5_SEG1 0
|
| 785 | #define NBIF0_BASE__INST5_SEG2 0
|
| 786 | #define NBIF0_BASE__INST5_SEG3 0
|
| 787 | #define NBIF0_BASE__INST5_SEG4 0
|
| 788 | #define NBIF0_BASE__INST5_SEG5 0
|
| 789 |
|
| 790 | #define NBIF0_BASE__INST6_SEG0 0
|
| 791 | #define NBIF0_BASE__INST6_SEG1 0
|
| 792 | #define NBIF0_BASE__INST6_SEG2 0
|
| 793 | #define NBIF0_BASE__INST6_SEG3 0
|
| 794 | #define NBIF0_BASE__INST6_SEG4 0
|
| 795 | #define NBIF0_BASE__INST6_SEG5 0
|
| 796 |
|
| 797 | #define NBIF0_BASE__INST7_SEG0 0
|
| 798 | #define NBIF0_BASE__INST7_SEG1 0
|
| 799 | #define NBIF0_BASE__INST7_SEG2 0
|
| 800 | #define NBIF0_BASE__INST7_SEG3 0
|
| 801 | #define NBIF0_BASE__INST7_SEG4 0
|
| 802 | #define NBIF0_BASE__INST7_SEG5 0
|
| 803 |
|
| 804 | #define OSSSYS_BASE__INST0_SEG0 0x000010A0
|
| 805 | #define OSSSYS_BASE__INST0_SEG1 0x00012500
|
| 806 | #define OSSSYS_BASE__INST0_SEG2 0x0040A000
|
| 807 | #define OSSSYS_BASE__INST0_SEG3 0
|
| 808 | #define OSSSYS_BASE__INST0_SEG4 0
|
| 809 | #define OSSSYS_BASE__INST0_SEG5 0
|
| 810 |
|
| 811 | #define OSSSYS_BASE__INST1_SEG0 0
|
| 812 | #define OSSSYS_BASE__INST1_SEG1 0
|
| 813 | #define OSSSYS_BASE__INST1_SEG2 0
|
| 814 | #define OSSSYS_BASE__INST1_SEG3 0
|
| 815 | #define OSSSYS_BASE__INST1_SEG4 0
|
| 816 | #define OSSSYS_BASE__INST1_SEG5 0
|
| 817 |
|
| 818 | #define OSSSYS_BASE__INST2_SEG0 0
|
| 819 | #define OSSSYS_BASE__INST2_SEG1 0
|
| 820 | #define OSSSYS_BASE__INST2_SEG2 0
|
| 821 | #define OSSSYS_BASE__INST2_SEG3 0
|
| 822 | #define OSSSYS_BASE__INST2_SEG4 0
|
| 823 | #define OSSSYS_BASE__INST2_SEG5 0
|
| 824 |
|
| 825 | #define OSSSYS_BASE__INST3_SEG0 0
|
| 826 | #define OSSSYS_BASE__INST3_SEG1 0
|
| 827 | #define OSSSYS_BASE__INST3_SEG2 0
|
| 828 | #define OSSSYS_BASE__INST3_SEG3 0
|
| 829 | #define OSSSYS_BASE__INST3_SEG4 0
|
| 830 | #define OSSSYS_BASE__INST3_SEG5 0
|
| 831 |
|
| 832 | #define OSSSYS_BASE__INST4_SEG0 0
|
| 833 | #define OSSSYS_BASE__INST4_SEG1 0
|
| 834 | #define OSSSYS_BASE__INST4_SEG2 0
|
| 835 | #define OSSSYS_BASE__INST4_SEG3 0
|
| 836 | #define OSSSYS_BASE__INST4_SEG4 0
|
| 837 | #define OSSSYS_BASE__INST4_SEG5 0
|
| 838 |
|
| 839 | #define OSSSYS_BASE__INST5_SEG0 0
|
| 840 | #define OSSSYS_BASE__INST5_SEG1 0
|
| 841 | #define OSSSYS_BASE__INST5_SEG2 0
|
| 842 | #define OSSSYS_BASE__INST5_SEG3 0
|
| 843 | #define OSSSYS_BASE__INST5_SEG4 0
|
| 844 | #define OSSSYS_BASE__INST5_SEG5 0
|
| 845 |
|
| 846 | #define OSSSYS_BASE__INST6_SEG0 0
|
| 847 | #define OSSSYS_BASE__INST6_SEG1 0
|
| 848 | #define OSSSYS_BASE__INST6_SEG2 0
|
| 849 | #define OSSSYS_BASE__INST6_SEG3 0
|
| 850 | #define OSSSYS_BASE__INST6_SEG4 0
|
| 851 | #define OSSSYS_BASE__INST6_SEG5 0
|
| 852 |
|
| 853 | #define OSSSYS_BASE__INST7_SEG0 0
|
| 854 | #define OSSSYS_BASE__INST7_SEG1 0
|
| 855 | #define OSSSYS_BASE__INST7_SEG2 0
|
| 856 | #define OSSSYS_BASE__INST7_SEG3 0
|
| 857 | #define OSSSYS_BASE__INST7_SEG4 0
|
| 858 | #define OSSSYS_BASE__INST7_SEG5 0
|
| 859 |
|
| 860 | #define PCIE0_BASE__INST0_SEG0 0x000128C0
|
| 861 | #define PCIE0_BASE__INST0_SEG1 0x00411800
|
| 862 | #define PCIE0_BASE__INST0_SEG2 0x04440000
|
| 863 | #define PCIE0_BASE__INST0_SEG3 0
|
| 864 | #define PCIE0_BASE__INST0_SEG4 0
|
| 865 | #define PCIE0_BASE__INST0_SEG5 0
|
| 866 |
|
| 867 | #define PCIE0_BASE__INST1_SEG0 0
|
| 868 | #define PCIE0_BASE__INST1_SEG1 0
|
| 869 | #define PCIE0_BASE__INST1_SEG2 0
|
| 870 | #define PCIE0_BASE__INST1_SEG3 0
|
| 871 | #define PCIE0_BASE__INST1_SEG4 0
|
| 872 | #define PCIE0_BASE__INST1_SEG5 0
|
| 873 |
|
| 874 | #define PCIE0_BASE__INST2_SEG0 0
|
| 875 | #define PCIE0_BASE__INST2_SEG1 0
|
| 876 | #define PCIE0_BASE__INST2_SEG2 0
|
| 877 | #define PCIE0_BASE__INST2_SEG3 0
|
| 878 | #define PCIE0_BASE__INST2_SEG4 0
|
| 879 | #define PCIE0_BASE__INST2_SEG5 0
|
| 880 |
|
| 881 | #define PCIE0_BASE__INST3_SEG0 0
|
| 882 | #define PCIE0_BASE__INST3_SEG1 0
|
| 883 | #define PCIE0_BASE__INST3_SEG2 0
|
| 884 | #define PCIE0_BASE__INST3_SEG3 0
|
| 885 | #define PCIE0_BASE__INST3_SEG4 0
|
| 886 | #define PCIE0_BASE__INST3_SEG5 0
|
| 887 |
|
| 888 | #define PCIE0_BASE__INST4_SEG0 0
|
| 889 | #define PCIE0_BASE__INST4_SEG1 0
|
| 890 | #define PCIE0_BASE__INST4_SEG2 0
|
| 891 | #define PCIE0_BASE__INST4_SEG3 0
|
| 892 | #define PCIE0_BASE__INST4_SEG4 0
|
| 893 | #define PCIE0_BASE__INST4_SEG5 0
|
| 894 |
|
| 895 | #define PCIE0_BASE__INST5_SEG0 0
|
| 896 | #define PCIE0_BASE__INST5_SEG1 0
|
| 897 | #define PCIE0_BASE__INST5_SEG2 0
|
| 898 | #define PCIE0_BASE__INST5_SEG3 0
|
| 899 | #define PCIE0_BASE__INST5_SEG4 0
|
| 900 | #define PCIE0_BASE__INST5_SEG5 0
|
| 901 |
|
| 902 | #define PCIE0_BASE__INST6_SEG0 0
|
| 903 | #define PCIE0_BASE__INST6_SEG1 0
|
| 904 | #define PCIE0_BASE__INST6_SEG2 0
|
| 905 | #define PCIE0_BASE__INST6_SEG3 0
|
| 906 | #define PCIE0_BASE__INST6_SEG4 0
|
| 907 | #define PCIE0_BASE__INST6_SEG5 0
|
| 908 |
|
| 909 | #define PCIE0_BASE__INST7_SEG0 0
|
| 910 | #define PCIE0_BASE__INST7_SEG1 0
|
| 911 | #define PCIE0_BASE__INST7_SEG2 0
|
| 912 | #define PCIE0_BASE__INST7_SEG3 0
|
| 913 | #define PCIE0_BASE__INST7_SEG4 0
|
| 914 | #define PCIE0_BASE__INST7_SEG5 0
|
| 915 |
|
| 916 | #define SDMA0_BASE__INST0_SEG0 0x00001260
|
| 917 | #define SDMA0_BASE__INST0_SEG1 0x00012540
|
| 918 | #define SDMA0_BASE__INST0_SEG2 0x0040A800
|
| 919 | #define SDMA0_BASE__INST0_SEG3 0
|
| 920 | #define SDMA0_BASE__INST0_SEG4 0
|
| 921 | #define SDMA0_BASE__INST0_SEG5 0
|
| 922 |
|
| 923 | #define SDMA0_BASE__INST1_SEG0 0
|
| 924 | #define SDMA0_BASE__INST1_SEG1 0
|
| 925 | #define SDMA0_BASE__INST1_SEG2 0
|
| 926 | #define SDMA0_BASE__INST1_SEG3 0
|
| 927 | #define SDMA0_BASE__INST1_SEG4 0
|
| 928 | #define SDMA0_BASE__INST1_SEG5 0
|
| 929 |
|
| 930 | #define SDMA0_BASE__INST2_SEG0 0
|
| 931 | #define SDMA0_BASE__INST2_SEG1 0
|
| 932 | #define SDMA0_BASE__INST2_SEG2 0
|
| 933 | #define SDMA0_BASE__INST2_SEG3 0
|
| 934 | #define SDMA0_BASE__INST2_SEG4 0
|
| 935 | #define SDMA0_BASE__INST2_SEG5 0
|
| 936 |
|
| 937 | #define SDMA0_BASE__INST3_SEG0 0
|
| 938 | #define SDMA0_BASE__INST3_SEG1 0
|
| 939 | #define SDMA0_BASE__INST3_SEG2 0
|
| 940 | #define SDMA0_BASE__INST3_SEG3 0
|
| 941 | #define SDMA0_BASE__INST3_SEG4 0
|
| 942 | #define SDMA0_BASE__INST3_SEG5 0
|
| 943 |
|
| 944 | #define SDMA0_BASE__INST4_SEG0 0
|
| 945 | #define SDMA0_BASE__INST4_SEG1 0
|
| 946 | #define SDMA0_BASE__INST4_SEG2 0
|
| 947 | #define SDMA0_BASE__INST4_SEG3 0
|
| 948 | #define SDMA0_BASE__INST4_SEG4 0
|
| 949 | #define SDMA0_BASE__INST4_SEG5 0
|
| 950 |
|
| 951 | #define SDMA0_BASE__INST5_SEG0 0
|
| 952 | #define SDMA0_BASE__INST5_SEG1 0
|
| 953 | #define SDMA0_BASE__INST5_SEG2 0
|
| 954 | #define SDMA0_BASE__INST5_SEG3 0
|
| 955 | #define SDMA0_BASE__INST5_SEG4 0
|
| 956 | #define SDMA0_BASE__INST5_SEG5 0
|
| 957 |
|
| 958 | #define SDMA0_BASE__INST6_SEG0 0
|
| 959 | #define SDMA0_BASE__INST6_SEG1 0
|
| 960 | #define SDMA0_BASE__INST6_SEG2 0
|
| 961 | #define SDMA0_BASE__INST6_SEG3 0
|
| 962 | #define SDMA0_BASE__INST6_SEG4 0
|
| 963 | #define SDMA0_BASE__INST6_SEG5 0
|
| 964 |
|
| 965 | #define SDMA1_BASE__INST0_SEG0 0x00001860
|
| 966 | #define SDMA1_BASE__INST0_SEG1 0x00012560
|
| 967 | #define SDMA1_BASE__INST0_SEG2 0x0040AC00
|
| 968 | #define SDMA1_BASE__INST0_SEG3 0
|
| 969 | #define SDMA1_BASE__INST0_SEG4 0
|
| 970 | #define SDMA1_BASE__INST0_SEG5 0
|
| 971 |
|
| 972 | #define SDMA1_BASE__INST1_SEG0 0
|
| 973 | #define SDMA1_BASE__INST1_SEG1 0
|
| 974 | #define SDMA1_BASE__INST1_SEG2 0
|
| 975 | #define SDMA1_BASE__INST1_SEG3 0
|
| 976 | #define SDMA1_BASE__INST1_SEG4 0
|
| 977 | #define SDMA1_BASE__INST1_SEG5 0
|
| 978 |
|
| 979 | #define SDMA1_BASE__INST2_SEG0 0
|
| 980 | #define SDMA1_BASE__INST2_SEG1 0
|
| 981 | #define SDMA1_BASE__INST2_SEG2 0
|
| 982 | #define SDMA1_BASE__INST2_SEG3 0
|
| 983 | #define SDMA1_BASE__INST2_SEG4 0
|
| 984 | #define SDMA1_BASE__INST2_SEG5 0
|
| 985 |
|
| 986 | #define SDMA1_BASE__INST3_SEG0 0
|
| 987 | #define SDMA1_BASE__INST3_SEG1 0
|
| 988 | #define SDMA1_BASE__INST3_SEG2 0
|
| 989 | #define SDMA1_BASE__INST3_SEG3 0
|
| 990 | #define SDMA1_BASE__INST3_SEG4 0
|
| 991 | #define SDMA1_BASE__INST3_SEG5 0
|
| 992 |
|
| 993 | #define SDMA1_BASE__INST4_SEG0 0
|
| 994 | #define SDMA1_BASE__INST4_SEG1 0
|
| 995 | #define SDMA1_BASE__INST4_SEG2 0
|
| 996 | #define SDMA1_BASE__INST4_SEG3 0
|
| 997 | #define SDMA1_BASE__INST4_SEG4 0
|
| 998 | #define SDMA1_BASE__INST4_SEG5 0
|
| 999 |
|
| 1000 | #define SDMA1_BASE__INST5_SEG0 0
|
| 1001 | #define SDMA1_BASE__INST5_SEG1 0
|
| 1002 | #define SDMA1_BASE__INST5_SEG2 0
|
| 1003 | #define SDMA1_BASE__INST5_SEG3 0
|
| 1004 | #define SDMA1_BASE__INST5_SEG4 0
|
| 1005 | #define SDMA1_BASE__INST5_SEG5 0
|
| 1006 |
|
| 1007 |
|
| 1008 | #define SDMA1_BASE__INST6_SEG0 0
|
| 1009 | #define SDMA1_BASE__INST6_SEG1 0
|
| 1010 | #define SDMA1_BASE__INST6_SEG2 0
|
| 1011 | #define SDMA1_BASE__INST6_SEG3 0
|
| 1012 | #define SDMA1_BASE__INST6_SEG4 0
|
| 1013 | #define SDMA1_BASE__INST6_SEG5 0
|
| 1014 |
|
| 1015 |
|
| 1016 | #define SDMA2_BASE__INST0_SEG0 0x00013760
|
| 1017 | #define SDMA2_BASE__INST0_SEG1 0x0001E000
|
| 1018 | #define SDMA2_BASE__INST0_SEG2 0x0042EC00
|
| 1019 | #define SDMA2_BASE__INST0_SEG3 0
|
| 1020 | #define SDMA2_BASE__INST0_SEG4 0
|
| 1021 | #define SDMA2_BASE__INST0_SEG5 0
|
| 1022 |
|
| 1023 |
|
| 1024 | #define SDMA2_BASE__INST1_SEG0 0
|
| 1025 | #define SDMA2_BASE__INST1_SEG1 0
|
| 1026 | #define SDMA2_BASE__INST1_SEG2 0
|
| 1027 | #define SDMA2_BASE__INST1_SEG3 0
|
| 1028 | #define SDMA2_BASE__INST1_SEG4 0
|
| 1029 | #define SDMA2_BASE__INST1_SEG5 0
|
| 1030 |
|
| 1031 | #define SDMA2_BASE__INST2_SEG0 0
|
| 1032 | #define SDMA2_BASE__INST2_SEG1 0
|
| 1033 | #define SDMA2_BASE__INST2_SEG2 0
|
| 1034 | #define SDMA2_BASE__INST2_SEG3 0
|
| 1035 | #define SDMA2_BASE__INST2_SEG4 0
|
| 1036 | #define SDMA2_BASE__INST2_SEG5 0
|
| 1037 |
|
| 1038 | #define SDMA2_BASE__INST3_SEG0 0
|
| 1039 | #define SDMA2_BASE__INST3_SEG1 0
|
| 1040 | #define SDMA2_BASE__INST3_SEG2 0
|
| 1041 | #define SDMA2_BASE__INST3_SEG3 0
|
| 1042 | #define SDMA2_BASE__INST3_SEG4 0
|
| 1043 | #define SDMA2_BASE__INST3_SEG5 0
|
| 1044 |
|
| 1045 | #define SDMA2_BASE__INST4_SEG0 0
|
| 1046 | #define SDMA2_BASE__INST4_SEG1 0
|
| 1047 | #define SDMA2_BASE__INST4_SEG2 0
|
| 1048 | #define SDMA2_BASE__INST4_SEG3 0
|
| 1049 | #define SDMA2_BASE__INST4_SEG4 0
|
| 1050 | #define SDMA2_BASE__INST4_SEG5 0
|
| 1051 |
|
| 1052 | #define SDMA2_BASE__INST5_SEG0 0
|
| 1053 | #define SDMA2_BASE__INST5_SEG1 0
|
| 1054 | #define SDMA2_BASE__INST5_SEG2 0
|
| 1055 | #define SDMA2_BASE__INST5_SEG3 0
|
| 1056 | #define SDMA2_BASE__INST5_SEG4 0
|
| 1057 | #define SDMA2_BASE__INST5_SEG5 0
|
| 1058 |
|
| 1059 | #define SDMA2_BASE__INST6_SEG0 0
|
| 1060 | #define SDMA2_BASE__INST6_SEG1 0
|
| 1061 | #define SDMA2_BASE__INST6_SEG2 0
|
| 1062 | #define SDMA2_BASE__INST6_SEG3 0
|
| 1063 | #define SDMA2_BASE__INST6_SEG4 0
|
| 1064 | #define SDMA2_BASE__INST6_SEG5 0
|
| 1065 |
|
| 1066 | #define SDMA3_BASE__INST0_SEG0 0x00013780
|
| 1067 | #define SDMA3_BASE__INST0_SEG1 0x0001E400
|
| 1068 | #define SDMA3_BASE__INST0_SEG2 0x0042F000
|
| 1069 | #define SDMA3_BASE__INST0_SEG3 0
|
| 1070 | #define SDMA3_BASE__INST0_SEG4 0
|
| 1071 | #define SDMA3_BASE__INST0_SEG5 0
|
| 1072 |
|
| 1073 | #define SDMA3_BASE__INST1_SEG0 0
|
| 1074 | #define SDMA3_BASE__INST1_SEG1 0
|
| 1075 | #define SDMA3_BASE__INST1_SEG2 0
|
| 1076 | #define SDMA3_BASE__INST1_SEG3 0
|
| 1077 | #define SDMA3_BASE__INST1_SEG4 0
|
| 1078 | #define SDMA3_BASE__INST1_SEG5 0
|
| 1079 |
|
| 1080 | #define SDMA3_BASE__INST2_SEG0 0
|
| 1081 | #define SDMA3_BASE__INST2_SEG1 0
|
| 1082 | #define SDMA3_BASE__INST2_SEG2 0
|
| 1083 | #define SDMA3_BASE__INST2_SEG3 0
|
| 1084 | #define SDMA3_BASE__INST2_SEG4 0
|
| 1085 | #define SDMA3_BASE__INST2_SEG5 0
|
| 1086 |
|
| 1087 | #define SDMA3_BASE__INST3_SEG0 0
|
| 1088 | #define SDMA3_BASE__INST3_SEG1 0
|
| 1089 | #define SDMA3_BASE__INST3_SEG2 0
|
| 1090 | #define SDMA3_BASE__INST3_SEG3 0
|
| 1091 | #define SDMA3_BASE__INST3_SEG4 0
|
| 1092 | #define SDMA3_BASE__INST3_SEG5 0
|
| 1093 |
|
| 1094 | #define SDMA3_BASE__INST4_SEG0 0
|
| 1095 | #define SDMA3_BASE__INST4_SEG1 0
|
| 1096 | #define SDMA3_BASE__INST4_SEG2 0
|
| 1097 | #define SDMA3_BASE__INST4_SEG3 0
|
| 1098 | #define SDMA3_BASE__INST4_SEG4 0
|
| 1099 | #define SDMA3_BASE__INST4_SEG5 0
|
| 1100 |
|
| 1101 | #define SDMA3_BASE__INST5_SEG0 0
|
| 1102 | #define SDMA3_BASE__INST5_SEG1 0
|
| 1103 | #define SDMA3_BASE__INST5_SEG2 0
|
| 1104 | #define SDMA3_BASE__INST5_SEG3 0
|
| 1105 | #define SDMA3_BASE__INST5_SEG4 0
|
| 1106 | #define SDMA3_BASE__INST5_SEG5 0
|
| 1107 |
|
| 1108 | #define SDMA3_BASE__INST6_SEG0 0
|
| 1109 | #define SDMA3_BASE__INST6_SEG1 0
|
| 1110 | #define SDMA3_BASE__INST6_SEG2 0
|
| 1111 | #define SDMA3_BASE__INST6_SEG3 0
|
| 1112 | #define SDMA3_BASE__INST6_SEG4 0
|
| 1113 | #define SDMA3_BASE__INST6_SEG5 0
|
| 1114 |
|
| 1115 | #define SDMA4_BASE__INST0_SEG0 0x000137A0
|
| 1116 | #define SDMA4_BASE__INST0_SEG1 0x0001E800
|
| 1117 | #define SDMA4_BASE__INST0_SEG2 0x0042F400
|
| 1118 | #define SDMA4_BASE__INST0_SEG3 0
|
| 1119 | #define SDMA4_BASE__INST0_SEG4 0
|
| 1120 | #define SDMA4_BASE__INST0_SEG5 0
|
| 1121 |
|
| 1122 | #define SDMA4_BASE__INST1_SEG0 0
|
| 1123 | #define SDMA4_BASE__INST1_SEG1 0
|
| 1124 | #define SDMA4_BASE__INST1_SEG2 0
|
| 1125 | #define SDMA4_BASE__INST1_SEG3 0
|
| 1126 | #define SDMA4_BASE__INST1_SEG4 0
|
| 1127 | #define SDMA4_BASE__INST1_SEG5 0
|
| 1128 |
|
| 1129 | #define SDMA4_BASE__INST2_SEG0 0
|
| 1130 | #define SDMA4_BASE__INST2_SEG1 0
|
| 1131 | #define SDMA4_BASE__INST2_SEG2 0
|
| 1132 | #define SDMA4_BASE__INST2_SEG3 0
|
| 1133 | #define SDMA4_BASE__INST2_SEG4 0
|
| 1134 | #define SDMA4_BASE__INST2_SEG5 0
|
| 1135 |
|
| 1136 | #define SDMA4_BASE__INST3_SEG0 0
|
| 1137 | #define SDMA4_BASE__INST3_SEG1 0
|
| 1138 | #define SDMA4_BASE__INST3_SEG2 0
|
| 1139 | #define SDMA4_BASE__INST3_SEG3 0
|
| 1140 | #define SDMA4_BASE__INST3_SEG4 0
|
| 1141 | #define SDMA4_BASE__INST3_SEG5 0
|
| 1142 |
|
| 1143 | #define SDMA4_BASE__INST4_SEG0 0
|
| 1144 | #define SDMA4_BASE__INST4_SEG1 0
|
| 1145 | #define SDMA4_BASE__INST4_SEG2 0
|
| 1146 | #define SDMA4_BASE__INST4_SEG3 0
|
| 1147 | #define SDMA4_BASE__INST4_SEG4 0
|
| 1148 | #define SDMA4_BASE__INST4_SEG5 0
|
| 1149 |
|
| 1150 | #define SDMA4_BASE__INST5_SEG0 0
|
| 1151 | #define SDMA4_BASE__INST5_SEG1 0
|
| 1152 | #define SDMA4_BASE__INST5_SEG2 0
|
| 1153 | #define SDMA4_BASE__INST5_SEG3 0
|
| 1154 | #define SDMA4_BASE__INST5_SEG4 0
|
| 1155 | #define SDMA4_BASE__INST5_SEG5 0
|
| 1156 |
|
| 1157 | #define SDMA4_BASE__INST6_SEG0 0
|
| 1158 | #define SDMA4_BASE__INST6_SEG1 0
|
| 1159 | #define SDMA4_BASE__INST6_SEG2 0
|
| 1160 | #define SDMA4_BASE__INST6_SEG3 0
|
| 1161 | #define SDMA4_BASE__INST6_SEG4 0
|
| 1162 | #define SDMA4_BASE__INST6_SEG5 0
|
| 1163 |
|
| 1164 | #define SDMA5_BASE__INST0_SEG0 0x000137C0
|
| 1165 | #define SDMA5_BASE__INST0_SEG1 0x0001EC00
|
| 1166 | #define SDMA5_BASE__INST0_SEG2 0x0042F800
|
| 1167 | #define SDMA5_BASE__INST0_SEG3 0
|
| 1168 | #define SDMA5_BASE__INST0_SEG4 0
|
| 1169 | #define SDMA5_BASE__INST0_SEG5 0
|
| 1170 |
|
| 1171 | #define SDMA5_BASE__INST1_SEG0 0
|
| 1172 | #define SDMA5_BASE__INST1_SEG1 0
|
| 1173 | #define SDMA5_BASE__INST1_SEG2 0
|
| 1174 | #define SDMA5_BASE__INST1_SEG3 0
|
| 1175 | #define SDMA5_BASE__INST1_SEG4 0
|
| 1176 | #define SDMA5_BASE__INST1_SEG5 0
|
| 1177 |
|
| 1178 | #define SDMA5_BASE__INST2_SEG0 0
|
| 1179 | #define SDMA5_BASE__INST2_SEG1 0
|
| 1180 | #define SDMA5_BASE__INST2_SEG2 0
|
| 1181 | #define SDMA5_BASE__INST2_SEG3 0
|
| 1182 | #define SDMA5_BASE__INST2_SEG4 0
|
| 1183 | #define SDMA5_BASE__INST2_SEG5 0
|
| 1184 |
|
| 1185 | #define SDMA5_BASE__INST3_SEG0 0
|
| 1186 | #define SDMA5_BASE__INST3_SEG1 0
|
| 1187 | #define SDMA5_BASE__INST3_SEG2 0
|
| 1188 | #define SDMA5_BASE__INST3_SEG3 0
|
| 1189 | #define SDMA5_BASE__INST3_SEG4 0
|
| 1190 | #define SDMA5_BASE__INST3_SEG5 0
|
| 1191 |
|
| 1192 | #define SDMA5_BASE__INST4_SEG0 0
|
| 1193 | #define SDMA5_BASE__INST4_SEG1 0
|
| 1194 | #define SDMA5_BASE__INST4_SEG2 0
|
| 1195 | #define SDMA5_BASE__INST4_SEG3 0
|
| 1196 | #define SDMA5_BASE__INST4_SEG4 0
|
| 1197 | #define SDMA5_BASE__INST4_SEG5 0
|
| 1198 |
|
| 1199 | #define SDMA5_BASE__INST5_SEG0 0
|
| 1200 | #define SDMA5_BASE__INST5_SEG1 0
|
| 1201 | #define SDMA5_BASE__INST5_SEG2 0
|
| 1202 | #define SDMA5_BASE__INST5_SEG3 0
|
| 1203 | #define SDMA5_BASE__INST5_SEG4 0
|
| 1204 | #define SDMA5_BASE__INST5_SEG5 0
|
| 1205 |
|
| 1206 | #define SDMA5_BASE__INST6_SEG0 0
|
| 1207 | #define SDMA5_BASE__INST6_SEG1 0
|
| 1208 | #define SDMA5_BASE__INST6_SEG2 0
|
| 1209 | #define SDMA5_BASE__INST6_SEG3 0
|
| 1210 | #define SDMA5_BASE__INST6_SEG4 0
|
| 1211 | #define SDMA5_BASE__INST6_SEG5 0
|
| 1212 |
|
| 1213 | #define SDMA6_BASE__INST0_SEG0 0x000137E0
|
| 1214 | #define SDMA6_BASE__INST0_SEG1 0x0001F000
|
| 1215 | #define SDMA6_BASE__INST0_SEG2 0x0042FC00
|
| 1216 | #define SDMA6_BASE__INST0_SEG3 0
|
| 1217 | #define SDMA6_BASE__INST0_SEG4 0
|
| 1218 | #define SDMA6_BASE__INST0_SEG5 0
|
| 1219 |
|
| 1220 | #define SDMA6_BASE__INST1_SEG0 0
|
| 1221 | #define SDMA6_BASE__INST1_SEG1 0
|
| 1222 | #define SDMA6_BASE__INST1_SEG2 0
|
| 1223 | #define SDMA6_BASE__INST1_SEG3 0
|
| 1224 | #define SDMA6_BASE__INST1_SEG4 0
|
| 1225 | #define SDMA6_BASE__INST1_SEG5 0
|
| 1226 |
|
| 1227 | #define SDMA6_BASE__INST2_SEG0 0
|
| 1228 | #define SDMA6_BASE__INST2_SEG1 0
|
| 1229 | #define SDMA6_BASE__INST2_SEG2 0
|
| 1230 | #define SDMA6_BASE__INST2_SEG3 0
|
| 1231 | #define SDMA6_BASE__INST2_SEG4 0
|
| 1232 | #define SDMA6_BASE__INST2_SEG5 0
|
| 1233 |
|
| 1234 | #define SDMA6_BASE__INST3_SEG0 0
|
| 1235 | #define SDMA6_BASE__INST3_SEG1 0
|
| 1236 | #define SDMA6_BASE__INST3_SEG2 0
|
| 1237 | #define SDMA6_BASE__INST3_SEG3 0
|
| 1238 | #define SDMA6_BASE__INST3_SEG4 0
|
| 1239 | #define SDMA6_BASE__INST3_SEG5 0
|
| 1240 |
|
| 1241 | #define SDMA6_BASE__INST4_SEG0 0
|
| 1242 | #define SDMA6_BASE__INST4_SEG1 0
|
| 1243 | #define SDMA6_BASE__INST4_SEG2 0
|
| 1244 | #define SDMA6_BASE__INST4_SEG3 0
|
| 1245 | #define SDMA6_BASE__INST4_SEG4 0
|
| 1246 | #define SDMA6_BASE__INST4_SEG5 0
|
| 1247 |
|
| 1248 | #define SDMA6_BASE__INST5_SEG0 0
|
| 1249 | #define SDMA6_BASE__INST5_SEG1 0
|
| 1250 | #define SDMA6_BASE__INST5_SEG2 0
|
| 1251 | #define SDMA6_BASE__INST5_SEG3 0
|
| 1252 | #define SDMA6_BASE__INST5_SEG4 0
|
| 1253 | #define SDMA6_BASE__INST5_SEG5 0
|
| 1254 |
|
| 1255 | #define SDMA6_BASE__INST6_SEG0 0
|
| 1256 | #define SDMA6_BASE__INST6_SEG1 0
|
| 1257 | #define SDMA6_BASE__INST6_SEG2 0
|
| 1258 | #define SDMA6_BASE__INST6_SEG3 0
|
| 1259 | #define SDMA6_BASE__INST6_SEG4 0
|
| 1260 | #define SDMA6_BASE__INST6_SEG5 0
|
| 1261 |
|
| 1262 | #define SDMA7_BASE__INST0_SEG0 0x00013800
|
| 1263 | #define SDMA7_BASE__INST0_SEG1 0x0001F400
|
| 1264 | #define SDMA7_BASE__INST0_SEG2 0x00430000
|
| 1265 | #define SDMA7_BASE__INST0_SEG3 0
|
| 1266 | #define SDMA7_BASE__INST0_SEG4 0
|
| 1267 | #define SDMA7_BASE__INST0_SEG5 0
|
| 1268 |
|
| 1269 | #define SDMA7_BASE__INST1_SEG0 0
|
| 1270 | #define SDMA7_BASE__INST1_SEG1 0
|
| 1271 | #define SDMA7_BASE__INST1_SEG2 0
|
| 1272 | #define SDMA7_BASE__INST1_SEG3 0
|
| 1273 | #define SDMA7_BASE__INST1_SEG4 0
|
| 1274 | #define SDMA7_BASE__INST1_SEG5 0
|
| 1275 |
|
| 1276 | #define SDMA7_BASE__INST2_SEG0 0
|
| 1277 | #define SDMA7_BASE__INST2_SEG1 0
|
| 1278 | #define SDMA7_BASE__INST2_SEG2 0
|
| 1279 | #define SDMA7_BASE__INST2_SEG3 0
|
| 1280 | #define SDMA7_BASE__INST2_SEG4 0
|
| 1281 | #define SDMA7_BASE__INST2_SEG5 0
|
| 1282 |
|
| 1283 | #define SDMA7_BASE__INST3_SEG0 0
|
| 1284 | #define SDMA7_BASE__INST3_SEG1 0
|
| 1285 | #define SDMA7_BASE__INST3_SEG2 0
|
| 1286 | #define SDMA7_BASE__INST3_SEG3 0
|
| 1287 | #define SDMA7_BASE__INST3_SEG4 0
|
| 1288 | #define SDMA7_BASE__INST3_SEG5 0
|
| 1289 |
|
| 1290 | #define SDMA7_BASE__INST4_SEG0 0
|
| 1291 | #define SDMA7_BASE__INST4_SEG1 0
|
| 1292 | #define SDMA7_BASE__INST4_SEG2 0
|
| 1293 | #define SDMA7_BASE__INST4_SEG3 0
|
| 1294 | #define SDMA7_BASE__INST4_SEG4 0
|
| 1295 | #define SDMA7_BASE__INST4_SEG5 0
|
| 1296 |
|
| 1297 | #define SDMA7_BASE__INST5_SEG0 0
|
| 1298 | #define SDMA7_BASE__INST5_SEG1 0
|
| 1299 | #define SDMA7_BASE__INST5_SEG2 0
|
| 1300 | #define SDMA7_BASE__INST5_SEG3 0
|
| 1301 | #define SDMA7_BASE__INST5_SEG4 0
|
| 1302 | #define SDMA7_BASE__INST5_SEG5 0
|
| 1303 |
|
| 1304 | #define SDMA7_BASE__INST6_SEG0 0
|
| 1305 | #define SDMA7_BASE__INST6_SEG1 0
|
| 1306 | #define SDMA7_BASE__INST6_SEG2 0
|
| 1307 | #define SDMA7_BASE__INST6_SEG3 0
|
| 1308 | #define SDMA7_BASE__INST6_SEG4 0
|
| 1309 | #define SDMA7_BASE__INST6_SEG5 0
|
| 1310 |
|
| 1311 | #define SMUIO_BASE__INST0_SEG0 0x00012080
|
| 1312 | #define SMUIO_BASE__INST0_SEG1 0x00016800
|
| 1313 | #define SMUIO_BASE__INST0_SEG2 0x00016A00
|
| 1314 | #define SMUIO_BASE__INST0_SEG3 0x00401000
|
| 1315 | #define SMUIO_BASE__INST0_SEG4 0x00440000
|
| 1316 | #define SMUIO_BASE__INST0_SEG5 0
|
| 1317 |
|
| 1318 | #define SMUIO_BASE__INST1_SEG0 0
|
| 1319 | #define SMUIO_BASE__INST1_SEG1 0
|
| 1320 | #define SMUIO_BASE__INST1_SEG2 0
|
| 1321 | #define SMUIO_BASE__INST1_SEG3 0
|
| 1322 | #define SMUIO_BASE__INST1_SEG4 0
|
| 1323 | #define SMUIO_BASE__INST1_SEG5 0
|
| 1324 |
|
| 1325 | #define SMUIO_BASE__INST2_SEG0 0
|
| 1326 | #define SMUIO_BASE__INST2_SEG1 0
|
| 1327 | #define SMUIO_BASE__INST2_SEG2 0
|
| 1328 | #define SMUIO_BASE__INST2_SEG3 0
|
| 1329 | #define SMUIO_BASE__INST2_SEG4 0
|
| 1330 | #define SMUIO_BASE__INST2_SEG5 0
|
| 1331 |
|
| 1332 | #define SMUIO_BASE__INST3_SEG0 0
|
| 1333 | #define SMUIO_BASE__INST3_SEG1 0
|
| 1334 | #define SMUIO_BASE__INST3_SEG2 0
|
| 1335 | #define SMUIO_BASE__INST3_SEG3 0
|
| 1336 | #define SMUIO_BASE__INST3_SEG4 0
|
| 1337 | #define SMUIO_BASE__INST3_SEG5 0
|
| 1338 |
|
| 1339 | #define SMUIO_BASE__INST4_SEG0 0
|
| 1340 | #define SMUIO_BASE__INST4_SEG1 0
|
| 1341 | #define SMUIO_BASE__INST4_SEG2 0
|
| 1342 | #define SMUIO_BASE__INST4_SEG3 0
|
| 1343 | #define SMUIO_BASE__INST4_SEG4 0
|
| 1344 | #define SMUIO_BASE__INST4_SEG5 0
|
| 1345 |
|
| 1346 | #define SMUIO_BASE__INST5_SEG0 0
|
| 1347 | #define SMUIO_BASE__INST5_SEG1 0
|
| 1348 | #define SMUIO_BASE__INST5_SEG2 0
|
| 1349 | #define SMUIO_BASE__INST5_SEG3 0
|
| 1350 | #define SMUIO_BASE__INST5_SEG4 0
|
| 1351 | #define SMUIO_BASE__INST5_SEG5 0
|
| 1352 |
|
| 1353 | #define SMUIO_BASE__INST6_SEG0 0
|
| 1354 | #define SMUIO_BASE__INST6_SEG1 0
|
| 1355 | #define SMUIO_BASE__INST6_SEG2 0
|
| 1356 | #define SMUIO_BASE__INST6_SEG3 0
|
| 1357 | #define SMUIO_BASE__INST6_SEG4 0
|
| 1358 | #define SMUIO_BASE__INST6_SEG5 0
|
| 1359 |
|
| 1360 | #define SMUIO_BASE__INST7_SEG0 0
|
| 1361 | #define SMUIO_BASE__INST7_SEG1 0
|
| 1362 | #define SMUIO_BASE__INST7_SEG2 0
|
| 1363 | #define SMUIO_BASE__INST7_SEG3 0
|
| 1364 | #define SMUIO_BASE__INST7_SEG4 0
|
| 1365 | #define SMUIO_BASE__INST7_SEG5 0
|
| 1366 |
|
| 1367 | #define THM_BASE__INST0_SEG0 0x00012060
|
| 1368 | #define THM_BASE__INST0_SEG1 0x00016600
|
| 1369 | #define THM_BASE__INST0_SEG2 0x00400C00
|
| 1370 | #define THM_BASE__INST0_SEG3 0
|
| 1371 | #define THM_BASE__INST0_SEG4 0
|
| 1372 | #define THM_BASE__INST0_SEG5 0
|
| 1373 |
|
| 1374 | #define THM_BASE__INST1_SEG0 0
|
| 1375 | #define THM_BASE__INST1_SEG1 0
|
| 1376 | #define THM_BASE__INST1_SEG2 0
|
| 1377 | #define THM_BASE__INST1_SEG3 0
|
| 1378 | #define THM_BASE__INST1_SEG4 0
|
| 1379 | #define THM_BASE__INST1_SEG5 0
|
| 1380 |
|
| 1381 | #define THM_BASE__INST2_SEG0 0
|
| 1382 | #define THM_BASE__INST2_SEG1 0
|
| 1383 | #define THM_BASE__INST2_SEG2 0
|
| 1384 | #define THM_BASE__INST2_SEG3 0
|
| 1385 | #define THM_BASE__INST2_SEG4 0
|
| 1386 | #define THM_BASE__INST2_SEG5 0
|
| 1387 |
|
| 1388 | #define THM_BASE__INST3_SEG0 0
|
| 1389 | #define THM_BASE__INST3_SEG1 0
|
| 1390 | #define THM_BASE__INST3_SEG2 0
|
| 1391 | #define THM_BASE__INST3_SEG3 0
|
| 1392 | #define THM_BASE__INST3_SEG4 0
|
| 1393 | #define THM_BASE__INST3_SEG5 0
|
| 1394 |
|
| 1395 | #define THM_BASE__INST4_SEG0 0
|
| 1396 | #define THM_BASE__INST4_SEG1 0
|
| 1397 | #define THM_BASE__INST4_SEG2 0
|
| 1398 | #define THM_BASE__INST4_SEG3 0
|
| 1399 | #define THM_BASE__INST4_SEG4 0
|
| 1400 | #define THM_BASE__INST4_SEG5 0
|
| 1401 |
|
| 1402 | #define THM_BASE__INST5_SEG0 0
|
| 1403 | #define THM_BASE__INST5_SEG1 0
|
| 1404 | #define THM_BASE__INST5_SEG2 0
|
| 1405 | #define THM_BASE__INST5_SEG3 0
|
| 1406 | #define THM_BASE__INST5_SEG4 0
|
| 1407 | #define THM_BASE__INST5_SEG5 0
|
| 1408 |
|
| 1409 | #define THM_BASE__INST6_SEG0 0
|
| 1410 | #define THM_BASE__INST6_SEG1 0
|
| 1411 | #define THM_BASE__INST6_SEG2 0
|
| 1412 | #define THM_BASE__INST6_SEG3 0
|
| 1413 | #define THM_BASE__INST6_SEG4 0
|
| 1414 | #define THM_BASE__INST6_SEG5 0
|
| 1415 |
|
| 1416 | #define THM_BASE__INST7_SEG0 0
|
| 1417 | #define THM_BASE__INST7_SEG1 0
|
| 1418 | #define THM_BASE__INST7_SEG2 0
|
| 1419 | #define THM_BASE__INST7_SEG3 0
|
| 1420 | #define THM_BASE__INST7_SEG4 0
|
| 1421 | #define THM_BASE__INST7_SEG5 0
|
| 1422 |
|
| 1423 | #define UMC_BASE__INST0_SEG0 0x000132C0
|
| 1424 | #define UMC_BASE__INST0_SEG1 0x00014000
|
| 1425 | #define UMC_BASE__INST0_SEG2 0x00425800
|
| 1426 | #define UMC_BASE__INST0_SEG3 0
|
| 1427 | #define UMC_BASE__INST0_SEG4 0
|
| 1428 | #define UMC_BASE__INST0_SEG5 0
|
| 1429 |
|
| 1430 | #define UMC_BASE__INST1_SEG0 0x000132E0
|
| 1431 | #define UMC_BASE__INST1_SEG1 0x00054000
|
| 1432 | #define UMC_BASE__INST1_SEG2 0x00425C00
|
| 1433 | #define UMC_BASE__INST1_SEG3 0
|
| 1434 | #define UMC_BASE__INST1_SEG4 0
|
| 1435 | #define UMC_BASE__INST1_SEG5 0
|
| 1436 |
|
| 1437 | #define UMC_BASE__INST2_SEG0 0x00013300
|
| 1438 | #define UMC_BASE__INST2_SEG1 0x00094000
|
| 1439 | #define UMC_BASE__INST2_SEG2 0x00426000
|
| 1440 | #define UMC_BASE__INST2_SEG3 0
|
| 1441 | #define UMC_BASE__INST2_SEG4 0
|
| 1442 | #define UMC_BASE__INST2_SEG5 0
|
| 1443 |
|
| 1444 | #define UMC_BASE__INST3_SEG0 0x00013320
|
| 1445 | #define UMC_BASE__INST3_SEG1 0x000D4000
|
| 1446 | #define UMC_BASE__INST3_SEG2 0x00426400
|
| 1447 | #define UMC_BASE__INST3_SEG3 0
|
| 1448 | #define UMC_BASE__INST3_SEG4 0
|
| 1449 | #define UMC_BASE__INST3_SEG5 0
|
| 1450 |
|
| 1451 | #define UMC_BASE__INST4_SEG0 0x00013340
|
| 1452 | #define UMC_BASE__INST4_SEG1 0x00114000
|
| 1453 | #define UMC_BASE__INST4_SEG2 0x00426800
|
| 1454 | #define UMC_BASE__INST4_SEG3 0
|
| 1455 | #define UMC_BASE__INST4_SEG4 0
|
| 1456 | #define UMC_BASE__INST4_SEG5 0
|
| 1457 |
|
| 1458 | #define UMC_BASE__INST5_SEG0 0x00013360
|
| 1459 | #define UMC_BASE__INST5_SEG1 0x00154000
|
| 1460 | #define UMC_BASE__INST5_SEG2 0x00426C00
|
| 1461 | #define UMC_BASE__INST5_SEG3 0
|
| 1462 | #define UMC_BASE__INST5_SEG4 0
|
| 1463 | #define UMC_BASE__INST5_SEG5 0
|
| 1464 |
|
| 1465 | #define UMC_BASE__INST6_SEG0 0x00013380
|
| 1466 | #define UMC_BASE__INST6_SEG1 0x00194000
|
| 1467 | #define UMC_BASE__INST6_SEG2 0x00427000
|
| 1468 | #define UMC_BASE__INST6_SEG3 0
|
| 1469 | #define UMC_BASE__INST6_SEG4 0
|
| 1470 | #define UMC_BASE__INST6_SEG5 0
|
| 1471 |
|
| 1472 | #define UMC_BASE__INST7_SEG0 0x000133A0
|
| 1473 | #define UMC_BASE__INST7_SEG1 0x001D4000
|
| 1474 | #define UMC_BASE__INST7_SEG2 0x00427400
|
| 1475 | #define UMC_BASE__INST7_SEG3 0
|
| 1476 | #define UMC_BASE__INST7_SEG4 0
|
| 1477 | #define UMC_BASE__INST7_SEG5 0
|
| 1478 |
|
| 1479 | #define UVD_BASE__INST0_SEG0 0x00007800
|
| 1480 | #define UVD_BASE__INST0_SEG1 0x00007E00
|
| 1481 | #define UVD_BASE__INST0_SEG2 0x00012180
|
| 1482 | #define UVD_BASE__INST0_SEG3 0x00403000
|
| 1483 | #define UVD_BASE__INST0_SEG4 0
|
| 1484 | #define UVD_BASE__INST0_SEG5 0
|
| 1485 |
|
| 1486 | #define UVD_BASE__INST1_SEG0 0x00007A00
|
| 1487 | #define UVD_BASE__INST1_SEG1 0x00009000
|
| 1488 | #define UVD_BASE__INST1_SEG2 0x000136E0
|
| 1489 | #define UVD_BASE__INST1_SEG3 0x0042DC00
|
| 1490 | #define UVD_BASE__INST1_SEG4 0
|
| 1491 | #define UVD_BASE__INST1_SEG5 0
|
| 1492 |
|
| 1493 | #define UVD_BASE__INST2_SEG0 0
|
| 1494 | #define UVD_BASE__INST2_SEG1 0
|
| 1495 | #define UVD_BASE__INST2_SEG2 0
|
| 1496 | #define UVD_BASE__INST2_SEG3 0
|
| 1497 | #define UVD_BASE__INST2_SEG4 0
|
| 1498 | #define UVD_BASE__INST2_SEG5 0
|
| 1499 |
|
| 1500 | #define UVD_BASE__INST3_SEG0 0
|
| 1501 | #define UVD_BASE__INST3_SEG1 0
|
| 1502 | #define UVD_BASE__INST3_SEG2 0
|
| 1503 | #define UVD_BASE__INST3_SEG3 0
|
| 1504 | #define UVD_BASE__INST3_SEG4 0
|
| 1505 | #define UVD_BASE__INST3_SEG5 0
|
| 1506 |
|
| 1507 | #define UVD_BASE__INST4_SEG0 0
|
| 1508 | #define UVD_BASE__INST4_SEG1 0
|
| 1509 | #define UVD_BASE__INST4_SEG2 0
|
| 1510 | #define UVD_BASE__INST4_SEG3 0
|
| 1511 | #define UVD_BASE__INST4_SEG4 0
|
| 1512 | #define UVD_BASE__INST4_SEG5 0
|
| 1513 |
|
| 1514 | #define UVD_BASE__INST5_SEG0 0
|
| 1515 | #define UVD_BASE__INST5_SEG1 0
|
| 1516 | #define UVD_BASE__INST5_SEG2 0
|
| 1517 | #define UVD_BASE__INST5_SEG3 0
|
| 1518 | #define UVD_BASE__INST5_SEG4 0
|
| 1519 | #define UVD_BASE__INST5_SEG5 0
|
| 1520 |
|
| 1521 | #define UVD_BASE__INST6_SEG0 0
|
| 1522 | #define UVD_BASE__INST6_SEG1 0
|
| 1523 | #define UVD_BASE__INST6_SEG2 0
|
| 1524 | #define UVD_BASE__INST6_SEG3 0
|
| 1525 | #define UVD_BASE__INST6_SEG4 0
|
| 1526 | #define UVD_BASE__INST6_SEG5 0
|
| 1527 |
|
| 1528 | #define UVD_BASE__INST7_SEG0 0
|
| 1529 | #define UVD_BASE__INST7_SEG1 0
|
| 1530 | #define UVD_BASE__INST7_SEG2 0
|
| 1531 | #define UVD_BASE__INST7_SEG3 0
|
| 1532 | #define UVD_BASE__INST7_SEG4 0
|
| 1533 | #define UVD_BASE__INST7_SEG5 0
|
| 1534 |
|
| 1535 | #define DBGU_IO_BASE__INST0_SEG0 0x000001E0
|
| 1536 | #define DBGU_IO_BASE__INST0_SEG1 0x000125A0
|
| 1537 | #define DBGU_IO_BASE__INST0_SEG2 0x0040B400
|
| 1538 | #define DBGU_IO_BASE__INST0_SEG3 0
|
| 1539 | #define DBGU_IO_BASE__INST0_SEG4 0
|
| 1540 | #define DBGU_IO_BASE__INST0_SEG5 0
|
| 1541 |
|
| 1542 | #define DBGU_IO_BASE__INST1_SEG0 0
|
| 1543 | #define DBGU_IO_BASE__INST1_SEG1 0
|
| 1544 | #define DBGU_IO_BASE__INST1_SEG2 0
|
| 1545 | #define DBGU_IO_BASE__INST1_SEG3 0
|
| 1546 | #define DBGU_IO_BASE__INST1_SEG4 0
|
| 1547 | #define DBGU_IO_BASE__INST1_SEG5 0
|
| 1548 |
|
| 1549 | #define DBGU_IO_BASE__INST2_SEG0 0
|
| 1550 | #define DBGU_IO_BASE__INST2_SEG1 0
|
| 1551 | #define DBGU_IO_BASE__INST2_SEG2 0
|
| 1552 | #define DBGU_IO_BASE__INST2_SEG3 0
|
| 1553 | #define DBGU_IO_BASE__INST2_SEG4 0
|
| 1554 | #define DBGU_IO_BASE__INST2_SEG5 0
|
| 1555 |
|
| 1556 | #define DBGU_IO_BASE__INST3_SEG0 0
|
| 1557 | #define DBGU_IO_BASE__INST3_SEG1 0
|
| 1558 | #define DBGU_IO_BASE__INST3_SEG2 0
|
| 1559 | #define DBGU_IO_BASE__INST3_SEG3 0
|
| 1560 | #define DBGU_IO_BASE__INST3_SEG4 0
|
| 1561 | #define DBGU_IO_BASE__INST3_SEG5 0
|
| 1562 |
|
| 1563 | #define DBGU_IO_BASE__INST4_SEG0 0
|
| 1564 | #define DBGU_IO_BASE__INST4_SEG1 0
|
| 1565 | #define DBGU_IO_BASE__INST4_SEG2 0
|
| 1566 | #define DBGU_IO_BASE__INST4_SEG3 0
|
| 1567 | #define DBGU_IO_BASE__INST4_SEG4 0
|
| 1568 | #define DBGU_IO_BASE__INST4_SEG5 0
|
| 1569 |
|
| 1570 | #define DBGU_IO_BASE__INST5_SEG0 0
|
| 1571 | #define DBGU_IO_BASE__INST5_SEG1 0
|
| 1572 | #define DBGU_IO_BASE__INST5_SEG2 0
|
| 1573 | #define DBGU_IO_BASE__INST5_SEG3 0
|
| 1574 | #define DBGU_IO_BASE__INST5_SEG4 0
|
| 1575 | #define DBGU_IO_BASE__INST5_SEG5 0
|
| 1576 |
|
| 1577 | #define DBGU_IO_BASE__INST6_SEG0 0
|
| 1578 | #define DBGU_IO_BASE__INST6_SEG1 0
|
| 1579 | #define DBGU_IO_BASE__INST6_SEG2 0
|
| 1580 | #define DBGU_IO_BASE__INST6_SEG3 0
|
| 1581 | #define DBGU_IO_BASE__INST6_SEG4 0
|
| 1582 | #define DBGU_IO_BASE__INST6_SEG5 0
|
| 1583 |
|
| 1584 | #define DBGU_IO_BASE__INST7_SEG0 0
|
| 1585 | #define DBGU_IO_BASE__INST7_SEG1 0
|
| 1586 | #define DBGU_IO_BASE__INST7_SEG2 0
|
| 1587 | #define DBGU_IO_BASE__INST7_SEG3 0
|
| 1588 | #define DBGU_IO_BASE__INST7_SEG4 0
|
| 1589 | #define DBGU_IO_BASE__INST7_SEG5 0
|
| 1590 |
|
| 1591 | #define RSMU_BASE__INST0_SEG0 0x00012000
|
| 1592 | #define RSMU_BASE__INST0_SEG1 0
|
| 1593 | #define RSMU_BASE__INST0_SEG2 0
|
| 1594 | #define RSMU_BASE__INST0_SEG3 0
|
| 1595 | #define RSMU_BASE__INST0_SEG4 0
|
| 1596 | #define RSMU_BASE__INST0_SEG5 0
|
| 1597 |
|
| 1598 | #define RSMU_BASE__INST1_SEG0 0
|
| 1599 | #define RSMU_BASE__INST1_SEG1 0
|
| 1600 | #define RSMU_BASE__INST1_SEG2 0
|
| 1601 | #define RSMU_BASE__INST1_SEG3 0
|
| 1602 | #define RSMU_BASE__INST1_SEG4 0
|
| 1603 | #define RSMU_BASE__INST1_SEG5 0
|
| 1604 |
|
| 1605 | #define RSMU_BASE__INST2_SEG0 0
|
| 1606 | #define RSMU_BASE__INST2_SEG1 0
|
| 1607 | #define RSMU_BASE__INST2_SEG2 0
|
| 1608 | #define RSMU_BASE__INST2_SEG3 0
|
| 1609 | #define RSMU_BASE__INST2_SEG4 0
|
| 1610 | #define RSMU_BASE__INST2_SEG5 0
|
| 1611 |
|
| 1612 | #define RSMU_BASE__INST3_SEG0 0
|
| 1613 | #define RSMU_BASE__INST3_SEG1 0
|
| 1614 | #define RSMU_BASE__INST3_SEG2 0
|
| 1615 | #define RSMU_BASE__INST3_SEG3 0
|
| 1616 | #define RSMU_BASE__INST3_SEG4 0
|
| 1617 | #define RSMU_BASE__INST3_SEG5 0
|
| 1618 |
|
| 1619 | #define RSMU_BASE__INST4_SEG0 0
|
| 1620 | #define RSMU_BASE__INST4_SEG1 0
|
| 1621 | #define RSMU_BASE__INST4_SEG2 0
|
| 1622 | #define RSMU_BASE__INST4_SEG3 0
|
| 1623 | #define RSMU_BASE__INST4_SEG4 0
|
| 1624 | #define RSMU_BASE__INST4_SEG5 0
|
| 1625 |
|
| 1626 | #define RSMU_BASE__INST5_SEG0 0
|
| 1627 | #define RSMU_BASE__INST5_SEG1 0
|
| 1628 | #define RSMU_BASE__INST5_SEG2 0
|
| 1629 | #define RSMU_BASE__INST5_SEG3 0
|
| 1630 | #define RSMU_BASE__INST5_SEG4 0
|
| 1631 | #define RSMU_BASE__INST5_SEG5 0
|
| 1632 |
|
| 1633 | #define RSMU_BASE__INST6_SEG0 0
|
| 1634 | #define RSMU_BASE__INST6_SEG1 0
|
| 1635 | #define RSMU_BASE__INST6_SEG2 0
|
| 1636 | #define RSMU_BASE__INST6_SEG3 0
|
| 1637 | #define RSMU_BASE__INST6_SEG4 0
|
| 1638 | #define RSMU_BASE__INST6_SEG5 0
|
| 1639 |
|
| 1640 | #define RSMU_BASE__INST7_SEG0 0
|
| 1641 | #define RSMU_BASE__INST7_SEG1 0
|
| 1642 | #define RSMU_BASE__INST7_SEG2 0
|
| 1643 | #define RSMU_BASE__INST7_SEG3 0
|
| 1644 | #define RSMU_BASE__INST7_SEG4 0
|
| 1645 | #define RSMU_BASE__INST7_SEG5 0
|
| 1646 |
|
| 1647 |
|
| 1648 | #endif
|