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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/*
24 * This file defines the private interface between the
25 * AMD kernel graphics drivers and the AMD KFD.
26 */
27
28#ifndef KGD_KFD_INTERFACE_H_INCLUDED
29#define KGD_KFD_INTERFACE_H_INCLUDED
30
31#include <linux/types.h>
32#include <linux/bitmap.h>
33#include <linux/dma-fence.h>
34#include "amdgpu_irq.h"
35#include "amdgpu_gfx.h"
36#include "amdgpu_ptl.h"
37
38struct pci_dev;
39struct amdgpu_device;
40
41struct kfd_dev;
42struct kgd_mem;
43
44enum kfd_preempt_type {
45 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
46 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
47 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE
48};
49
50struct kfd_vm_fault_info {
51 uint64_t page_addr;
52 uint32_t vmid;
53 uint32_t mc_id;
54 uint32_t status;
55 bool prot_valid;
56 bool prot_read;
57 bool prot_write;
58 bool prot_exec;
59};
60
61/* For getting GPU local memory information from KGD */
62struct kfd_local_mem_info {
63 uint64_t local_mem_size_private;
64 uint64_t local_mem_size_public;
65 uint32_t vram_width;
66 uint32_t mem_clk_max;
67};
68
69enum kgd_memory_pool {
70 KGD_POOL_SYSTEM_CACHEABLE = 1,
71 KGD_POOL_SYSTEM_WRITECOMBINE = 2,
72 KGD_POOL_FRAMEBUFFER = 3,
73};
74
75struct kfd_cu_occupancy {
76 u32 wave_cnt;
77 u32 doorbell_off;
78};
79
80/**
81 * enum kfd_sched_policy
82 *
83 * @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp)
84 * scheduling. In this scheduling mode we're using the firmware code to
85 * schedule the user mode queues and kernel queues such as HIQ and DIQ.
86 * the HIQ queue is used as a special queue that dispatches the configuration
87 * to the cp and the user mode queues list that are currently running.
88 * the DIQ queue is a debugging queue that dispatches debugging commands to the
89 * firmware.
90 * in this scheduling mode user mode queues over subscription feature is
91 * enabled.
92 *
93 * @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over
94 * subscription feature disabled.
95 *
96 * @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly
97 * set the command processor registers and sets the queues "manually". This
98 * mode is used *ONLY* for debugging proposes.
99 *
100 */
101enum kfd_sched_policy {
102 KFD_SCHED_POLICY_HWS = 0,
103 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION,
104 KFD_SCHED_POLICY_NO_HWS
105};
106
107struct kgd2kfd_shared_resources {
108 /* Bit n == 1 means VMID n is available for KFD. */
109 unsigned int compute_vmid_bitmap;
110
111 /* number of pipes per mec */
112 uint32_t num_pipe_per_mec;
113
114 /* number of queues per pipe */
115 uint32_t num_queue_per_pipe;
116
117 /* Bit n == 1 means Queue n is available for KFD */
118 DECLARE_BITMAP(cp_queue_bitmap, AMDGPU_MAX_QUEUES);
119
120 /* SDMA doorbell assignments (SOC15 and later chips only). Only
121 * specific doorbells are routed to each SDMA engine. Others
122 * are routed to IH and VCN. They are not usable by the CP.
123 */
124 uint32_t *sdma_doorbell_idx;
125
126 /* From SOC15 onward, the doorbell index range not usable for CP
127 * queues.
128 */
129 uint32_t non_cp_doorbells_start;
130 uint32_t non_cp_doorbells_end;
131
132 /* Base address of doorbell aperture. */
133 phys_addr_t doorbell_physical_address;
134
135 /* Size in bytes of doorbell aperture. */
136 size_t doorbell_aperture_size;
137
138 /* Number of bytes at start of aperture reserved for KGD. */
139 size_t doorbell_start_offset;
140
141 /* GPUVM address space size in bytes */
142 uint64_t gpuvm_size;
143
144 /* Minor device number of the render node */
145 int drm_render_minor;
146
147 bool enable_mes;
148};
149
150struct tile_config {
151 uint32_t *tile_config_ptr;
152 uint32_t *macro_tile_config_ptr;
153 uint32_t num_tile_configs;
154 uint32_t num_macro_tile_configs;
155
156 uint32_t gb_addr_config;
157 uint32_t num_banks;
158 uint32_t num_ranks;
159};
160
161#define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
162
163/**
164 * struct kfd2kgd_calls
165 *
166 * @program_sh_mem_settings: A function that should initiate the memory
167 * properties such as main aperture memory type (cache / non cached) and
168 * secondary aperture base address, size and memory type.
169 * This function is used only for no cp scheduling mode.
170 *
171 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
172 * scheduling mode. Only used for no cp scheduling mode.
173 *
174 * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
175 * sceduling mode.
176 *
177 * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
178 * used only for no HWS mode.
179 *
180 * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
181 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
182 *
183 * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
184 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
185 *
186 * @hqd_is_occupies: Checks if a hqd slot is occupied.
187 *
188 * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
189 *
190 * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
191 *
192 * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
193 * SDMA hqd slot.
194 *
195 * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
196 * Only used for no cp scheduling mode
197 *
198 * @set_vm_context_page_table_base: Program page table base for a VMID
199 *
200 * @invalidate_tlbs: Invalidate TLBs for a specific PASID
201 *
202 * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
203 *
204 * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
205 * IH ring entry. This function allows the KFD ISR to get the VMID
206 * from the fault status register as early as possible.
207 *
208 * @get_cu_occupancy: Function pointer that returns to caller the number
209 * of wave fronts that are in flight for all of the queues of a process
210 * as identified by its pasid. It is important to note that the value
211 * returned by this function is a snapshot of current moment and cannot
212 * guarantee any minimum for the number of waves in-flight. This function
213 * is defined for devices that belong to GFX9 and later GFX families. Care
214 * must be taken in calling this function as it is not defined for devices
215 * that belong to GFX8 and below GFX families.
216 *
217 * This structure contains function pointers to services that the kgd driver
218 * provides to amdkfd driver.
219 *
220 */
221struct kfd2kgd_calls {
222 /* Register access functions */
223 void (*program_sh_mem_settings)(struct amdgpu_device *adev, uint32_t vmid,
224 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
225 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases,
226 uint32_t inst);
227
228 int (*set_pasid_vmid_mapping)(struct amdgpu_device *adev, u32 pasid,
229 unsigned int vmid, uint32_t inst);
230
231 int (*init_interrupts)(struct amdgpu_device *adev, uint32_t pipe_id,
232 uint32_t inst);
233
234 int (*hqd_load)(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
235 uint32_t queue_id, uint32_t __user *wptr,
236 uint32_t wptr_shift, uint32_t wptr_mask,
237 struct mm_struct *mm, uint32_t inst);
238
239 int (*hiq_mqd_load)(struct amdgpu_device *adev, void *mqd,
240 uint32_t pipe_id, uint32_t queue_id,
241 uint32_t doorbell_off, uint32_t inst);
242
243 int (*hqd_sdma_load)(struct amdgpu_device *adev, void *mqd,
244 uint32_t __user *wptr, struct mm_struct *mm);
245
246 int (*hqd_dump)(struct amdgpu_device *adev,
247 uint32_t pipe_id, uint32_t queue_id,
248 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst);
249
250 int (*hqd_sdma_dump)(struct amdgpu_device *adev,
251 uint32_t engine_id, uint32_t queue_id,
252 uint32_t (**dump)[2], uint32_t *n_regs);
253
254 bool (*hqd_is_occupied)(struct amdgpu_device *adev,
255 uint64_t queue_address, uint32_t pipe_id,
256 uint32_t queue_id, uint32_t inst);
257
258 int (*hqd_destroy)(struct amdgpu_device *adev, void *mqd,
259 enum kfd_preempt_type reset_type,
260 unsigned int timeout, uint32_t pipe_id,
261 uint32_t queue_id, uint32_t inst);
262
263 bool (*hqd_sdma_is_occupied)(struct amdgpu_device *adev, void *mqd);
264
265 int (*hqd_sdma_destroy)(struct amdgpu_device *adev, void *mqd,
266 unsigned int timeout);
267
268 int (*wave_control_execute)(struct amdgpu_device *adev,
269 uint32_t gfx_index_val,
270 uint32_t sq_cmd, uint32_t inst);
271 bool (*get_atc_vmid_pasid_mapping_info)(struct amdgpu_device *adev,
272 uint8_t vmid,
273 uint16_t *p_pasid);
274
275 /* No longer needed from GFXv9 onward. The scratch base address is
276 * passed to the shader by the CP. It's the user mode driver's
277 * responsibility.
278 */
279 void (*set_scratch_backing_va)(struct amdgpu_device *adev,
280 uint64_t va, uint32_t vmid);
281
282 void (*set_vm_context_page_table_base)(struct amdgpu_device *adev,
283 uint32_t vmid, uint64_t page_table_base);
284 uint32_t (*read_vmid_from_vmfault_reg)(struct amdgpu_device *adev);
285
286 uint32_t (*enable_debug_trap)(struct amdgpu_device *adev,
287 bool restore_dbg_registers,
288 uint32_t vmid);
289 uint32_t (*disable_debug_trap)(struct amdgpu_device *adev,
290 bool keep_trap_enabled,
291 uint32_t vmid);
292 int (*validate_trap_override_request)(struct amdgpu_device *adev,
293 uint32_t trap_override,
294 uint32_t *trap_mask_supported);
295 uint32_t (*set_wave_launch_trap_override)(struct amdgpu_device *adev,
296 uint32_t vmid,
297 uint32_t trap_override,
298 uint32_t trap_mask_bits,
299 uint32_t trap_mask_request,
300 uint32_t *trap_mask_prev,
301 uint32_t kfd_dbg_trap_cntl_prev);
302 uint32_t (*set_wave_launch_mode)(struct amdgpu_device *adev,
303 uint8_t wave_launch_mode,
304 uint32_t vmid);
305 uint32_t (*set_address_watch)(struct amdgpu_device *adev,
306 uint64_t watch_address,
307 uint32_t watch_address_mask,
308 uint32_t watch_id,
309 uint32_t watch_mode,
310 uint32_t debug_vmid,
311 uint32_t inst);
312 uint32_t (*clear_address_watch)(struct amdgpu_device *adev,
313 uint32_t watch_id);
314 void (*get_iq_wait_times)(struct amdgpu_device *adev,
315 uint32_t *wait_times,
316 uint32_t inst);
317 void (*build_dequeue_wait_counts_packet_info)(struct amdgpu_device *adev,
318 uint32_t wait_times,
319 uint32_t sch_wave,
320 uint32_t que_sleep,
321 uint32_t *reg_offset,
322 uint32_t *reg_data);
323 void (*get_cu_occupancy)(struct amdgpu_device *adev,
324 struct kfd_cu_occupancy *cu_occupancy,
325 int *max_waves_per_cu, uint32_t inst);
326 void (*program_trap_handler_settings)(struct amdgpu_device *adev,
327 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
328 uint32_t inst);
329 uint64_t (*hqd_get_pq_addr)(struct amdgpu_device *adev,
330 uint32_t pipe_id, uint32_t queue_id,
331 uint32_t inst);
332 uint64_t (*hqd_reset)(struct amdgpu_device *adev,
333 uint32_t pipe_id, uint32_t queue_id,
334 uint32_t inst, unsigned int utimeout);
335 uint32_t (*hqd_sdma_get_doorbell)(struct amdgpu_device *adev,
336 int engine, int queue);
337 uint32_t (*ptl_ctrl)(struct amdgpu_device *adev,
338 uint32_t cmd,
339 uint32_t *ptl_state,
340 enum amdgpu_ptl_fmt *fmt1,
341 enum amdgpu_ptl_fmt *fmt2);
342 int (*hqd_sdma_get_counter)(struct amdgpu_device *adev,
343 void *mqd, uint32_t num_sdma_queues_per_eng,
344 uint64_t *val);
345};
346
347#endif /* KGD_KFD_INTERFACE_H_INCLUDED */