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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __KGD_PP_INTERFACE_H__
25#define __KGD_PP_INTERFACE_H__
26
27#include <linux/units.h>
28
29extern const struct amdgpu_ip_block_version pp_smu_ip_block;
30extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
31extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
32extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
33extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
34extern const struct amdgpu_ip_block_version smu_v15_0_ip_block;
35
36enum smu_temp_metric_type {
37 SMU_TEMP_METRIC_BASEBOARD,
38 SMU_TEMP_METRIC_GPUBOARD,
39 SMU_TEMP_METRIC_MAX,
40};
41
42enum smu_event_type {
43 SMU_EVENT_RESET_COMPLETE = 0,
44};
45
46struct amd_vce_state {
47 /* vce clocks */
48 u32 evclk;
49 u32 ecclk;
50 /* gpu clocks */
51 u32 sclk;
52 u32 mclk;
53 u8 clk_idx;
54 u8 pstate;
55};
56
57
58enum amd_dpm_forced_level {
59 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
60 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
61 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
62 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
63 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
64 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
65 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
66 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
67 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
68 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
69};
70
71enum amd_pm_state_type {
72 /* not used for dpm */
73 POWER_STATE_TYPE_DEFAULT,
74 POWER_STATE_TYPE_POWERSAVE,
75 /* user selectable states */
76 POWER_STATE_TYPE_BATTERY,
77 POWER_STATE_TYPE_BALANCED,
78 POWER_STATE_TYPE_PERFORMANCE,
79 /* internal states */
80 POWER_STATE_TYPE_INTERNAL_UVD,
81 POWER_STATE_TYPE_INTERNAL_UVD_SD,
82 POWER_STATE_TYPE_INTERNAL_UVD_HD,
83 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
84 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
85 POWER_STATE_TYPE_INTERNAL_BOOT,
86 POWER_STATE_TYPE_INTERNAL_THERMAL,
87 POWER_STATE_TYPE_INTERNAL_ACPI,
88 POWER_STATE_TYPE_INTERNAL_ULV,
89 POWER_STATE_TYPE_INTERNAL_3DPERF,
90};
91
92#define AMD_MAX_VCE_LEVELS 6
93
94enum amd_vce_level {
95 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
96 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
97 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
98 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
99 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
100 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
101};
102
103enum amd_fan_ctrl_mode {
104 AMD_FAN_CTRL_NONE = 0,
105 AMD_FAN_CTRL_MANUAL = 1,
106 AMD_FAN_CTRL_AUTO = 2,
107};
108
109enum pp_clock_type {
110 PP_SCLK,
111 PP_MCLK,
112 PP_PCIE,
113 PP_SOCCLK,
114 PP_FCLK,
115 PP_DCEFCLK,
116 PP_VCLK,
117 PP_VCLK1,
118 PP_DCLK,
119 PP_DCLK1,
120 PP_ISPICLK,
121 PP_ISPXCLK,
122 OD_SCLK,
123 OD_MCLK,
124 OD_FCLK,
125 OD_VDDC_CURVE,
126 OD_RANGE,
127 OD_VDDGFX_OFFSET,
128 OD_CCLK,
129 OD_FAN_CURVE,
130 OD_ACOUSTIC_LIMIT,
131 OD_ACOUSTIC_TARGET,
132 OD_FAN_TARGET_TEMPERATURE,
133 OD_FAN_MINIMUM_PWM,
134 OD_FAN_ZERO_RPM_ENABLE,
135 OD_FAN_ZERO_RPM_STOP_TEMP,
136};
137
138enum amd_pp_sensors {
139 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
140 AMDGPU_PP_SENSOR_CPU_CLK,
141 AMDGPU_PP_SENSOR_VDDNB,
142 AMDGPU_PP_SENSOR_VDDGFX,
143 AMDGPU_PP_SENSOR_UVD_VCLK,
144 AMDGPU_PP_SENSOR_UVD_DCLK,
145 AMDGPU_PP_SENSOR_VCE_ECCLK,
146 AMDGPU_PP_SENSOR_GPU_LOAD,
147 AMDGPU_PP_SENSOR_MEM_LOAD,
148 AMDGPU_PP_SENSOR_GFX_MCLK,
149 AMDGPU_PP_SENSOR_GPU_TEMP,
150 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
151 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
152 AMDGPU_PP_SENSOR_MEM_TEMP,
153 AMDGPU_PP_SENSOR_VCE_POWER,
154 AMDGPU_PP_SENSOR_UVD_POWER,
155 AMDGPU_PP_SENSOR_GPU_AVG_POWER, /* milliwatts */
156 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, /* milliwatts */
157 AMDGPU_PP_SENSOR_SS_APU_SHARE,
158 AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
159 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
160 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
161 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
162 AMDGPU_PP_SENSOR_MIN_FAN_RPM,
163 AMDGPU_PP_SENSOR_MAX_FAN_RPM,
164 AMDGPU_PP_SENSOR_VCN_POWER_STATE,
165 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
166 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
167 AMDGPU_PP_SENSOR_VCN_LOAD,
168 AMDGPU_PP_SENSOR_VDDBOARD,
169 AMDGPU_PP_SENSOR_NODEPOWERLIMIT,
170 AMDGPU_PP_SENSOR_NODEPOWER,
171 AMDGPU_PP_SENSOR_GPPTRESIDENCY,
172 AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT,
173 AMDGPU_PP_SENSOR_UBB_POWER,
174 AMDGPU_PP_SENSOR_UBB_POWER_LIMIT,
175};
176
177enum amd_pp_task {
178 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
179 AMD_PP_TASK_ENABLE_USER_STATE,
180 AMD_PP_TASK_READJUST_POWER_STATE,
181 AMD_PP_TASK_COMPLETE_INIT,
182 AMD_PP_TASK_MAX
183};
184
185enum PP_SMC_POWER_PROFILE {
186 PP_SMC_POWER_PROFILE_UNKNOWN = -1,
187 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
188 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
189 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
190 PP_SMC_POWER_PROFILE_VIDEO = 0x3,
191 PP_SMC_POWER_PROFILE_VR = 0x4,
192 PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
193 PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
194 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7,
195 PP_SMC_POWER_PROFILE_CAPPED = 0x8,
196 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9,
197 PP_SMC_POWER_PROFILE_COUNT,
198};
199
200extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
201
202
203
204enum {
205 PP_GROUP_UNKNOWN = 0,
206 PP_GROUP_GFX = 1,
207 PP_GROUP_SYS,
208 PP_GROUP_MAX
209};
210
211enum PP_OD_DPM_TABLE_COMMAND {
212 PP_OD_EDIT_SCLK_VDDC_TABLE,
213 PP_OD_EDIT_MCLK_VDDC_TABLE,
214 PP_OD_EDIT_FCLK_TABLE,
215 PP_OD_EDIT_CCLK_VDDC_TABLE,
216 PP_OD_EDIT_VDDC_CURVE,
217 PP_OD_RESTORE_DEFAULT_TABLE,
218 PP_OD_COMMIT_DPM_TABLE,
219 PP_OD_EDIT_VDDGFX_OFFSET,
220 PP_OD_EDIT_FAN_CURVE,
221 PP_OD_EDIT_ACOUSTIC_LIMIT,
222 PP_OD_EDIT_ACOUSTIC_TARGET,
223 PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
224 PP_OD_EDIT_FAN_MINIMUM_PWM,
225 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE,
226 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP,
227};
228
229struct pp_states_info {
230 uint32_t nums;
231 uint32_t states[16];
232};
233
234enum PP_HWMON_TEMP {
235 PP_TEMP_EDGE = 0,
236 PP_TEMP_JUNCTION,
237 PP_TEMP_MEM,
238 PP_TEMP_MAX
239};
240
241enum pp_mp1_state {
242 PP_MP1_STATE_NONE,
243 PP_MP1_STATE_SHUTDOWN,
244 PP_MP1_STATE_UNLOAD,
245 PP_MP1_STATE_RESET,
246 PP_MP1_STATE_FLR,
247};
248
249enum pp_df_cstate {
250 DF_CSTATE_DISALLOW = 0,
251 DF_CSTATE_ALLOW,
252};
253
254/**
255 * DOC: amdgpu_pp_power
256 *
257 * APU power is managed to system-level requirements through the PPT
258 * (package power tracking) feature. PPT is intended to limit power to the
259 * requirements of the power source and could be dynamically updated to
260 * maximize APU performance within the system power budget.
261 *
262 * Two types of power measurement can be requested, where supported, with
263 * :c:type:`enum pp_power_type <pp_power_type>`.
264 */
265
266/**
267 * enum pp_power_limit_level - Used to query the power limits
268 *
269 * @PP_PWR_LIMIT_MIN: Minimum Power Limit
270 * @PP_PWR_LIMIT_CURRENT: Current Power Limit
271 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
272 * @PP_PWR_LIMIT_MAX: Maximum Power Limit
273 */
274enum pp_power_limit_level {
275 PP_PWR_LIMIT_MIN = -1,
276 PP_PWR_LIMIT_CURRENT,
277 PP_PWR_LIMIT_DEFAULT,
278 PP_PWR_LIMIT_MAX,
279};
280
281/**
282 * enum pp_power_type - Used to specify the type of the requested power
283 *
284 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
285 * moving average of APU power (default ~5000 ms).
286 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
287 * where supported.
288 */
289enum pp_power_type {
290 PP_PWR_TYPE_SUSTAINED,
291 PP_PWR_TYPE_FAST,
292};
293
294enum pp_xgmi_plpd_mode {
295 XGMI_PLPD_NONE = -1,
296 XGMI_PLPD_DISALLOW,
297 XGMI_PLPD_DEFAULT,
298 XGMI_PLPD_OPTIMIZED,
299 XGMI_PLPD_COUNT,
300};
301
302enum pp_pm_policy {
303 PP_PM_POLICY_NONE = -1,
304 PP_PM_POLICY_SOC_PSTATE = 0,
305 PP_PM_POLICY_XGMI_PLPD,
306 PP_PM_POLICY_NUM,
307};
308
309enum pp_policy_soc_pstate {
310 SOC_PSTATE_DEFAULT = 0,
311 SOC_PSTATE_0,
312 SOC_PSTATE_1,
313 SOC_PSTATE_2,
314 SOC_PSTAT_COUNT,
315};
316
317#define PP_POLICY_MAX_LEVELS 5
318
319#define PP_GROUP_MASK 0xF0000000
320#define PP_GROUP_SHIFT 28
321
322#define PP_BLOCK_MASK 0x0FFFFF00
323#define PP_BLOCK_SHIFT 8
324
325#define PP_BLOCK_GFX_CG 0x01
326#define PP_BLOCK_GFX_MG 0x02
327#define PP_BLOCK_GFX_3D 0x04
328#define PP_BLOCK_GFX_RLC 0x08
329#define PP_BLOCK_GFX_CP 0x10
330#define PP_BLOCK_SYS_BIF 0x01
331#define PP_BLOCK_SYS_MC 0x02
332#define PP_BLOCK_SYS_ROM 0x04
333#define PP_BLOCK_SYS_DRM 0x08
334#define PP_BLOCK_SYS_HDP 0x10
335#define PP_BLOCK_SYS_SDMA 0x20
336
337#define PP_STATE_MASK 0x0000000F
338#define PP_STATE_SHIFT 0
339#define PP_STATE_SUPPORT_MASK 0x000000F0
340#define PP_STATE_SUPPORT_SHIFT 0
341
342#define PP_STATE_CG 0x01
343#define PP_STATE_LS 0x02
344#define PP_STATE_DS 0x04
345#define PP_STATE_SD 0x08
346#define PP_STATE_SUPPORT_CG 0x10
347#define PP_STATE_SUPPORT_LS 0x20
348#define PP_STATE_SUPPORT_DS 0x40
349#define PP_STATE_SUPPORT_SD 0x80
350
351#define PP_CG_MSG_ID(group, block, support, state) \
352 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
353 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
354
355#define XGMI_MODE_PSTATE_D3 0
356#define XGMI_MODE_PSTATE_D0 1
357
358#define NUM_HBM_INSTANCES 4
359#define NUM_XGMI_LINKS 8
360#define MAX_GFX_CLKS 8
361#define MAX_CLKS 4
362#define NUM_VCN 4
363#define NUM_JPEG_ENG 32
364#define NUM_JPEG_ENG_V1 40
365#define MAX_XCC 8
366#define NUM_XCP 8
367struct seq_file;
368enum amd_pp_clock_type;
369struct amd_pp_simple_clock_info;
370struct amd_pp_display_configuration;
371struct amd_pp_clock_info;
372struct pp_display_clock_request;
373struct pp_clock_levels_with_voltage;
374struct pp_clock_levels_with_latency;
375struct amd_pp_clocks;
376struct pp_smu_wm_range_sets;
377struct pp_smu_nv_clock_table;
378struct dpm_clocks;
379
380struct amdgpu_xcp_metrics {
381 /* Utilization Instantaneous (%) */
382 uint32_t gfx_busy_inst[MAX_XCC];
383 uint16_t jpeg_busy[NUM_JPEG_ENG];
384 uint16_t vcn_busy[NUM_VCN];
385 /* Utilization Accumulated (%) */
386 uint64_t gfx_busy_acc[MAX_XCC];
387};
388
389struct amdgpu_xcp_metrics_v1_1 {
390 /* Utilization Instantaneous (%) */
391 uint32_t gfx_busy_inst[MAX_XCC];
392 uint16_t jpeg_busy[NUM_JPEG_ENG];
393 uint16_t vcn_busy[NUM_VCN];
394 /* Utilization Accumulated (%) */
395 uint64_t gfx_busy_acc[MAX_XCC];
396 /* Total App Clock Counter Accumulated */
397 uint64_t gfx_below_host_limit_acc[MAX_XCC];
398};
399
400struct amdgpu_xcp_metrics_v1_2 {
401 /* Utilization Instantaneous (%) */
402 uint32_t gfx_busy_inst[MAX_XCC];
403 uint16_t jpeg_busy[NUM_JPEG_ENG_V1];
404 uint16_t vcn_busy[NUM_VCN];
405 /* Utilization Accumulated (%) */
406 uint64_t gfx_busy_acc[MAX_XCC];
407 /* Total App Clock Counter Accumulated */
408 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC];
409 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC];
410 uint64_t gfx_low_utilization_acc[MAX_XCC];
411 uint64_t gfx_below_host_limit_total_acc[MAX_XCC];
412};
413
414struct amd_pm_funcs {
415/* export for dpm on ci and si */
416 int (*pre_set_power_state)(void *handle);
417 int (*set_power_state)(void *handle);
418 void (*post_set_power_state)(void *handle);
419 void (*display_configuration_changed)(void *handle);
420 void (*print_power_state)(void *handle, void *ps);
421 bool (*vblank_too_short)(void *handle);
422 void (*notify_ac_dc)(void *handle);
423 int (*check_state_equal)(void *handle,
424 void *cps,
425 void *rps,
426 bool *equal);
427/* export for sysfs */
428 int (*set_fan_control_mode)(void *handle, u32 mode);
429 int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
430 int (*set_fan_speed_pwm)(void *handle, u32 speed);
431 int (*get_fan_speed_pwm)(void *handle, u32 *speed);
432 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
433 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
434 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
435 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
436 int (*get_sclk_od)(void *handle);
437 int (*set_sclk_od)(void *handle, uint32_t value);
438 int (*get_mclk_od)(void *handle);
439 int (*set_mclk_od)(void *handle, uint32_t value);
440 int (*read_sensor)(void *handle, int idx, void *value, int *size);
441 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
442 int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
443 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
444 enum amd_pm_state_type (*get_current_power_state)(void *handle);
445 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
446 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
447 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
448 int (*get_pp_table)(void *handle, char **table);
449 int (*set_pp_table)(void *handle, const char *buf, size_t size);
450 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
451 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
452 int (*pause_power_profile)(void *handle, bool pause);
453/* export to amdgpu */
454 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
455 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
456 enum amd_pm_state_type *user_state);
457 int (*load_firmware)(void *handle);
458 int (*wait_for_fw_loading_complete)(void *handle);
459 int (*set_powergating_by_smu)(void *handle,
460 uint32_t block_type,
461 bool gate,
462 int inst);
463 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
464 int (*set_power_limit)(void *handle, uint32_t limit_type, uint32_t n);
465 int (*get_power_limit)(void *handle, uint32_t *limit,
466 enum pp_power_limit_level pp_limit_level,
467 enum pp_power_type power_type);
468 int (*get_power_profile_mode)(void *handle, char *buf);
469 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
470 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
471 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
472 long *input, uint32_t size);
473 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
474 int (*smu_i2c_bus_access)(void *handle, bool acquire);
475 int (*gfx_state_change_set)(void *handle, uint32_t state);
476/* export to DC */
477 u32 (*get_sclk)(void *handle, bool low);
478 u32 (*get_mclk)(void *handle, bool low);
479 int (*display_configuration_change)(void *handle,
480 const struct amd_pp_display_configuration *input);
481 int (*get_current_clocks)(void *handle,
482 struct amd_pp_clock_info *clocks);
483 int (*get_clock_by_type)(void *handle,
484 enum amd_pp_clock_type type,
485 struct amd_pp_clocks *clocks);
486 int (*get_clock_by_type_with_latency)(void *handle,
487 enum amd_pp_clock_type type,
488 struct pp_clock_levels_with_latency *clocks);
489 int (*get_clock_by_type_with_voltage)(void *handle,
490 enum amd_pp_clock_type type,
491 struct pp_clock_levels_with_voltage *clocks);
492 int (*set_watermarks_for_clocks_ranges)(void *handle,
493 void *clock_ranges);
494 int (*display_clock_voltage_request)(void *handle,
495 struct pp_display_clock_request *clock);
496 int (*get_display_mode_validation_clocks)(void *handle,
497 struct amd_pp_simple_clock_info *clocks);
498 int (*notify_smu_enable_pwe)(void *handle);
499 int (*enable_mgpu_fan_boost)(void *handle);
500 int (*set_active_display_count)(void *handle, uint32_t count);
501 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
502 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
503 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
504 int (*get_asic_baco_capability)(void *handle);
505 int (*get_asic_baco_state)(void *handle, int *state);
506 int (*set_asic_baco_state)(void *handle, int state);
507 int (*get_ppfeature_status)(void *handle, char *buf);
508 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
509 int (*asic_reset_mode_2)(void *handle);
510 int (*asic_reset_enable_gfx_features)(void *handle);
511 int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
512 int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
513 ssize_t (*get_gpu_metrics)(void *handle, void **table);
514 ssize_t (*get_temp_metrics)(void *handle, enum smu_temp_metric_type type, void *table);
515 bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type);
516 ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table);
517 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
518 int (*set_watermarks_for_clock_ranges)(void *handle,
519 struct pp_smu_wm_range_sets *ranges);
520 int (*display_disable_memory_clock_switch)(void *handle,
521 bool disable_memory_clock_switch);
522 int (*get_max_sustainable_clocks_by_dc)(void *handle,
523 struct pp_smu_nv_clock_table *max_clocks);
524 int (*get_uclk_dpm_states)(void *handle,
525 unsigned int *clock_values_in_khz,
526 unsigned int *num_states);
527 int (*get_dpm_clock_table)(void *handle,
528 struct dpm_clocks *clock_table);
529 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
530 void (*pm_compute_clocks)(void *handle);
531 int (*notify_rlc_state)(void *handle, bool en);
532};
533
534struct metrics_table_header {
535 uint16_t structure_size;
536 uint8_t format_revision;
537 uint8_t content_revision;
538};
539
540enum amdgpu_metrics_attr_id {
541 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HOTSPOT,
542 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MEM,
543 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_VRSOC,
544 AMDGPU_METRICS_ATTR_ID_CURR_SOCKET_POWER,
545 AMDGPU_METRICS_ATTR_ID_AVERAGE_GFX_ACTIVITY,
546 AMDGPU_METRICS_ATTR_ID_AVERAGE_UMC_ACTIVITY,
547 AMDGPU_METRICS_ATTR_ID_MEM_MAX_BANDWIDTH,
548 AMDGPU_METRICS_ATTR_ID_ENERGY_ACCUMULATOR,
549 AMDGPU_METRICS_ATTR_ID_SYSTEM_CLOCK_COUNTER,
550 AMDGPU_METRICS_ATTR_ID_ACCUMULATION_COUNTER,
551 AMDGPU_METRICS_ATTR_ID_PROCHOT_RESIDENCY_ACC,
552 AMDGPU_METRICS_ATTR_ID_PPT_RESIDENCY_ACC,
553 AMDGPU_METRICS_ATTR_ID_SOCKET_THM_RESIDENCY_ACC,
554 AMDGPU_METRICS_ATTR_ID_VR_THM_RESIDENCY_ACC,
555 AMDGPU_METRICS_ATTR_ID_HBM_THM_RESIDENCY_ACC,
556 AMDGPU_METRICS_ATTR_ID_GFXCLK_LOCK_STATUS,
557 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_WIDTH,
558 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_SPEED,
559 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_WIDTH,
560 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_SPEED,
561 AMDGPU_METRICS_ATTR_ID_GFX_ACTIVITY_ACC,
562 AMDGPU_METRICS_ATTR_ID_MEM_ACTIVITY_ACC,
563 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_ACC,
564 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_INST,
565 AMDGPU_METRICS_ATTR_ID_PCIE_L0_TO_RECOV_COUNT_ACC,
566 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_COUNT_ACC,
567 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_ROVER_COUNT_ACC,
568 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_SENT_COUNT_ACC,
569 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_RCVD_COUNT_ACC,
570 AMDGPU_METRICS_ATTR_ID_XGMI_READ_DATA_ACC,
571 AMDGPU_METRICS_ATTR_ID_XGMI_WRITE_DATA_ACC,
572 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_STATUS,
573 AMDGPU_METRICS_ATTR_ID_FIRMWARE_TIMESTAMP,
574 AMDGPU_METRICS_ATTR_ID_CURRENT_GFXCLK,
575 AMDGPU_METRICS_ATTR_ID_CURRENT_SOCCLK,
576 AMDGPU_METRICS_ATTR_ID_CURRENT_VCLK0,
577 AMDGPU_METRICS_ATTR_ID_CURRENT_DCLK0,
578 AMDGPU_METRICS_ATTR_ID_CURRENT_UCLK,
579 AMDGPU_METRICS_ATTR_ID_NUM_PARTITION,
580 AMDGPU_METRICS_ATTR_ID_PCIE_LC_PERF_OTHER_END_RECOVERY,
581 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_INST,
582 AMDGPU_METRICS_ATTR_ID_JPEG_BUSY,
583 AMDGPU_METRICS_ATTR_ID_VCN_BUSY,
584 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_ACC,
585 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_PPT_ACC,
586 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC,
587 AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC,
588 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC,
589 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HBM,
590 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MID,
591 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_AID,
592 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_XCD,
593 AMDGPU_METRICS_ATTR_ID_LABEL_VERSION,
594 AMDGPU_METRICS_ATTR_ID_NODE_ID,
595 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_RETIMER,
596 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC,
597 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC_2,
598 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_VDD18_VR,
599 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_B_VR,
600 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_D_VR,
601 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_A,
602 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_C,
603 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X0,
604 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X1,
605 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_B,
606 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_D,
607 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_B,
608 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_D,
609 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_B,
610 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_D,
611 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_B,
612 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_D,
613 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_A,
614 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_C,
615 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_A,
616 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_C,
617 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_UCIE,
618 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAA,
619 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_A,
620 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_C,
621 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075,
622 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA,
623 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FRONT,
624 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_BACK,
625 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM7,
626 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_IBC,
627 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_UFPGA,
628 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM1,
629 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_HSC,
630 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_2_3_HSC,
631 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_HSC,
632 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_6_7_HSC,
633 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_0V72_VR,
634 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_3V3_VR,
635 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR,
636 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR,
637 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_0V9_VR,
638 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_0V9_VR,
639 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_2_3_0V9_VR,
640 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_6_7_0V9_VR,
641 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR,
642 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR,
643 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC_HSC,
644 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC,
645 AMDGPU_METRICS_ATTR_ID_MAX,
646};
647
648enum amdgpu_metrics_attr_type {
649 AMDGPU_METRICS_TYPE_U8,
650 AMDGPU_METRICS_TYPE_S8,
651 AMDGPU_METRICS_TYPE_U16,
652 AMDGPU_METRICS_TYPE_S16,
653 AMDGPU_METRICS_TYPE_U32,
654 AMDGPU_METRICS_TYPE_S32,
655 AMDGPU_METRICS_TYPE_U64,
656 AMDGPU_METRICS_TYPE_S64,
657 AMDGPU_METRICS_TYPE_MAX,
658};
659
660enum amdgpu_metrics_attr_unit {
661 /* None */
662 AMDGPU_METRICS_UNIT_NONE,
663 /* MHz*/
664 AMDGPU_METRICS_UNIT_CLOCK_1,
665 /* Degree Celsius*/
666 AMDGPU_METRICS_UNIT_TEMP_1,
667 /* Watts*/
668 AMDGPU_METRICS_UNIT_POWER_1,
669 /* In nanoseconds*/
670 AMDGPU_METRICS_UNIT_TIME_1,
671 /* In 10 nanoseconds*/
672 AMDGPU_METRICS_UNIT_TIME_2,
673 /* Speed in GT/s */
674 AMDGPU_METRICS_UNIT_SPEED_1,
675 /* Speed in 0.1 GT/s */
676 AMDGPU_METRICS_UNIT_SPEED_2,
677 /* Bandwidth GB/s */
678 AMDGPU_METRICS_UNIT_BW_1,
679 /* Data in KB */
680 AMDGPU_METRICS_UNIT_DATA_1,
681 /* Percentage */
682 AMDGPU_METRICS_UNIT_PERCENT,
683 AMDGPU_METRICS_UNIT_MAX,
684};
685
686#define AMDGPU_METRICS_ATTR_UNIT_MASK 0xFF000000
687#define AMDGPU_METRICS_ATTR_UNIT_SHIFT 24
688#define AMDGPU_METRICS_ATTR_TYPE_MASK 0x00F00000
689#define AMDGPU_METRICS_ATTR_TYPE_SHIFT 20
690#define AMDGPU_METRICS_ATTR_ID_MASK 0x000FFC00
691#define AMDGPU_METRICS_ATTR_ID_SHIFT 10
692#define AMDGPU_METRICS_ATTR_INST_MASK 0x000003FF
693#define AMDGPU_METRICS_ATTR_INST_SHIFT 0
694
695#define AMDGPU_METRICS_ENC_ATTR(unit, type, id, inst) \
696 (((u64)(unit) << AMDGPU_METRICS_ATTR_UNIT_SHIFT) | \
697 ((u64)(type) << AMDGPU_METRICS_ATTR_TYPE_SHIFT) | \
698 ((u64)(id) << AMDGPU_METRICS_ATTR_ID_SHIFT) | (inst))
699
700/*
701 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
702 * Use gpu_metrics_v1_1 or later instead.
703 */
704struct gpu_metrics_v1_0 {
705 struct metrics_table_header common_header;
706
707 /* Driver attached timestamp (in ns) */
708 uint64_t system_clock_counter;
709
710 /* Temperature */
711 uint16_t temperature_edge;
712 uint16_t temperature_hotspot;
713 uint16_t temperature_mem;
714 uint16_t temperature_vrgfx;
715 uint16_t temperature_vrsoc;
716 uint16_t temperature_vrmem;
717
718 /* Utilization */
719 uint16_t average_gfx_activity;
720 uint16_t average_umc_activity; // memory controller
721 uint16_t average_mm_activity; // UVD or VCN
722
723 /* Power/Energy */
724 uint16_t average_socket_power;
725 uint32_t energy_accumulator;
726
727 /* Average clocks */
728 uint16_t average_gfxclk_frequency;
729 uint16_t average_socclk_frequency;
730 uint16_t average_uclk_frequency;
731 uint16_t average_vclk0_frequency;
732 uint16_t average_dclk0_frequency;
733 uint16_t average_vclk1_frequency;
734 uint16_t average_dclk1_frequency;
735
736 /* Current clocks */
737 uint16_t current_gfxclk;
738 uint16_t current_socclk;
739 uint16_t current_uclk;
740 uint16_t current_vclk0;
741 uint16_t current_dclk0;
742 uint16_t current_vclk1;
743 uint16_t current_dclk1;
744
745 /* Throttle status */
746 uint32_t throttle_status;
747
748 /* Fans */
749 uint16_t current_fan_speed;
750
751 /* Link width/speed */
752 uint8_t pcie_link_width;
753 uint8_t pcie_link_speed; // in 0.1 GT/s
754};
755
756struct gpu_metrics_v1_1 {
757 struct metrics_table_header common_header;
758
759 /* Temperature */
760 uint16_t temperature_edge;
761 uint16_t temperature_hotspot;
762 uint16_t temperature_mem;
763 uint16_t temperature_vrgfx;
764 uint16_t temperature_vrsoc;
765 uint16_t temperature_vrmem;
766
767 /* Utilization */
768 uint16_t average_gfx_activity;
769 uint16_t average_umc_activity; // memory controller
770 uint16_t average_mm_activity; // UVD or VCN
771
772 /* Power/Energy */
773 uint16_t average_socket_power;
774 uint64_t energy_accumulator;
775
776 /* Driver attached timestamp (in ns) */
777 uint64_t system_clock_counter;
778
779 /* Average clocks */
780 uint16_t average_gfxclk_frequency;
781 uint16_t average_socclk_frequency;
782 uint16_t average_uclk_frequency;
783 uint16_t average_vclk0_frequency;
784 uint16_t average_dclk0_frequency;
785 uint16_t average_vclk1_frequency;
786 uint16_t average_dclk1_frequency;
787
788 /* Current clocks */
789 uint16_t current_gfxclk;
790 uint16_t current_socclk;
791 uint16_t current_uclk;
792 uint16_t current_vclk0;
793 uint16_t current_dclk0;
794 uint16_t current_vclk1;
795 uint16_t current_dclk1;
796
797 /* Throttle status */
798 uint32_t throttle_status;
799
800 /* Fans */
801 uint16_t current_fan_speed;
802
803 /* Link width/speed */
804 uint16_t pcie_link_width;
805 uint16_t pcie_link_speed; // in 0.1 GT/s
806
807 uint16_t padding;
808
809 uint32_t gfx_activity_acc;
810 uint32_t mem_activity_acc;
811
812 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
813};
814
815struct gpu_metrics_v1_2 {
816 struct metrics_table_header common_header;
817
818 /* Temperature */
819 uint16_t temperature_edge;
820 uint16_t temperature_hotspot;
821 uint16_t temperature_mem;
822 uint16_t temperature_vrgfx;
823 uint16_t temperature_vrsoc;
824 uint16_t temperature_vrmem;
825
826 /* Utilization */
827 uint16_t average_gfx_activity;
828 uint16_t average_umc_activity; // memory controller
829 uint16_t average_mm_activity; // UVD or VCN
830
831 /* Power/Energy */
832 uint16_t average_socket_power;
833 uint64_t energy_accumulator;
834
835 /* Driver attached timestamp (in ns) */
836 uint64_t system_clock_counter;
837
838 /* Average clocks */
839 uint16_t average_gfxclk_frequency;
840 uint16_t average_socclk_frequency;
841 uint16_t average_uclk_frequency;
842 uint16_t average_vclk0_frequency;
843 uint16_t average_dclk0_frequency;
844 uint16_t average_vclk1_frequency;
845 uint16_t average_dclk1_frequency;
846
847 /* Current clocks */
848 uint16_t current_gfxclk;
849 uint16_t current_socclk;
850 uint16_t current_uclk;
851 uint16_t current_vclk0;
852 uint16_t current_dclk0;
853 uint16_t current_vclk1;
854 uint16_t current_dclk1;
855
856 /* Throttle status (ASIC dependent) */
857 uint32_t throttle_status;
858
859 /* Fans */
860 uint16_t current_fan_speed;
861
862 /* Link width/speed */
863 uint16_t pcie_link_width;
864 uint16_t pcie_link_speed; // in 0.1 GT/s
865
866 uint16_t padding;
867
868 uint32_t gfx_activity_acc;
869 uint32_t mem_activity_acc;
870
871 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
872
873 /* PMFW attached timestamp (10ns resolution) */
874 uint64_t firmware_timestamp;
875};
876
877struct gpu_metrics_v1_3 {
878 struct metrics_table_header common_header;
879
880 /* Temperature */
881 uint16_t temperature_edge;
882 uint16_t temperature_hotspot;
883 uint16_t temperature_mem;
884 uint16_t temperature_vrgfx;
885 uint16_t temperature_vrsoc;
886 uint16_t temperature_vrmem;
887
888 /* Utilization */
889 uint16_t average_gfx_activity;
890 uint16_t average_umc_activity; // memory controller
891 uint16_t average_mm_activity; // UVD or VCN
892
893 /* Power/Energy */
894 uint16_t average_socket_power;
895 uint64_t energy_accumulator;
896
897 /* Driver attached timestamp (in ns) */
898 uint64_t system_clock_counter;
899
900 /* Average clocks */
901 uint16_t average_gfxclk_frequency;
902 uint16_t average_socclk_frequency;
903 uint16_t average_uclk_frequency;
904 uint16_t average_vclk0_frequency;
905 uint16_t average_dclk0_frequency;
906 uint16_t average_vclk1_frequency;
907 uint16_t average_dclk1_frequency;
908
909 /* Current clocks */
910 uint16_t current_gfxclk;
911 uint16_t current_socclk;
912 uint16_t current_uclk;
913 uint16_t current_vclk0;
914 uint16_t current_dclk0;
915 uint16_t current_vclk1;
916 uint16_t current_dclk1;
917
918 /* Throttle status */
919 uint32_t throttle_status;
920
921 /* Fans */
922 uint16_t current_fan_speed;
923
924 /* Link width/speed */
925 uint16_t pcie_link_width;
926 uint16_t pcie_link_speed; // in 0.1 GT/s
927
928 uint16_t padding;
929
930 uint32_t gfx_activity_acc;
931 uint32_t mem_activity_acc;
932
933 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
934
935 /* PMFW attached timestamp (10ns resolution) */
936 uint64_t firmware_timestamp;
937
938 /* Voltage (mV) */
939 uint16_t voltage_soc;
940 uint16_t voltage_gfx;
941 uint16_t voltage_mem;
942
943 uint16_t padding1;
944
945 /* Throttle status (ASIC independent) */
946 uint64_t indep_throttle_status;
947};
948
949struct gpu_metrics_v1_4 {
950 struct metrics_table_header common_header;
951
952 /* Temperature (Celsius) */
953 uint16_t temperature_hotspot;
954 uint16_t temperature_mem;
955 uint16_t temperature_vrsoc;
956
957 /* Power (Watts) */
958 uint16_t curr_socket_power;
959
960 /* Utilization (%) */
961 uint16_t average_gfx_activity;
962 uint16_t average_umc_activity; // memory controller
963 uint16_t vcn_activity[NUM_VCN];
964
965 /* Energy (15.259uJ (2^-16) units) */
966 uint64_t energy_accumulator;
967
968 /* Driver attached timestamp (in ns) */
969 uint64_t system_clock_counter;
970
971 /* Throttle status */
972 uint32_t throttle_status;
973
974 /* Clock Lock Status. Each bit corresponds to clock instance */
975 uint32_t gfxclk_lock_status;
976
977 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
978 uint16_t pcie_link_width;
979 uint16_t pcie_link_speed;
980
981 /* XGMI bus width and bitrate (in Gbps) */
982 uint16_t xgmi_link_width;
983 uint16_t xgmi_link_speed;
984
985 /* Utilization Accumulated (%) */
986 uint32_t gfx_activity_acc;
987 uint32_t mem_activity_acc;
988
989 /*PCIE accumulated bandwidth (GB/sec) */
990 uint64_t pcie_bandwidth_acc;
991
992 /*PCIE instantaneous bandwidth (GB/sec) */
993 uint64_t pcie_bandwidth_inst;
994
995 /* PCIE L0 to recovery state transition accumulated count */
996 uint64_t pcie_l0_to_recov_count_acc;
997
998 /* PCIE replay accumulated count */
999 uint64_t pcie_replay_count_acc;
1000
1001 /* PCIE replay rollover accumulated count */
1002 uint64_t pcie_replay_rover_count_acc;
1003
1004 /* XGMI accumulated data transfer size(KiloBytes) */
1005 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1006 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1007
1008 /* PMFW attached timestamp (10ns resolution) */
1009 uint64_t firmware_timestamp;
1010
1011 /* Current clocks (Mhz) */
1012 uint16_t current_gfxclk[MAX_GFX_CLKS];
1013 uint16_t current_socclk[MAX_CLKS];
1014 uint16_t current_vclk0[MAX_CLKS];
1015 uint16_t current_dclk0[MAX_CLKS];
1016 uint16_t current_uclk;
1017
1018 uint16_t padding;
1019};
1020
1021struct gpu_metrics_v1_5 {
1022 struct metrics_table_header common_header;
1023
1024 /* Temperature (Celsius) */
1025 uint16_t temperature_hotspot;
1026 uint16_t temperature_mem;
1027 uint16_t temperature_vrsoc;
1028
1029 /* Power (Watts) */
1030 uint16_t curr_socket_power;
1031
1032 /* Utilization (%) */
1033 uint16_t average_gfx_activity;
1034 uint16_t average_umc_activity; // memory controller
1035 uint16_t vcn_activity[NUM_VCN];
1036 uint16_t jpeg_activity[NUM_JPEG_ENG];
1037
1038 /* Energy (15.259uJ (2^-16) units) */
1039 uint64_t energy_accumulator;
1040
1041 /* Driver attached timestamp (in ns) */
1042 uint64_t system_clock_counter;
1043
1044 /* Throttle status */
1045 uint32_t throttle_status;
1046
1047 /* Clock Lock Status. Each bit corresponds to clock instance */
1048 uint32_t gfxclk_lock_status;
1049
1050 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
1051 uint16_t pcie_link_width;
1052 uint16_t pcie_link_speed;
1053
1054 /* XGMI bus width and bitrate (in Gbps) */
1055 uint16_t xgmi_link_width;
1056 uint16_t xgmi_link_speed;
1057
1058 /* Utilization Accumulated (%) */
1059 uint32_t gfx_activity_acc;
1060 uint32_t mem_activity_acc;
1061
1062 /*PCIE accumulated bandwidth (GB/sec) */
1063 uint64_t pcie_bandwidth_acc;
1064
1065 /*PCIE instantaneous bandwidth (GB/sec) */
1066 uint64_t pcie_bandwidth_inst;
1067
1068 /* PCIE L0 to recovery state transition accumulated count */
1069 uint64_t pcie_l0_to_recov_count_acc;
1070
1071 /* PCIE replay accumulated count */
1072 uint64_t pcie_replay_count_acc;
1073
1074 /* PCIE replay rollover accumulated count */
1075 uint64_t pcie_replay_rover_count_acc;
1076
1077 /* PCIE NAK sent accumulated count */
1078 uint32_t pcie_nak_sent_count_acc;
1079
1080 /* PCIE NAK received accumulated count */
1081 uint32_t pcie_nak_rcvd_count_acc;
1082
1083 /* XGMI accumulated data transfer size(KiloBytes) */
1084 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1085 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1086
1087 /* PMFW attached timestamp (10ns resolution) */
1088 uint64_t firmware_timestamp;
1089
1090 /* Current clocks (Mhz) */
1091 uint16_t current_gfxclk[MAX_GFX_CLKS];
1092 uint16_t current_socclk[MAX_CLKS];
1093 uint16_t current_vclk0[MAX_CLKS];
1094 uint16_t current_dclk0[MAX_CLKS];
1095 uint16_t current_uclk;
1096
1097 uint16_t padding;
1098};
1099
1100struct gpu_metrics_v1_6 {
1101 struct metrics_table_header common_header;
1102
1103 /* Temperature (Celsius) */
1104 uint16_t temperature_hotspot;
1105 uint16_t temperature_mem;
1106 uint16_t temperature_vrsoc;
1107
1108 /* Power (Watts) */
1109 uint16_t curr_socket_power;
1110
1111 /* Utilization (%) */
1112 uint16_t average_gfx_activity;
1113 uint16_t average_umc_activity; // memory controller
1114
1115 /* Energy (15.259uJ (2^-16) units) */
1116 uint64_t energy_accumulator;
1117
1118 /* Driver attached timestamp (in ns) */
1119 uint64_t system_clock_counter;
1120
1121 /* Accumulation cycle counter */
1122 uint32_t accumulation_counter;
1123
1124 /* Accumulated throttler residencies */
1125 uint32_t prochot_residency_acc;
1126 uint32_t ppt_residency_acc;
1127 uint32_t socket_thm_residency_acc;
1128 uint32_t vr_thm_residency_acc;
1129 uint32_t hbm_thm_residency_acc;
1130
1131 /* Clock Lock Status. Each bit corresponds to clock instance */
1132 uint32_t gfxclk_lock_status;
1133
1134 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
1135 uint16_t pcie_link_width;
1136 uint16_t pcie_link_speed;
1137
1138 /* XGMI bus width and bitrate (in Gbps) */
1139 uint16_t xgmi_link_width;
1140 uint16_t xgmi_link_speed;
1141
1142 /* Utilization Accumulated (%) */
1143 uint32_t gfx_activity_acc;
1144 uint32_t mem_activity_acc;
1145
1146 /*PCIE accumulated bandwidth (GB/sec) */
1147 uint64_t pcie_bandwidth_acc;
1148
1149 /*PCIE instantaneous bandwidth (GB/sec) */
1150 uint64_t pcie_bandwidth_inst;
1151
1152 /* PCIE L0 to recovery state transition accumulated count */
1153 uint64_t pcie_l0_to_recov_count_acc;
1154
1155 /* PCIE replay accumulated count */
1156 uint64_t pcie_replay_count_acc;
1157
1158 /* PCIE replay rollover accumulated count */
1159 uint64_t pcie_replay_rover_count_acc;
1160
1161 /* PCIE NAK sent accumulated count */
1162 uint32_t pcie_nak_sent_count_acc;
1163
1164 /* PCIE NAK received accumulated count */
1165 uint32_t pcie_nak_rcvd_count_acc;
1166
1167 /* XGMI accumulated data transfer size(KiloBytes) */
1168 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1169 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1170
1171 /* PMFW attached timestamp (10ns resolution) */
1172 uint64_t firmware_timestamp;
1173
1174 /* Current clocks (Mhz) */
1175 uint16_t current_gfxclk[MAX_GFX_CLKS];
1176 uint16_t current_socclk[MAX_CLKS];
1177 uint16_t current_vclk0[MAX_CLKS];
1178 uint16_t current_dclk0[MAX_CLKS];
1179 uint16_t current_uclk;
1180
1181 /* Number of current partition */
1182 uint16_t num_partition;
1183
1184 /* XCP metrics stats */
1185 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP];
1186
1187 /* PCIE other end recovery counter */
1188 uint32_t pcie_lc_perf_other_end_recovery;
1189};
1190
1191struct gpu_metrics_v1_7 {
1192 struct metrics_table_header common_header;
1193
1194 /* Temperature (Celsius) */
1195 uint16_t temperature_hotspot;
1196 uint16_t temperature_mem;
1197 uint16_t temperature_vrsoc;
1198
1199 /* Power (Watts) */
1200 uint16_t curr_socket_power;
1201
1202 /* Utilization (%) */
1203 uint16_t average_gfx_activity;
1204 uint16_t average_umc_activity; // memory controller
1205
1206 /* VRAM max bandwidthi (in GB/sec) at max memory clock */
1207 uint64_t mem_max_bandwidth;
1208
1209 /* Energy (15.259uJ (2^-16) units) */
1210 uint64_t energy_accumulator;
1211
1212 /* Driver attached timestamp (in ns) */
1213 uint64_t system_clock_counter;
1214
1215 /* Accumulation cycle counter */
1216 uint32_t accumulation_counter;
1217
1218 /* Accumulated throttler residencies */
1219 uint32_t prochot_residency_acc;
1220 uint32_t ppt_residency_acc;
1221 uint32_t socket_thm_residency_acc;
1222 uint32_t vr_thm_residency_acc;
1223 uint32_t hbm_thm_residency_acc;
1224
1225 /* Clock Lock Status. Each bit corresponds to clock instance */
1226 uint32_t gfxclk_lock_status;
1227
1228 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
1229 uint16_t pcie_link_width;
1230 uint16_t pcie_link_speed;
1231
1232 /* XGMI bus width and bitrate (in Gbps) */
1233 uint16_t xgmi_link_width;
1234 uint16_t xgmi_link_speed;
1235
1236 /* Utilization Accumulated (%) */
1237 uint32_t gfx_activity_acc;
1238 uint32_t mem_activity_acc;
1239
1240 /*PCIE accumulated bandwidth (GB/sec) */
1241 uint64_t pcie_bandwidth_acc;
1242
1243 /*PCIE instantaneous bandwidth (GB/sec) */
1244 uint64_t pcie_bandwidth_inst;
1245
1246 /* PCIE L0 to recovery state transition accumulated count */
1247 uint64_t pcie_l0_to_recov_count_acc;
1248
1249 /* PCIE replay accumulated count */
1250 uint64_t pcie_replay_count_acc;
1251
1252 /* PCIE replay rollover accumulated count */
1253 uint64_t pcie_replay_rover_count_acc;
1254
1255 /* PCIE NAK sent accumulated count */
1256 uint32_t pcie_nak_sent_count_acc;
1257
1258 /* PCIE NAK received accumulated count */
1259 uint32_t pcie_nak_rcvd_count_acc;
1260
1261 /* XGMI accumulated data transfer size(KiloBytes) */
1262 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1263 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1264
1265 /* XGMI link status(active/inactive) */
1266 uint16_t xgmi_link_status[NUM_XGMI_LINKS];
1267
1268 uint16_t padding;
1269
1270 /* PMFW attached timestamp (10ns resolution) */
1271 uint64_t firmware_timestamp;
1272
1273 /* Current clocks (Mhz) */
1274 uint16_t current_gfxclk[MAX_GFX_CLKS];
1275 uint16_t current_socclk[MAX_CLKS];
1276 uint16_t current_vclk0[MAX_CLKS];
1277 uint16_t current_dclk0[MAX_CLKS];
1278 uint16_t current_uclk;
1279
1280 /* Number of current partition */
1281 uint16_t num_partition;
1282
1283 /* XCP metrics stats */
1284 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP];
1285
1286 /* PCIE other end recovery counter */
1287 uint32_t pcie_lc_perf_other_end_recovery;
1288};
1289
1290struct gpu_metrics_v1_8 {
1291 struct metrics_table_header common_header;
1292
1293 /* Temperature (Celsius) */
1294 uint16_t temperature_hotspot;
1295 uint16_t temperature_mem;
1296 uint16_t temperature_vrsoc;
1297
1298 /* Power (Watts) */
1299 uint16_t curr_socket_power;
1300
1301 /* Utilization (%) */
1302 uint16_t average_gfx_activity;
1303 uint16_t average_umc_activity; // memory controller
1304
1305 /* VRAM max bandwidthi (in GB/sec) at max memory clock */
1306 uint64_t mem_max_bandwidth;
1307
1308 /* Energy (15.259uJ (2^-16) units) */
1309 uint64_t energy_accumulator;
1310
1311 /* Driver attached timestamp (in ns) */
1312 uint64_t system_clock_counter;
1313
1314 /* Accumulation cycle counter */
1315 uint32_t accumulation_counter;
1316
1317 /* Accumulated throttler residencies */
1318 uint32_t prochot_residency_acc;
1319 uint32_t ppt_residency_acc;
1320 uint32_t socket_thm_residency_acc;
1321 uint32_t vr_thm_residency_acc;
1322 uint32_t hbm_thm_residency_acc;
1323
1324 /* Clock Lock Status. Each bit corresponds to clock instance */
1325 uint32_t gfxclk_lock_status;
1326
1327 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
1328 uint16_t pcie_link_width;
1329 uint16_t pcie_link_speed;
1330
1331 /* XGMI bus width and bitrate (in Gbps) */
1332 uint16_t xgmi_link_width;
1333 uint16_t xgmi_link_speed;
1334
1335 /* Utilization Accumulated (%) */
1336 uint32_t gfx_activity_acc;
1337 uint32_t mem_activity_acc;
1338
1339 /*PCIE accumulated bandwidth (GB/sec) */
1340 uint64_t pcie_bandwidth_acc;
1341
1342 /*PCIE instantaneous bandwidth (GB/sec) */
1343 uint64_t pcie_bandwidth_inst;
1344
1345 /* PCIE L0 to recovery state transition accumulated count */
1346 uint64_t pcie_l0_to_recov_count_acc;
1347
1348 /* PCIE replay accumulated count */
1349 uint64_t pcie_replay_count_acc;
1350
1351 /* PCIE replay rollover accumulated count */
1352 uint64_t pcie_replay_rover_count_acc;
1353
1354 /* PCIE NAK sent accumulated count */
1355 uint32_t pcie_nak_sent_count_acc;
1356
1357 /* PCIE NAK received accumulated count */
1358 uint32_t pcie_nak_rcvd_count_acc;
1359
1360 /* XGMI accumulated data transfer size(KiloBytes) */
1361 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1362 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1363
1364 /* XGMI link status(active/inactive) */
1365 uint16_t xgmi_link_status[NUM_XGMI_LINKS];
1366
1367 uint16_t padding;
1368
1369 /* PMFW attached timestamp (10ns resolution) */
1370 uint64_t firmware_timestamp;
1371
1372 /* Current clocks (Mhz) */
1373 uint16_t current_gfxclk[MAX_GFX_CLKS];
1374 uint16_t current_socclk[MAX_CLKS];
1375 uint16_t current_vclk0[MAX_CLKS];
1376 uint16_t current_dclk0[MAX_CLKS];
1377 uint16_t current_uclk;
1378
1379 /* Number of current partition */
1380 uint16_t num_partition;
1381
1382 /* XCP metrics stats */
1383 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP];
1384
1385 /* PCIE other end recovery counter */
1386 uint32_t pcie_lc_perf_other_end_recovery;
1387};
1388
1389struct gpu_metrics_attr {
1390 /* Field type encoded with AMDGPU_METRICS_ENC_ATTR */
1391 uint64_t attr_encoding;
1392 /* Attribute value, depends on attr_encoding */
1393 void *attr_value;
1394};
1395
1396struct gpu_metrics_v1_9 {
1397 struct metrics_table_header common_header;
1398 int attr_count;
1399 struct gpu_metrics_attr metrics_attrs[];
1400};
1401
1402/*
1403 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
1404 * Use gpu_metrics_v2_1 or later instead.
1405 */
1406struct gpu_metrics_v2_0 {
1407 struct metrics_table_header common_header;
1408
1409 /* Driver attached timestamp (in ns) */
1410 uint64_t system_clock_counter;
1411
1412 /* Temperature */
1413 uint16_t temperature_gfx; // gfx temperature on APUs
1414 uint16_t temperature_soc; // soc temperature on APUs
1415 uint16_t temperature_core[8]; // CPU core temperature on APUs
1416 uint16_t temperature_l3[2];
1417
1418 /* Utilization */
1419 uint16_t average_gfx_activity;
1420 uint16_t average_mm_activity; // UVD or VCN
1421
1422 /* Power/Energy */
1423 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1424 uint16_t average_cpu_power;
1425 uint16_t average_soc_power;
1426 uint16_t average_gfx_power;
1427 uint16_t average_core_power[8]; // CPU core power on APUs
1428
1429 /* Average clocks */
1430 uint16_t average_gfxclk_frequency;
1431 uint16_t average_socclk_frequency;
1432 uint16_t average_uclk_frequency;
1433 uint16_t average_fclk_frequency;
1434 uint16_t average_vclk_frequency;
1435 uint16_t average_dclk_frequency;
1436
1437 /* Current clocks */
1438 uint16_t current_gfxclk;
1439 uint16_t current_socclk;
1440 uint16_t current_uclk;
1441 uint16_t current_fclk;
1442 uint16_t current_vclk;
1443 uint16_t current_dclk;
1444 uint16_t current_coreclk[8]; // CPU core clocks
1445 uint16_t current_l3clk[2];
1446
1447 /* Throttle status */
1448 uint32_t throttle_status;
1449
1450 /* Fans */
1451 uint16_t fan_pwm;
1452
1453 uint16_t padding;
1454};
1455
1456struct gpu_metrics_v2_1 {
1457 struct metrics_table_header common_header;
1458
1459 /* Temperature */
1460 uint16_t temperature_gfx; // gfx temperature on APUs
1461 uint16_t temperature_soc; // soc temperature on APUs
1462 uint16_t temperature_core[8]; // CPU core temperature on APUs
1463 uint16_t temperature_l3[2];
1464
1465 /* Utilization */
1466 uint16_t average_gfx_activity;
1467 uint16_t average_mm_activity; // UVD or VCN
1468
1469 /* Driver attached timestamp (in ns) */
1470 uint64_t system_clock_counter;
1471
1472 /* Power/Energy */
1473 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1474 uint16_t average_cpu_power;
1475 uint16_t average_soc_power;
1476 uint16_t average_gfx_power;
1477 uint16_t average_core_power[8]; // CPU core power on APUs
1478
1479 /* Average clocks */
1480 uint16_t average_gfxclk_frequency;
1481 uint16_t average_socclk_frequency;
1482 uint16_t average_uclk_frequency;
1483 uint16_t average_fclk_frequency;
1484 uint16_t average_vclk_frequency;
1485 uint16_t average_dclk_frequency;
1486
1487 /* Current clocks */
1488 uint16_t current_gfxclk;
1489 uint16_t current_socclk;
1490 uint16_t current_uclk;
1491 uint16_t current_fclk;
1492 uint16_t current_vclk;
1493 uint16_t current_dclk;
1494 uint16_t current_coreclk[8]; // CPU core clocks
1495 uint16_t current_l3clk[2];
1496
1497 /* Throttle status */
1498 uint32_t throttle_status;
1499
1500 /* Fans */
1501 uint16_t fan_pwm;
1502
1503 uint16_t padding[3];
1504};
1505
1506struct gpu_metrics_v2_2 {
1507 struct metrics_table_header common_header;
1508
1509 /* Temperature */
1510 uint16_t temperature_gfx; // gfx temperature on APUs
1511 uint16_t temperature_soc; // soc temperature on APUs
1512 uint16_t temperature_core[8]; // CPU core temperature on APUs
1513 uint16_t temperature_l3[2];
1514
1515 /* Utilization */
1516 uint16_t average_gfx_activity;
1517 uint16_t average_mm_activity; // UVD or VCN
1518
1519 /* Driver attached timestamp (in ns) */
1520 uint64_t system_clock_counter;
1521
1522 /* Power/Energy */
1523 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1524 uint16_t average_cpu_power;
1525 uint16_t average_soc_power;
1526 uint16_t average_gfx_power;
1527 uint16_t average_core_power[8]; // CPU core power on APUs
1528
1529 /* Average clocks */
1530 uint16_t average_gfxclk_frequency;
1531 uint16_t average_socclk_frequency;
1532 uint16_t average_uclk_frequency;
1533 uint16_t average_fclk_frequency;
1534 uint16_t average_vclk_frequency;
1535 uint16_t average_dclk_frequency;
1536
1537 /* Current clocks */
1538 uint16_t current_gfxclk;
1539 uint16_t current_socclk;
1540 uint16_t current_uclk;
1541 uint16_t current_fclk;
1542 uint16_t current_vclk;
1543 uint16_t current_dclk;
1544 uint16_t current_coreclk[8]; // CPU core clocks
1545 uint16_t current_l3clk[2];
1546
1547 /* Throttle status (ASIC dependent) */
1548 uint32_t throttle_status;
1549
1550 /* Fans */
1551 uint16_t fan_pwm;
1552
1553 uint16_t padding[3];
1554
1555 /* Throttle status (ASIC independent) */
1556 uint64_t indep_throttle_status;
1557};
1558
1559struct gpu_metrics_v2_3 {
1560 struct metrics_table_header common_header;
1561
1562 /* Temperature */
1563 uint16_t temperature_gfx; // gfx temperature on APUs
1564 uint16_t temperature_soc; // soc temperature on APUs
1565 uint16_t temperature_core[8]; // CPU core temperature on APUs
1566 uint16_t temperature_l3[2];
1567
1568 /* Utilization */
1569 uint16_t average_gfx_activity;
1570 uint16_t average_mm_activity; // UVD or VCN
1571
1572 /* Driver attached timestamp (in ns) */
1573 uint64_t system_clock_counter;
1574
1575 /* Power/Energy */
1576 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1577 uint16_t average_cpu_power;
1578 uint16_t average_soc_power;
1579 uint16_t average_gfx_power;
1580 uint16_t average_core_power[8]; // CPU core power on APUs
1581
1582 /* Average clocks */
1583 uint16_t average_gfxclk_frequency;
1584 uint16_t average_socclk_frequency;
1585 uint16_t average_uclk_frequency;
1586 uint16_t average_fclk_frequency;
1587 uint16_t average_vclk_frequency;
1588 uint16_t average_dclk_frequency;
1589
1590 /* Current clocks */
1591 uint16_t current_gfxclk;
1592 uint16_t current_socclk;
1593 uint16_t current_uclk;
1594 uint16_t current_fclk;
1595 uint16_t current_vclk;
1596 uint16_t current_dclk;
1597 uint16_t current_coreclk[8]; // CPU core clocks
1598 uint16_t current_l3clk[2];
1599
1600 /* Throttle status (ASIC dependent) */
1601 uint32_t throttle_status;
1602
1603 /* Fans */
1604 uint16_t fan_pwm;
1605
1606 uint16_t padding[3];
1607
1608 /* Throttle status (ASIC independent) */
1609 uint64_t indep_throttle_status;
1610
1611 /* Average Temperature */
1612 uint16_t average_temperature_gfx; // average gfx temperature on APUs
1613 uint16_t average_temperature_soc; // average soc temperature on APUs
1614 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs
1615 uint16_t average_temperature_l3[2];
1616};
1617
1618struct gpu_metrics_v2_4 {
1619 struct metrics_table_header common_header;
1620
1621 /* Temperature (unit: centi-Celsius) */
1622 uint16_t temperature_gfx;
1623 uint16_t temperature_soc;
1624 uint16_t temperature_core[8];
1625 uint16_t temperature_l3[2];
1626
1627 /* Utilization (unit: centi) */
1628 uint16_t average_gfx_activity;
1629 uint16_t average_mm_activity;
1630
1631 /* Driver attached timestamp (in ns) */
1632 uint64_t system_clock_counter;
1633
1634 /* Power/Energy (unit: mW) */
1635 uint16_t average_socket_power;
1636 uint16_t average_cpu_power;
1637 uint16_t average_soc_power;
1638 uint16_t average_gfx_power;
1639 uint16_t average_core_power[8];
1640
1641 /* Average clocks (unit: MHz) */
1642 uint16_t average_gfxclk_frequency;
1643 uint16_t average_socclk_frequency;
1644 uint16_t average_uclk_frequency;
1645 uint16_t average_fclk_frequency;
1646 uint16_t average_vclk_frequency;
1647 uint16_t average_dclk_frequency;
1648
1649 /* Current clocks (unit: MHz) */
1650 uint16_t current_gfxclk;
1651 uint16_t current_socclk;
1652 uint16_t current_uclk;
1653 uint16_t current_fclk;
1654 uint16_t current_vclk;
1655 uint16_t current_dclk;
1656 uint16_t current_coreclk[8];
1657 uint16_t current_l3clk[2];
1658
1659 /* Throttle status (ASIC dependent) */
1660 uint32_t throttle_status;
1661
1662 /* Fans */
1663 uint16_t fan_pwm;
1664
1665 uint16_t padding[3];
1666
1667 /* Throttle status (ASIC independent) */
1668 uint64_t indep_throttle_status;
1669
1670 /* Average Temperature (unit: centi-Celsius) */
1671 uint16_t average_temperature_gfx;
1672 uint16_t average_temperature_soc;
1673 uint16_t average_temperature_core[8];
1674 uint16_t average_temperature_l3[2];
1675
1676 /* Power/Voltage (unit: mV) */
1677 uint16_t average_cpu_voltage;
1678 uint16_t average_soc_voltage;
1679 uint16_t average_gfx_voltage;
1680
1681 /* Power/Current (unit: mA) */
1682 uint16_t average_cpu_current;
1683 uint16_t average_soc_current;
1684 uint16_t average_gfx_current;
1685};
1686
1687struct gpu_metrics_v3_0 {
1688 struct metrics_table_header common_header;
1689
1690 /* Temperature */
1691 /* gfx temperature on APUs */
1692 uint16_t temperature_gfx;
1693 /* soc temperature on APUs */
1694 uint16_t temperature_soc;
1695 /* CPU core temperature on APUs */
1696 uint16_t temperature_core[16];
1697 /* skin temperature on APUs */
1698 uint16_t temperature_skin;
1699
1700 /* Utilization */
1701 /* time filtered GFX busy % [0-100] */
1702 uint16_t average_gfx_activity;
1703 /* time filtered VCN busy % [0-100] */
1704 uint16_t average_vcn_activity;
1705 /* time filtered IPU per-column busy % [0-100] */
1706 uint16_t average_ipu_activity[8];
1707 /* time filtered per-core C0 residency % [0-100]*/
1708 uint16_t average_core_c0_activity[16];
1709 /* time filtered DRAM read bandwidth [MB/sec] */
1710 uint16_t average_dram_reads;
1711 /* time filtered DRAM write bandwidth [MB/sec] */
1712 uint16_t average_dram_writes;
1713 /* time filtered IPU read bandwidth [MB/sec] */
1714 uint16_t average_ipu_reads;
1715 /* time filtered IPU write bandwidth [MB/sec] */
1716 uint16_t average_ipu_writes;
1717
1718 /* Driver attached timestamp (in ns) */
1719 uint64_t system_clock_counter;
1720
1721 /* Power/Energy */
1722 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1723 uint32_t average_socket_power;
1724 /* time filtered IPU power [mW] */
1725 uint16_t average_ipu_power;
1726 /* time filtered APU power [mW] */
1727 uint32_t average_apu_power;
1728 /* time filtered GFX power [mW] */
1729 uint32_t average_gfx_power;
1730 /* time filtered dGPU power [mW] */
1731 uint32_t average_dgpu_power;
1732 /* time filtered sum of core power across all cores in the socket [mW] */
1733 uint32_t average_all_core_power;
1734 /* calculated core power [mW] */
1735 uint16_t average_core_power[16];
1736 /* time filtered total system power [mW] */
1737 uint16_t average_sys_power;
1738 /* maximum IRM defined STAPM power limit [mW] */
1739 uint16_t stapm_power_limit;
1740 /* time filtered STAPM power limit [mW] */
1741 uint16_t current_stapm_power_limit;
1742
1743 /* time filtered clocks [MHz] */
1744 uint16_t average_gfxclk_frequency;
1745 uint16_t average_socclk_frequency;
1746 uint16_t average_vpeclk_frequency;
1747 uint16_t average_ipuclk_frequency;
1748 uint16_t average_fclk_frequency;
1749 uint16_t average_vclk_frequency;
1750 uint16_t average_uclk_frequency;
1751 uint16_t average_mpipu_frequency;
1752
1753 /* Current clocks */
1754 /* target core frequency [MHz] */
1755 uint16_t current_coreclk[16];
1756 /* CCLK frequency limit enforced on classic cores [MHz] */
1757 uint16_t current_core_maxfreq;
1758 /* GFXCLK frequency limit enforced on GFX [MHz] */
1759 uint16_t current_gfx_maxfreq;
1760
1761 /* Throttle Residency (ASIC dependent) */
1762 uint32_t throttle_residency_prochot;
1763 uint32_t throttle_residency_spl;
1764 uint32_t throttle_residency_fppt;
1765 uint32_t throttle_residency_sppt;
1766 uint32_t throttle_residency_thm_core;
1767 uint32_t throttle_residency_thm_gfx;
1768 uint32_t throttle_residency_thm_soc;
1769
1770 /* Metrics table alpha filter time constant [us] */
1771 uint32_t time_filter_alphavalue;
1772};
1773
1774struct amdgpu_pmmetrics_header {
1775 uint16_t structure_size;
1776 uint16_t pad;
1777 uint32_t mp1_ip_discovery_version;
1778 uint32_t pmfw_version;
1779 uint32_t pmmetrics_version;
1780};
1781
1782struct amdgpu_pm_metrics {
1783 struct amdgpu_pmmetrics_header common_header;
1784
1785 uint8_t data[];
1786};
1787
1788enum amdgpu_vr_temp {
1789 AMDGPU_VDDCR_VDD0_TEMP,
1790 AMDGPU_VDDCR_VDD1_TEMP,
1791 AMDGPU_VDDCR_VDD2_TEMP,
1792 AMDGPU_VDDCR_VDD3_TEMP,
1793 AMDGPU_VDDCR_SOC_A_TEMP,
1794 AMDGPU_VDDCR_SOC_C_TEMP,
1795 AMDGPU_VDDCR_SOCIO_A_TEMP,
1796 AMDGPU_VDDCR_SOCIO_C_TEMP,
1797 AMDGPU_VDD_085_HBM_TEMP,
1798 AMDGPU_VDDCR_11_HBM_B_TEMP,
1799 AMDGPU_VDDCR_11_HBM_D_TEMP,
1800 AMDGPU_VDD_USR_TEMP,
1801 AMDGPU_VDDIO_11_E32_TEMP,
1802 AMDGPU_VR_MAX_TEMP_ENTRIES,
1803};
1804
1805enum amdgpu_system_temp {
1806 AMDGPU_UBB_FPGA_TEMP,
1807 AMDGPU_UBB_FRONT_TEMP,
1808 AMDGPU_UBB_BACK_TEMP,
1809 AMDGPU_UBB_OAM7_TEMP,
1810 AMDGPU_UBB_IBC_TEMP,
1811 AMDGPU_UBB_UFPGA_TEMP,
1812 AMDGPU_UBB_OAM1_TEMP,
1813 AMDGPU_OAM_0_1_HSC_TEMP,
1814 AMDGPU_OAM_2_3_HSC_TEMP,
1815 AMDGPU_OAM_4_5_HSC_TEMP,
1816 AMDGPU_OAM_6_7_HSC_TEMP,
1817 AMDGPU_UBB_FPGA_0V72_VR_TEMP,
1818 AMDGPU_UBB_FPGA_3V3_VR_TEMP,
1819 AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP,
1820 AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP,
1821 AMDGPU_RETIMER_0_1_0V9_VR_TEMP,
1822 AMDGPU_RETIMER_4_5_0V9_VR_TEMP,
1823 AMDGPU_RETIMER_2_3_0V9_VR_TEMP,
1824 AMDGPU_RETIMER_6_7_0V9_VR_TEMP,
1825 AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP,
1826 AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP,
1827 AMDGPU_IBC_HSC_TEMP,
1828 AMDGPU_IBC_TEMP,
1829 AMDGPU_SYSTEM_MAX_TEMP_ENTRIES = 32,
1830};
1831
1832enum amdgpu_node_temp {
1833 AMDGPU_RETIMER_X_TEMP,
1834 AMDGPU_OAM_X_IBC_TEMP,
1835 AMDGPU_OAM_X_IBC_2_TEMP,
1836 AMDGPU_OAM_X_VDD18_VR_TEMP,
1837 AMDGPU_OAM_X_04_HBM_B_VR_TEMP,
1838 AMDGPU_OAM_X_04_HBM_D_VR_TEMP,
1839 AMDGPU_NODE_MAX_TEMP_ENTRIES = 12,
1840};
1841
1842struct amdgpu_gpuboard_temp_metrics_v1_0 {
1843 struct metrics_table_header common_header;
1844 uint16_t label_version;
1845 uint16_t node_id;
1846 uint64_t accumulation_counter;
1847 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */
1848 uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES];
1849 uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES];
1850};
1851
1852struct amdgpu_baseboard_temp_metrics_v1_0 {
1853 struct metrics_table_header common_header;
1854 uint16_t label_version;
1855 uint16_t node_id;
1856 uint64_t accumulation_counter;
1857 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */
1858 uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES];
1859};
1860
1861struct amdgpu_partition_metrics_v1_0 {
1862 struct metrics_table_header common_header;
1863 /* Current clocks (Mhz) */
1864 uint16_t current_gfxclk[MAX_XCC];
1865 uint16_t current_socclk[MAX_CLKS];
1866 uint16_t current_vclk0[MAX_CLKS];
1867 uint16_t current_dclk0[MAX_CLKS];
1868 uint16_t current_uclk;
1869 uint16_t padding;
1870
1871 /* Utilization Instantaneous (%) */
1872 uint32_t gfx_busy_inst[MAX_XCC];
1873 uint16_t jpeg_busy[NUM_JPEG_ENG_V1];
1874 uint16_t vcn_busy[NUM_VCN];
1875 /* Utilization Accumulated (%) */
1876 uint64_t gfx_busy_acc[MAX_XCC];
1877 /* Total App Clock Counter Accumulated */
1878 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC];
1879 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC];
1880 uint64_t gfx_low_utilization_acc[MAX_XCC];
1881 uint64_t gfx_below_host_limit_total_acc[MAX_XCC];
1882};
1883
1884struct amdgpu_partition_metrics_v1_1 {
1885 struct metrics_table_header common_header;
1886 int attr_count;
1887 struct gpu_metrics_attr metrics_attrs[];
1888};
1889
1890enum amdgpu_xgmi_link_status {
1891 AMDGPU_XGMI_LINK_INACTIVE = 0,
1892 AMDGPU_XGMI_LINK_ACTIVE = 1,
1893 /* Status not available */
1894 AMDGPU_XGMI_LINK_NA = 2,
1895};
1896
1897struct amdgpu_gpuboard_temp_metrics_v1_1 {
1898 struct metrics_table_header common_header;
1899 int attr_count;
1900 struct gpu_metrics_attr metrics_attrs[];
1901};
1902
1903struct amdgpu_baseboard_temp_metrics_v1_1 {
1904 struct metrics_table_header common_header;
1905 int attr_count;
1906 struct gpu_metrics_attr metrics_attrs[];
1907};
1908
1909#endif