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1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __MES_API_DEF_H__
25#define __MES_API_DEF_H__
26
27#pragma pack(push, 4)
28
29#define MES_API_VERSION 1
30
31/* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG */
32#define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000
33
34/* Driver submits one API(cmd) as a single Frame and this command size is same
35 * for all API to ease the debugging and parsing of ring buffer.
36 */
37enum { API_FRAME_SIZE_IN_DWORDS = 64 };
38
39/* To avoid command in scheduler context to be overwritten whenenver mutilple
40 * interrupts come in, this creates another queue.
41 */
42enum { API_NUMBER_OF_COMMAND_MAX = 32 };
43
44enum MES_API_TYPE {
45 MES_API_TYPE_SCHEDULER = 1,
46 MES_API_TYPE_MAX
47};
48
49enum MES_SCH_API_OPCODE {
50 MES_SCH_API_SET_HW_RSRC = 0,
51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
52 MES_SCH_API_ADD_QUEUE = 2,
53 MES_SCH_API_REMOVE_QUEUE = 3,
54 MES_SCH_API_PERFORM_YIELD = 4,
55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5,
56 MES_SCH_API_SUSPEND = 6,
57 MES_SCH_API_RESUME = 7,
58 MES_SCH_API_RESET = 8,
59 MES_SCH_API_SET_LOG_BUFFER = 9,
60 MES_SCH_API_CHANGE_GANG_PRORITY = 10,
61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
62 MES_SCH_API_PROGRAM_GDS = 12,
63 MES_SCH_API_SET_DEBUG_VMID = 13,
64 MES_SCH_API_MISC = 14,
65 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
66 MES_SCH_API_AMD_LOG = 16,
67 MES_SCH_API_SET_HW_RSRC_1 = 19,
68 MES_SCH_API_MAX = 0xFF
69};
70
71union MES_API_HEADER {
72 struct {
73 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
74 uint32_t opcode : 8;
75 uint32_t dwsize : 8; /* including header */
76 uint32_t reserved : 12;
77 };
78
79 uint32_t u32All;
80};
81
82enum MES_AMD_PRIORITY_LEVEL {
83 AMD_PRIORITY_LEVEL_LOW = 0,
84 AMD_PRIORITY_LEVEL_NORMAL = 1,
85 AMD_PRIORITY_LEVEL_MEDIUM = 2,
86 AMD_PRIORITY_LEVEL_HIGH = 3,
87 AMD_PRIORITY_LEVEL_REALTIME = 4,
88 AMD_PRIORITY_NUM_LEVELS
89};
90
91enum MES_QUEUE_TYPE {
92 MES_QUEUE_TYPE_GFX,
93 MES_QUEUE_TYPE_COMPUTE,
94 MES_QUEUE_TYPE_SDMA,
95 MES_QUEUE_TYPE_MAX,
96};
97
98struct MES_API_STATUS {
99 uint64_t api_completion_fence_addr;
100 uint64_t api_completion_fence_value;
101};
102
103enum { MAX_COMPUTE_PIPES = 8 };
104enum { MAX_GFX_PIPES = 2 };
105enum { MAX_SDMA_PIPES = 2 };
106
107enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
108enum { MAX_GFX_HQD_PER_PIPE = 8 };
109enum { MAX_SDMA_HQD_PER_PIPE = 10 };
110enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 };
111
112enum { MAX_QUEUES_IN_A_GANG = 8 };
113
114enum VM_HUB_TYPE {
115 VM_HUB_TYPE_GC = 0,
116 VM_HUB_TYPE_MM = 1,
117 VM_HUB_TYPE_MAX,
118};
119
120enum { VMID_INVALID = 0xffff };
121
122enum { MAX_VMID_GCHUB = 16 };
123enum { MAX_VMID_MMHUB = 16 };
124
125enum SET_DEBUG_VMID_OPERATIONS {
126 DEBUG_VMID_OP_PROGRAM = 0,
127 DEBUG_VMID_OP_ALLOCATE = 1,
128 DEBUG_VMID_OP_RELEASE = 2
129};
130
131enum MES_LOG_OPERATION {
132 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
133 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
134 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
135 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
136 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
137 MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
138};
139
140enum MES_LOG_CONTEXT_STATE {
141 MES_LOG_CONTEXT_STATE_IDLE = 0,
142 MES_LOG_CONTEXT_STATE_RUNNING = 1,
143 MES_LOG_CONTEXT_STATE_READY = 2,
144 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
145 MES_LOG_CONTEXT_STATE_INVALID = 0xF,
146};
147
148struct MES_LOG_CONTEXT_STATE_CHANGE {
149 void *h_context;
150 enum MES_LOG_CONTEXT_STATE new_context_state;
151};
152
153struct MES_LOG_QUEUE_NEW_WORK {
154 uint64_t h_queue;
155 uint64_t reserved;
156};
157
158struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
159 uint64_t h_queue;
160 uint64_t h_sync_object;
161};
162
163struct MES_LOG_QUEUE_NO_MORE_WORK {
164 uint64_t h_queue;
165 uint64_t reserved;
166};
167
168struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
169 uint64_t h_queue;
170 uint64_t h_sync_object;
171};
172
173struct MES_LOG_ENTRY_HEADER {
174 uint32_t first_free_entry_index;
175 uint32_t wraparound_count;
176 uint64_t number_of_entries;
177 uint64_t reserved[2];
178};
179
180struct MES_LOG_ENTRY_DATA {
181 uint64_t gpu_time_stamp;
182 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
183 uint32_t reserved_operation_type_bits;
184 union {
185 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
186 struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
187 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
188 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
189 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
190 uint64_t all[2];
191 };
192};
193
194struct MES_LOG_BUFFER {
195 struct MES_LOG_ENTRY_HEADER header;
196 struct MES_LOG_ENTRY_DATA entries[1];
197};
198
199enum MES_SWIP_TO_HWIP_DEF {
200 MES_MAX_HWIP_SEGMENT = 8,
201};
202
203union MESAPI_SET_HW_RESOURCES {
204 struct {
205 union MES_API_HEADER header;
206 uint32_t vmid_mask_mmhub;
207 uint32_t vmid_mask_gfxhub;
208 uint32_t gds_size;
209 uint32_t paging_vmid;
210 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
211 uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
212 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
213 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
214 uint64_t g_sch_ctx_gpu_mc_ptr;
215 uint64_t query_status_fence_gpu_mc_ptr;
216 uint32_t gc_base[MES_MAX_HWIP_SEGMENT];
217 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];
218 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];
219 struct MES_API_STATUS api_status;
220 union {
221 struct {
222 uint32_t disable_reset : 1;
223 uint32_t use_different_vmid_compute : 1;
224 uint32_t disable_mes_log : 1;
225 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
226 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
227 uint32_t second_gfx_pipe_enabled : 1;
228 uint32_t enable_level_process_quantum_check : 1;
229 uint32_t legacy_sch_mode : 1;
230 uint32_t disable_add_queue_wptr_mc_addr : 1;
231 uint32_t enable_mes_event_int_logging : 1;
232 uint32_t enable_reg_active_poll : 1;
233 uint32_t use_disable_queue_in_legacy_uq_preemption : 1;
234 uint32_t send_write_data : 1;
235 uint32_t os_tdr_timeout_override : 1;
236 uint32_t use_rs64mem_for_proc_gang_ctx : 1;
237 uint32_t use_add_queue_unmap_flag_addr : 1;
238 uint32_t enable_mes_sch_stb_log : 1;
239 uint32_t limit_single_process : 1;
240 uint32_t is_strix_tmz_wa_enabled :1;
241 uint32_t enable_lr_compute_wa : 2;
242 uint32_t enable_compute_pipe_reset : 1;
243 uint32_t reserved : 10;
244 };
245 uint32_t uint32_t_all;
246 };
247 uint32_t oversubscription_timer;
248 uint64_t doorbell_info;
249 uint64_t event_intr_history_gpu_mc_ptr;
250 uint64_t timestamp;
251 uint32_t os_tdr_timeout_in_sec;
252 };
253
254 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
255};
256
257union MESAPI_SET_HW_RESOURCES_1 {
258 struct {
259 union MES_API_HEADER header;
260 struct MES_API_STATUS api_status;
261 uint64_t timestamp;
262 union {
263 struct {
264 uint32_t enable_mes_info_ctx : 1;
265 uint32_t reserved : 31;
266 };
267 uint32_t uint32_all;
268 };
269 uint64_t mes_info_ctx_mc_addr;
270 uint32_t mes_info_ctx_size;
271 uint64_t reserved1;
272 uint64_t cleaner_shader_fence_mc_addr;
273 };
274
275 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
276};
277
278union MESAPI__ADD_QUEUE {
279 struct {
280 union MES_API_HEADER header;
281 uint32_t process_id;
282 uint64_t page_table_base_addr;
283 uint64_t process_va_start;
284 uint64_t process_va_end;
285 uint64_t process_quantum;
286 uint64_t process_context_addr;
287 uint64_t gang_quantum;
288 uint64_t gang_context_addr;
289 uint32_t inprocess_gang_priority;
290 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
291 uint32_t doorbell_offset;
292 uint64_t mqd_addr;
293 uint64_t wptr_addr;
294 uint64_t h_context;
295 uint64_t h_queue;
296 enum MES_QUEUE_TYPE queue_type;
297 uint32_t gds_base;
298 uint32_t gds_size;
299 uint32_t gws_base;
300 uint32_t gws_size;
301 uint32_t oa_mask;
302 uint64_t trap_handler_addr;
303 uint32_t vm_context_cntl;
304
305 struct {
306 uint32_t paging : 1;
307 uint32_t debug_vmid : 4;
308 uint32_t program_gds : 1;
309 uint32_t is_gang_suspended : 1;
310 uint32_t is_tmz_queue : 1;
311 uint32_t map_kiq_utility_queue : 1;
312 uint32_t is_kfd_process : 1;
313 uint32_t trap_en : 1;
314 uint32_t is_aql_queue : 1;
315 uint32_t skip_process_ctx_clear : 1;
316 uint32_t map_legacy_kq : 1;
317 uint32_t exclusively_scheduled : 1;
318 uint32_t is_long_running : 1;
319 uint32_t is_dwm_queue : 1;
320 uint32_t is_video_blit_queue : 1;
321 uint32_t reserved : 14;
322 };
323 struct MES_API_STATUS api_status;
324 uint64_t tma_addr;
325 uint32_t sch_id;
326 uint64_t timestamp;
327 uint32_t process_context_array_index;
328 uint32_t gang_context_array_index;
329 uint32_t pipe_id;
330 uint32_t queue_id;
331 uint32_t alignment_mode_setting;
332 uint32_t full_sh_mem_config_data;
333 uint64_t unmap_flag_addr;
334 };
335
336 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
337};
338
339union MESAPI__REMOVE_QUEUE {
340 struct {
341 union MES_API_HEADER header;
342 uint32_t doorbell_offset;
343 uint64_t gang_context_addr;
344
345 struct {
346 uint32_t unmap_legacy_gfx_queue : 1;
347 uint32_t unmap_kiq_utility_queue : 1;
348 uint32_t preempt_legacy_gfx_queue : 1;
349 uint32_t unmap_legacy_queue : 1;
350 uint32_t remove_queue_after_reset : 1;
351 uint32_t reserved : 27;
352 };
353 struct MES_API_STATUS api_status;
354
355 uint32_t pipe_id;
356 uint32_t queue_id;
357
358 uint64_t tf_addr;
359 uint32_t tf_data;
360
361 enum MES_QUEUE_TYPE queue_type;
362 uint64_t timestamp;
363 uint32_t gang_context_array_index;
364 };
365
366 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
367};
368
369union MESAPI__SET_SCHEDULING_CONFIG {
370 struct {
371 union MES_API_HEADER header;
372 /* Grace period when preempting another priority band for this
373 * priority band. The value for idle priority band is ignored,
374 * as it never preempts other bands.
375 */
376 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
377 /* Default quantum for scheduling across processes within
378 * a priority band.
379 */
380 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
381 /* Default grace period for processes that preempt each other
382 * within a priority band.
383 */
384 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
385 /* For normal level this field specifies the target GPU
386 * percentage in situations when it's starved by the high level.
387 * Valid values are between 0 and 50, with the default being 10.
388 */
389 uint32_t normal_yield_percent;
390 struct MES_API_STATUS api_status;
391 };
392
393 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
394};
395
396union MESAPI__PERFORM_YIELD {
397 struct {
398 union MES_API_HEADER header;
399 uint32_t dummy;
400 struct MES_API_STATUS api_status;
401 };
402
403 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
404};
405
406union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
407 struct {
408 union MES_API_HEADER header;
409 uint32_t inprocess_gang_priority;
410 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
411 uint64_t gang_quantum;
412 uint64_t gang_context_addr;
413 struct MES_API_STATUS api_status;
414 };
415
416 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
417};
418
419union MESAPI__SUSPEND {
420 struct {
421 union MES_API_HEADER header;
422 /* false - suspend all gangs; true - specific gang */
423 struct {
424 uint32_t suspend_all_gangs : 1;
425 uint32_t reserved : 31;
426 };
427 /* gang_context_addr is valid only if suspend_all = false */
428 uint64_t gang_context_addr;
429
430 uint64_t suspend_fence_addr;
431 uint32_t suspend_fence_value;
432
433 struct MES_API_STATUS api_status;
434 uint32_t doorbell_offset;
435 };
436
437 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
438};
439
440union MESAPI__RESUME {
441 struct {
442 union MES_API_HEADER header;
443 /* false - resume all gangs; true - specified gang */
444 struct {
445 uint32_t resume_all_gangs : 1;
446 uint32_t reserved : 31;
447 };
448 /* valid only if resume_all_gangs = false */
449 uint64_t gang_context_addr;
450
451 struct MES_API_STATUS api_status;
452 uint32_t doorbell_offset;
453 };
454
455 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
456};
457
458union MESAPI__RESET {
459 struct {
460 union MES_API_HEADER header;
461
462 struct {
463 /* Only reset the queue given by doorbell_offset (not entire gang) */
464 uint32_t reset_queue_only : 1;
465 /* Hang detection first then reset any queues that are hung */
466 uint32_t hang_detect_then_reset : 1;
467 /* Only do hang detection (no reset) */
468 uint32_t hang_detect_only : 1;
469 /* Rest HP and LP kernel queues not managed by MES */
470 uint32_t reset_legacy_gfx : 1;
471 uint32_t reserved : 28;
472 };
473
474 uint64_t gang_context_addr;
475
476 /* valid only if reset_queue_only = true */
477 uint32_t doorbell_offset;
478
479 /* valid only if hang_detect_then_reset = true */
480 uint64_t doorbell_offset_addr;
481 enum MES_QUEUE_TYPE queue_type;
482
483 /* valid only if reset_legacy_gfx = true */
484 uint32_t pipe_id_lp;
485 uint32_t queue_id_lp;
486 uint32_t vmid_id_lp;
487 uint64_t mqd_mc_addr_lp;
488 uint32_t doorbell_offset_lp;
489 uint64_t wptr_addr_lp;
490
491 uint32_t pipe_id_hp;
492 uint32_t queue_id_hp;
493 uint32_t vmid_id_hp;
494 uint64_t mqd_mc_addr_hp;
495 uint32_t doorbell_offset_hp;
496 uint64_t wptr_addr_hp;
497
498 struct MES_API_STATUS api_status;
499 };
500
501 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
502};
503
504union MESAPI__SET_LOGGING_BUFFER {
505 struct {
506 union MES_API_HEADER header;
507 /* There are separate log buffers for each queue type */
508 enum MES_QUEUE_TYPE log_type;
509 /* Log buffer GPU Address */
510 uint64_t logging_buffer_addr;
511 /* number of entries in the log buffer */
512 uint32_t number_of_entries;
513 /* Entry index at which CPU interrupt needs to be signalled */
514 uint32_t interrupt_entry;
515
516 struct MES_API_STATUS api_status;
517 };
518
519 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
520};
521
522enum MES_API_QUERY_MES_OPCODE {
523 MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE,
524 MES_API_QUERY_MES__GET_CAPS = MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE,
525 MES_API_QUERY_MES__CHECK_HEALTHY,
526 MES_API_QUERY_MES__MAX,
527};
528
529enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 };
530
531/**
532 * Obsolete
533 * to be removed once KMD stopped refering to it.
534 * use MES_API_QUERY_MES__CAPS instead
535*/
536struct MES_API_QUERY_MES__CTX_ARRAY_SIZE {
537 uint64_t proc_ctx_array_size_addr;
538 uint64_t gang_ctx_array_size_addr;
539};
540
541struct MES_API_QUERY_MES__HEALTHY_CHECK {
542 uint64_t healthy_addr;
543};
544
545struct MES_API_QUERY_MES__CAPS {
546 uint64_t proc_ctx_array_size_addr;
547 uint64_t gang_ctx_array_size_addr;
548 uint64_t features_enablement_addr;
549};
550
551union MESAPI__QUERY_MES_STATUS {
552 struct {
553 union MES_API_HEADER header;
554 enum MES_API_QUERY_MES_OPCODE subopcode;
555 struct MES_API_STATUS api_status;
556 uint64_t timestamp;
557 union {
558 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE ctx_array_size;
559 struct MES_API_QUERY_MES__CAPS caps;
560 struct MES_API_QUERY_MES__HEALTHY_CHECK healthy_check;
561 uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS];
562 };
563 };
564
565 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
566};
567
568union MESAPI__PROGRAM_GDS {
569 struct {
570 union MES_API_HEADER header;
571 uint64_t process_context_addr;
572 uint32_t gds_base;
573 uint32_t gds_size;
574 uint32_t gws_base;
575 uint32_t gws_size;
576 uint32_t oa_mask;
577 struct MES_API_STATUS api_status;
578 };
579
580 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
581};
582
583union MESAPI__SET_DEBUG_VMID {
584 struct {
585 union MES_API_HEADER header;
586 struct MES_API_STATUS api_status;
587 union {
588 struct {
589 uint32_t use_gds : 1;
590 uint32_t operation : 2;
591 uint32_t reserved : 29;
592 } flags;
593 uint32_t u32All;
594 };
595 uint32_t reserved;
596 uint32_t debug_vmid;
597 uint64_t process_context_addr;
598 uint64_t page_table_base_addr;
599 uint64_t process_va_start;
600 uint64_t process_va_end;
601 uint32_t gds_base;
602 uint32_t gds_size;
603 uint32_t gws_base;
604 uint32_t gws_size;
605 uint32_t oa_mask;
606
607 /* output addr of the acquired vmid value */
608 uint64_t output_addr;
609 };
610
611 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
612};
613
614enum MESAPI_MISC_OPCODE {
615 MESAPI_MISC__WRITE_REG,
616 MESAPI_MISC__INV_GART,
617 MESAPI_MISC__QUERY_STATUS,
618 MESAPI_MISC__READ_REG,
619 MESAPI_MISC__WAIT_REG_MEM,
620 MESAPI_MISC__SET_SHADER_DEBUGGER,
621 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
622 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
623 MESAPI_MISC__CHANGE_CONFIG,
624 MESAPI_MISC__LAUNCH_CLEANER_SHADER,
625
626 MESAPI_MISC__MAX,
627};
628
629enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
630
631struct WRITE_REG {
632 uint32_t reg_offset;
633 uint32_t reg_value;
634};
635
636struct READ_REG {
637 uint32_t reg_offset;
638 uint64_t buffer_addr;
639};
640
641enum WRM_OPERATION {
642 WRM_OPERATION__WAIT_REG_MEM,
643 WRM_OPERATION__WR_WAIT_WR_REG,
644 WRM_OPERATION__MAX,
645};
646
647struct WAIT_REG_MEM {
648 enum WRM_OPERATION op;
649 uint32_t reference;
650 uint32_t mask;
651 uint32_t reg_offset1;
652 uint32_t reg_offset2;
653};
654
655struct INV_GART {
656 uint64_t inv_range_va_start;
657 uint64_t inv_range_size;
658};
659
660struct QUERY_STATUS {
661 uint32_t context_id;
662};
663
664struct SET_SHADER_DEBUGGER {
665 uint64_t process_context_addr;
666 union {
667 struct {
668 uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */
669 uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */
670 uint32_t reserved : 29;
671 uint32_t process_ctx_flush : 1;
672 };
673 uint32_t u32all;
674 } flags;
675 uint32_t spi_gdbg_per_vmid_cntl;
676 uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */
677 uint32_t trap_en;
678};
679
680enum MESAPI_MISC__CHANGE_CONFIG_OPTION {
681 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
682 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
683 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2,
684
685 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
686};
687
688struct CHANGE_CONFIG {
689 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode;
690 union {
691 struct {
692 uint32_t limit_single_process : 1;
693 uint32_t enable_hws_logging_buffer : 1;
694 uint32_t reserved : 31;
695 } bits;
696 uint32_t all;
697 } option;
698
699 struct {
700 uint32_t tdr_level;
701 uint32_t tdr_delay;
702 } tdr_config;
703};
704
705union MESAPI__MISC {
706 struct {
707 union MES_API_HEADER header;
708 enum MESAPI_MISC_OPCODE opcode;
709 struct MES_API_STATUS api_status;
710
711 union {
712 struct WRITE_REG write_reg;
713 struct INV_GART inv_gart;
714 struct QUERY_STATUS query_status;
715 struct READ_REG read_reg;
716 struct WAIT_REG_MEM wait_reg_mem;
717 struct SET_SHADER_DEBUGGER set_shader_debugger;
718 enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
719 struct CHANGE_CONFIG change_config;
720
721 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
722 };
723 };
724
725 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
726};
727
728union MESAPI__UPDATE_ROOT_PAGE_TABLE {
729 struct {
730 union MES_API_HEADER header;
731 uint64_t page_table_base_addr;
732 uint64_t process_context_addr;
733 struct MES_API_STATUS api_status;
734 };
735
736 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
737};
738
739union MESAPI_AMD_LOG {
740 struct {
741 union MES_API_HEADER header;
742 uint64_t p_buffer_memory;
743 uint64_t p_buffer_size_used;
744 struct MES_API_STATUS api_status;
745 };
746
747 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
748};
749
750#pragma pack(pop)
751#endif