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1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __MES_API_DEF_H__
25#define __MES_API_DEF_H__
26
27#pragma pack(push, 8)
28
29#define MES_API_VERSION 0x14
30
31/* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */
32#define AMDGPU_MES_LOG_BUFFER_SIZE 0xC000
33
34/* Driver submits one API(cmd) as a single Frame and this command size is same for all API
35 * to ease the debugging and parsing of ring buffer.
36 */
37enum {API_FRAME_SIZE_IN_DWORDS = 64};
38
39/* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in,
40 * this creates another queue
41 */
42enum {API_NUMBER_OF_COMMAND_MAX = 32};
43
44enum MES_API_TYPE {
45 MES_API_TYPE_SCHEDULER = 1,
46 MES_API_TYPE_MAX
47};
48
49enum MES_SCH_API_OPCODE {
50 MES_SCH_API_SET_HW_RSRC = 0,
51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
52 MES_SCH_API_ADD_QUEUE = 2,
53 MES_SCH_API_REMOVE_QUEUE = 3,
54 MES_SCH_API_PERFORM_YIELD = 4,
55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5, /* For windows GANG = Context */
56 MES_SCH_API_SUSPEND = 6,
57 MES_SCH_API_RESUME = 7,
58 MES_SCH_API_RESET = 8,
59 MES_SCH_API_SET_LOG_BUFFER = 9,
60 MES_SCH_API_CHANGE_GANG_PRORITY = 10,
61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
62 MES_SCH_API_SET_DEBUG_VMID = 13,
63 MES_SCH_API_MISC = 14,
64 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
65 MES_SCH_API_AMD_LOG = 16,
66 MES_SCH_API_SET_SE_MODE = 17,
67 MES_SCH_API_SET_GANG_SUBMIT = 18,
68 MES_SCH_API_SET_HW_RSRC_1 = 19,
69 MES_SCH_API_INV_TLBS = 20,
70
71 MES_SCH_API_MAX = 0xFF
72};
73
74enum MES_RRMT_MODE {
75 MES_RRMT_MODE_LOCAL_XCD,
76 MES_RRMT_MODE_LOCAL_REMOTE_AID,
77 MES_RRMT_MODE_REMOTE_XCD,
78 MES_RRMT_MODE_REMOTE_MID
79};
80
81union MES_API_HEADER {
82 struct {
83 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
84 uint32_t opcode : 8;
85 uint32_t dwsize : 8; /* including header */
86 uint32_t reserved : 12;
87 };
88
89 uint32_t u32All;
90};
91
92enum MES_AMD_PRIORITY_LEVEL {
93 AMD_PRIORITY_LEVEL_LOW = 0,
94 AMD_PRIORITY_LEVEL_NORMAL = 1,
95 AMD_PRIORITY_LEVEL_MEDIUM = 2,
96 AMD_PRIORITY_LEVEL_HIGH = 3,
97 AMD_PRIORITY_LEVEL_REALTIME = 4,
98
99 AMD_PRIORITY_NUM_LEVELS
100};
101
102enum MES_QUEUE_TYPE {
103 MES_QUEUE_TYPE_GFX,
104 MES_QUEUE_TYPE_COMPUTE,
105 MES_QUEUE_TYPE_SDMA,
106
107 MES_QUEUE_TYPE_MAX,
108 MES_QUEUE_TYPE_SCHQ = MES_QUEUE_TYPE_MAX,
109};
110
111struct MES_API_STATUS {
112 uint64_t api_completion_fence_addr;
113 uint64_t api_completion_fence_value;
114};
115
116/*
117 * MES will set api_completion_fence_value in api_completion_fence_addr
118 * when it can successflly process the API. MES will also trigger
119 * following interrupt when it finish process the API no matter success
120 * or failed.
121 * Interrupt source id 181 (EOP) with context ID (DW 6 in the int
122 * cookie) set to 0xb1 and context type set to 8. Driver side need
123 * to enable TIME_STAMP_INT_ENABLE in CPC_INT_CNTL for MES pipe to
124 * catch this interrupt.
125 * Driver side also need to set enable_mes_fence_int = 1 in
126 * set_HW_resource package to enable this fence interrupt.
127 * when the API process failed.
128 * lowre 32 bits set to 0.
129 * higher 32 bits set as follows (bit shift within high 32)
130 * bit 0 - 7 API specific error code.
131 * bit 8 - 15 API OPCODE.
132 * bit 16 - 23 MISC OPCODE if any
133 * bit 24 - 30 ERROR category (API_ERROR_XXX)
134 * bit 31 Set to 1 to indicate error status
135 *
136 */
137enum { MES_SCH_ERROR_CODE_HEADER_SHIFT_12 = 8 };
138enum { MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 = 16 };
139enum { MES_ERROR_CATEGORY_SHIFT_12 = 24 };
140enum { MES_API_STATUS_ERROR_SHIFT_12 = 31 };
141
142enum MES_ERROR_CATEGORY_CODE_12 {
143 MES_ERROR_API = 1,
144 MES_ERROR_SCHEDULING = 2,
145 MES_ERROR_UNKNOWN = 3,
146};
147
148#define MES_ERR_CODE(api_err, opcode, misc_op, category) \
149 ((uint64) (api_err | opcode << MES_SCH_ERROR_CODE_HEADER_SHIFT_12 | \
150 misc_op << MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 | \
151 category << MES_ERROR_CATEGORY_SHIFT_12 | \
152 1 << MES_API_STATUS_ERROR_SHIFT_12) << 32)
153
154enum { MAX_COMPUTE_PIPES = 8 };
155enum { MAX_GFX_PIPES = 2 };
156enum { MAX_SDMA_PIPES = 2 };
157
158enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
159enum { MAX_GFX_HQD_PER_PIPE = 8 };
160enum { MAX_SDMA_HQD_PER_PIPE = 10 };
161enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 };
162
163
164enum { MAX_QUEUES_IN_A_GANG = 8 };
165
166enum VM_HUB_TYPE {
167 VM_HUB_TYPE_GC = 0,
168 VM_HUB_TYPE_MM = 1,
169
170 VM_HUB_TYPE_MAX,
171};
172
173enum { VMID_INVALID = 0xffff };
174
175enum { MAX_VMID_GCHUB = 16 };
176enum { MAX_VMID_MMHUB = 16 };
177
178enum SET_DEBUG_VMID_OPERATIONS {
179 DEBUG_VMID_OP_PROGRAM = 0,
180 DEBUG_VMID_OP_ALLOCATE = 1,
181 DEBUG_VMID_OP_RELEASE = 2,
182 DEBUG_VMID_OP_VM_SETUP = 3 // used to set up the debug vmid page table in the kernel queue case (mode 1)
183};
184
185enum MES_MS_LOG_CONTEXT_STATE {
186 MES_LOG_CONTEXT_STATE_IDLE = 0,
187 MES_LOG_CONTEXT_STATE_RUNNING = 1,
188 MES_LOG_CONTEXT_STATE_READY = 2,
189 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
190 MES_LOG_CONTEXT_STATE_INVALID = 0xF,
191};
192
193enum MES_MS_LOG_OPERATION {
194 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
195 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
196 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
197 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
198 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
199 MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
200};
201
202struct MES_LOG_CONTEXT_STATE_CHANGE {
203 uint64_t h_context;
204 enum MES_MS_LOG_CONTEXT_STATE new_context_state;
205};
206
207struct MES_LOG_QUEUE_NEW_WORK {
208 uint64_t h_queue;
209 uint64_t reserved;
210};
211
212struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
213 uint64_t h_queue;
214 uint64_t h_sync_object;
215};
216
217struct MES_LOG_QUEUE_NO_MORE_WORK {
218 uint64_t h_queue;
219 uint64_t reserved;
220};
221
222struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
223 uint64_t h_queue;
224 uint64_t h_sync_object;
225};
226
227struct MES_LOG_ENTRY_HEADER {
228 uint32_t first_free_entry_index;
229 uint32_t wraparound_count;
230 uint64_t number_of_entries;
231 uint64_t reserved[2];
232};
233
234struct MES_LOG_ENTRY_DATA {
235 uint64_t gpu_time_stamp;
236 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
237 uint32_t reserved_operation_type_bits;
238 union {
239 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
240 struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
241 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
242 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
243 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
244 uint64_t all[2];
245 };
246};
247
248struct MES_LOG_BUFFER {
249 struct MES_LOG_ENTRY_HEADER header;
250 struct MES_LOG_ENTRY_DATA entries[];
251};
252
253enum MES_SWIP_TO_HWIP_DEF {
254 MES_MAX_HWIP_SEGMENT = 8,
255};
256
257union MESAPI_SET_HW_RESOURCES {
258 struct {
259 union MES_API_HEADER header;
260 uint32_t vmid_mask_mmhub;
261 uint32_t vmid_mask_gfxhub;
262 uint32_t gds_size;
263 uint32_t paging_vmid;
264 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
265 uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
266 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
267 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
268 uint64_t g_sch_ctx_gpu_mc_ptr;
269 uint64_t query_status_fence_gpu_mc_ptr;
270 uint32_t gc_base[MES_MAX_HWIP_SEGMENT];
271 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];
272 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];
273 struct MES_API_STATUS api_status;
274 union {
275 struct {
276 uint32_t disable_reset : 1;
277 uint32_t use_different_vmid_compute : 1;
278 uint32_t disable_mes_log : 1;
279 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
280 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
281 uint32_t second_gfx_pipe_enabled : 1;
282 uint32_t enable_level_process_quantum_check : 1;
283 uint32_t legacy_sch_mode : 1;
284 uint32_t disable_add_queue_wptr_mc_addr : 1;
285 uint32_t enable_mes_event_int_logging : 1;
286 uint32_t enable_reg_active_poll : 1;
287 uint32_t use_disable_queue_in_legacy_uq_preemption : 1;
288 uint32_t send_write_data : 1;
289 uint32_t os_tdr_timeout_override : 1;
290 uint32_t use_rs64mem_for_proc_gang_ctx : 1;
291 uint32_t halt_on_misaligned_access : 1;
292 uint32_t use_add_queue_unmap_flag_addr : 1;
293 uint32_t enable_mes_sch_stb_log : 1;
294 uint32_t limit_single_process : 1;
295 uint32_t unmapped_doorbell_handling: 2;
296 uint32_t enable_mes_fence_int: 1;
297 uint32_t enable_lr_compute_wa : 2;
298 uint32_t enable_compute_pipe_reset : 1;
299 uint32_t reserved : 7;
300 };
301 uint32_t uint32_all;
302 };
303 uint32_t oversubscription_timer;
304 uint64_t doorbell_info;
305 uint64_t event_intr_history_gpu_mc_ptr;
306 uint64_t timestamp;
307 uint32_t os_tdr_timeout_in_sec;
308 };
309
310 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
311};
312
313union MESAPI_SET_HW_RESOURCES_1 {
314 struct {
315 union MES_API_HEADER header;
316 struct MES_API_STATUS api_status;
317 uint64_t timestamp;
318 union {
319 struct {
320 uint32_t enable_mes_debug_ctx : 1;
321 uint32_t mes_coop_mode : 1; /* 0: non-coop; 1: coop */
322 uint32_t reserved : 30;
323 };
324 uint32_t uint32_all;
325 };
326 uint64_t mes_debug_ctx_mc_addr;
327 uint32_t mes_debug_ctx_size;
328 /* unit is 100ms */
329 uint32_t mes_kiq_unmap_timeout;
330 /* shared buffer of master/slaves, valid if mes_coop_mode=1 */
331 uint64_t coop_sch_shared_mc_addr;
332 uint64_t cleaner_shader_fence_mc_addr;
333 };
334
335 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
336};
337
338union MESAPI__ADD_QUEUE {
339 struct {
340 union MES_API_HEADER header;
341 uint32_t process_id;
342 uint64_t page_table_base_addr;
343 uint64_t process_va_start;
344 uint64_t process_va_end;
345 uint64_t process_quantum;
346 uint64_t process_context_addr;
347 uint64_t gang_quantum;
348 uint64_t gang_context_addr;
349 uint32_t inprocess_gang_priority;
350 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
351 uint32_t doorbell_offset;
352 uint64_t mqd_addr;
353 /* From MES_API_VERSION 2, mc addr is expected for wptr_addr */
354 uint64_t wptr_addr;
355 uint64_t h_context;
356 uint64_t h_queue;
357 enum MES_QUEUE_TYPE queue_type;
358 uint32_t gds_base;
359 union {
360 /* backwards compatibility with Linux, remove union once they use kfd_queue_size */
361 uint32_t gds_size;
362 uint32_t kfd_queue_size;
363 };
364 uint32_t gws_base;
365 uint32_t gws_size;
366 uint32_t oa_mask;
367 uint64_t trap_handler_addr;
368 uint32_t vm_context_cntl;
369
370 struct {
371 uint32_t paging : 1;
372 uint32_t debug_vmid : 4;
373 uint32_t program_gds : 1;
374 uint32_t is_gang_suspended : 1;
375 uint32_t is_tmz_queue : 1;
376 uint32_t map_kiq_utility_queue : 1;
377 uint32_t is_kfd_process : 1;
378 uint32_t trap_en : 1;
379 uint32_t is_aql_queue : 1;
380 uint32_t skip_process_ctx_clear : 1;
381 uint32_t map_legacy_kq : 1;
382 uint32_t exclusively_scheduled : 1;
383 uint32_t is_long_running : 1;
384 uint32_t is_dwm_queue : 1;
385 uint32_t reserved : 15;
386 };
387 struct MES_API_STATUS api_status;
388 uint64_t tma_addr;
389 uint32_t sch_id;
390 uint64_t timestamp;
391 uint32_t process_context_array_index;
392 uint32_t gang_context_array_index;
393 uint32_t pipe_id; //used for mapping legacy kernel queue
394 uint32_t queue_id;
395 uint32_t alignment_mode_setting;
396 uint32_t full_sh_mem_config_data;
397 };
398
399 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
400};
401
402union MESAPI__REMOVE_QUEUE {
403 struct {
404 union MES_API_HEADER header;
405 uint32_t doorbell_offset;
406 uint64_t gang_context_addr;
407
408 struct {
409 uint32_t reserved01 : 1;
410 uint32_t unmap_kiq_utility_queue : 1;
411 uint32_t preempt_legacy_gfx_queue : 1;
412 uint32_t unmap_legacy_queue : 1;
413 uint32_t remove_queue_after_reset : 1;
414 uint32_t reserved : 27;
415 };
416 struct MES_API_STATUS api_status;
417
418 uint32_t pipe_id;
419 uint32_t queue_id;
420
421 uint64_t tf_addr;
422 uint32_t tf_data;
423
424 enum MES_QUEUE_TYPE queue_type;
425 uint64_t timestamp;
426 uint32_t gang_context_array_index;
427 };
428
429 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
430};
431
432union MESAPI__SET_SCHEDULING_CONFIG {
433 struct {
434 union MES_API_HEADER header;
435 /* Grace period when preempting another priority band for this priority band.
436 * The value for idle priority band is ignored, as it never preempts other bands.
437 */
438 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
439
440 /* Default quantum for scheduling across processes within a priority band. */
441 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
442
443 /* Default grace period for processes that preempt each other within a priority band.*/
444 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
445
446 /* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level.
447 * Valid values are between 0 and 50, with the default being 10.
448 */
449 uint32_t normal_yield_percent;
450
451 struct MES_API_STATUS api_status;
452 uint64_t timestamp;
453 };
454
455 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
456};
457
458union MESAPI__PERFORM_YIELD {
459 struct {
460 union MES_API_HEADER header;
461 uint32_t dummy;
462 struct MES_API_STATUS api_status;
463 uint64_t timestamp;
464 };
465
466 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
467};
468
469union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
470 struct {
471 union MES_API_HEADER header;
472 uint32_t inprocess_gang_priority;
473 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
474 uint64_t gang_quantum;
475 uint64_t gang_context_addr;
476 struct MES_API_STATUS api_status;
477 uint32_t doorbell_offset;
478 uint64_t timestamp;
479 uint32_t gang_context_array_index;
480 struct {
481 uint32_t queue_quantum_scale : 2;
482 uint32_t queue_quantum_duration : 8;
483 uint32_t apply_quantum_all_processes : 1;
484 uint32_t reserved : 21;
485 };
486 };
487
488 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
489};
490
491union MESAPI__SUSPEND {
492 struct {
493 union MES_API_HEADER header;
494 /* false - suspend all gangs; true - specific gang */
495 struct {
496 uint32_t suspend_all_gangs : 1; // suspend all compute gangs (can be set together with suspend_all_sdma_gangs)
497 uint32_t query_status : 1;
498 uint32_t suspend_all_sdma_gangs : 1; // suspend all sdma gangs (can be set together with suspend_all_gangs)
499 uint32_t reserved : 29;
500 };
501 /* gang_context_addr is valid only if suspend_all = false */
502
503 uint64_t gang_context_addr;
504
505 uint64_t suspend_fence_addr;
506 uint32_t suspend_fence_value;
507
508 struct MES_API_STATUS api_status;
509
510 union {
511 uint32_t return_value; // to be removed
512 uint32_t sch_id; //keep the old return_value temporarily for compatibility
513 };
514 uint32_t doorbell_offset;
515 uint64_t timestamp;
516 enum MES_QUEUE_TYPE legacy_uq_type;
517 enum MES_AMD_PRIORITY_LEVEL legacy_uq_priority_level;
518 uint32_t gang_context_array_index;
519 };
520
521 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
522};
523
524union MESAPI__RESUME {
525 struct {
526 union MES_API_HEADER header;
527 /* false - resume all gangs; true - specified gang */
528 struct {
529 uint32_t resume_all_gangs : 1;
530 uint32_t reserved : 31;
531 };
532 /* valid only if resume_all_gangs = false */
533 uint64_t gang_context_addr;
534
535 struct MES_API_STATUS api_status;
536 uint32_t doorbell_offset;
537 uint64_t timestamp;
538 uint32_t gang_context_array_index;
539 };
540
541 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
542};
543
544union MESAPI__RESET {
545 struct {
546 union MES_API_HEADER header;
547
548 struct {
549 /* Only reset the queue given by doorbell_offset (not entire gang) */
550 uint32_t reset_queue_only : 1;
551 /* Hang detection first then reset any queues that are hung */
552 uint32_t hang_detect_then_reset : 1;
553 /* Only do hang detection (no reset) */
554 uint32_t hang_detect_only : 1;
555 /* Reset HP and LP kernel queues not managed by MES */
556 uint32_t reset_legacy_gfx : 1;
557 /* Fallback to use conneceted queue index when CP_CNTX_STAT method fails (gfx pipe 0) */
558 uint32_t use_connected_queue_index : 1;
559 /* For gfx pipe 1 */
560 uint32_t use_connected_queue_index_p1 : 1;
561 uint32_t reserved : 26;
562 };
563
564 uint64_t gang_context_addr;
565
566 /* valid only if reset_queue_only = true */
567 uint32_t doorbell_offset;
568
569 /*
570 * valid only if hang_detect_then_reset or hang_detect_only = true
571 * doorbell_offset_addr will store the structure as follows
572 * struct
573 * {
574 * uint32_t db_offset[list_size];
575 * uint32_t hqd_id[list_size];
576 * }
577 * The hqd_id has following defines :
578 * struct
579 * {
580 * uint32 queue_type : 3; Type of the queue
581 * uint32 pipe_index : 4; pipe Index
582 * uint32 hqd_index : 8; This is queue_index within the pipe
583 * uint32 reserved : 17;
584 * };
585 * The list_size is the total queue numbers that been managed by mes.
586 * It can be calculated from all hqd_masks(including gfX, compute and sdma)
587 * on set_hw_resource API
588 */
589 uint64_t doorbell_offset_addr;
590 enum MES_QUEUE_TYPE queue_type;
591
592 /* valid only if reset_legacy_gfx = true */
593 uint32_t pipe_id_lp;
594 uint32_t queue_id_lp;
595 uint32_t vmid_id_lp;
596 uint64_t mqd_mc_addr_lp;
597 uint32_t doorbell_offset_lp;
598 uint64_t wptr_addr_lp;
599
600 uint32_t pipe_id_hp;
601 uint32_t queue_id_hp;
602 uint32_t vmid_id_hp;
603 uint64_t mqd_mc_addr_hp;
604 uint32_t doorbell_offset_hp;
605 uint64_t wptr_addr_hp;
606
607 struct MES_API_STATUS api_status;
608 uint32_t active_vmids;
609 uint64_t timestamp;
610
611 uint32_t gang_context_array_index;
612
613 uint32_t connected_queue_index;
614 uint32_t connected_queue_index_p1;
615 };
616
617 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
618};
619
620union MESAPI__SET_LOGGING_BUFFER {
621 struct {
622 union MES_API_HEADER header;
623 /* There are separate log buffers for each queue type */
624 enum MES_QUEUE_TYPE log_type;
625 /* Log buffer GPU Address */
626 uint64_t logging_buffer_addr;
627 /* number of entries in the log buffer */
628 uint32_t number_of_entries;
629 /* Entry index at which CPU interrupt needs to be signalled */
630 uint32_t interrupt_entry;
631
632 struct MES_API_STATUS api_status;
633 uint64_t timestamp;
634 uint32_t vmid;
635 };
636
637 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
638};
639
640enum MES_API_QUERY_MES_OPCODE {
641 MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE,
642 MES_API_QUERY_MES__CHECK_HEALTHY,
643 MES_API_QUERY_MES__MAX,
644};
645
646enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 };
647
648struct MES_API_QUERY_MES__CTX_ARRAY_SIZE {
649 uint64_t proc_ctx_array_size_addr;
650 uint64_t gang_ctx_array_size_addr;
651};
652
653struct MES_API_QUERY_MES__HEALTHY_CHECK {
654 uint64_t healthy_addr;
655};
656
657union MESAPI__QUERY_MES_STATUS {
658 struct {
659 union MES_API_HEADER header;
660 enum MES_API_QUERY_MES_OPCODE subopcode;
661 struct MES_API_STATUS api_status;
662 uint64_t timestamp;
663 union {
664 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE ctx_array_size;
665 struct MES_API_QUERY_MES__HEALTHY_CHECK healthy_check;
666 uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS];
667 };
668 };
669
670 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
671};
672
673union MESAPI__SET_DEBUG_VMID {
674 struct {
675 union MES_API_HEADER header;
676 struct MES_API_STATUS api_status;
677 union {
678 struct {
679 uint32_t use_gds : 1;
680 uint32_t operation : 2;
681 uint32_t reserved : 29;
682 } flags;
683 uint32_t u32All;
684 };
685 uint32_t reserved;
686 uint32_t debug_vmid;
687 uint64_t process_context_addr;
688 uint64_t page_table_base_addr;
689 uint64_t process_va_start;
690 uint64_t process_va_end;
691 uint32_t gds_base;
692 uint32_t gds_size;
693 uint32_t gws_base;
694 uint32_t gws_size;
695 uint32_t oa_mask;
696
697 uint64_t output_addr; // output addr of the acquired vmid value
698
699 uint64_t timestamp;
700
701 uint32_t process_vm_cntl;
702 enum MES_QUEUE_TYPE queue_type;
703
704 uint32_t process_context_array_index;
705
706 uint32_t alignment_mode_setting;
707 uint32_t full_sh_mem_config_data;
708 };
709
710 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
711};
712
713enum MESAPI_MISC_OPCODE {
714 MESAPI_MISC__WRITE_REG,
715 MESAPI_MISC__INV_GART,
716 MESAPI_MISC__QUERY_STATUS,
717 MESAPI_MISC__READ_REG,
718 MESAPI_MISC__WAIT_REG_MEM,
719 MESAPI_MISC__SET_SHADER_DEBUGGER,
720 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
721 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
722 MESAPI_MISC__QUERY_HUNG_ENGINE_ID,
723 MESAPI_MISC__CHANGE_CONFIG,
724 MESAPI_MISC__LAUNCH_CLEANER_SHADER,
725 MESAPI_MISC__SETUP_MES_DBGEXT,
726
727 MESAPI_MISC__MAX,
728};
729
730enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20};
731
732/*
733 * RRMT(Register Remapping Table), allow the firmware to modify the upper
734 * address to correctly steer the register transaction to expected DIE
735 */
736struct RRMT_OPTION {
737 union {
738 struct {
739 uint32_t mode : 4;
740 uint32_t mid_die_id : 4;
741 uint32_t xcd_die_id : 4;
742 };
743 uint32_t all;
744 };
745};
746
747
748struct WRITE_REG {
749 uint32_t reg_offset;
750 uint32_t reg_value;
751 struct RRMT_OPTION rrmt_opt;
752};
753
754struct READ_REG {
755 uint32_t reg_offset;
756 uint64_t buffer_addr;
757 union {
758 struct {
759 uint32_t read64Bits : 1;
760 uint32_t reserved : 31;
761 } bits;
762 uint32_t all;
763 } option;
764 struct RRMT_OPTION rrmt_opt;
765};
766
767struct INV_GART {
768 uint64_t inv_range_va_start;
769 uint64_t inv_range_size;
770};
771
772struct QUERY_STATUS {
773 uint32_t context_id;
774};
775
776enum WRM_OPERATION {
777 WRM_OPERATION__WAIT_REG_MEM,
778 WRM_OPERATION__WR_WAIT_WR_REG,
779
780 WRM_OPERATION__MAX,
781};
782
783struct WAIT_REG_MEM {
784 enum WRM_OPERATION op;
785 /* only function = equal_to_the_reference_value and mem_space = register_space supported for now */
786 uint32_t reference;
787 uint32_t mask;
788 uint32_t reg_offset1;
789 uint32_t reg_offset2;
790 struct RRMT_OPTION rrmt_opt1; /* for reg1 */
791 struct RRMT_OPTION rrmt_opt2; /* for reg2 */
792};
793
794struct SET_SHADER_DEBUGGER {
795 uint64_t process_context_addr;
796 union {
797 struct {
798 uint32_t single_memop : 1; // SQ_DEBUG.single_memop
799 uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op
800 uint32_t lds_oor_reporting : 1; /* SQ_DEBUG.ADDR_OUT_OF_RANGE_REPORTING */
801 uint32_t reserved : 29;
802 };
803 uint32_t u32all;
804 } flags;
805 uint32_t spi_gdbg_per_vmid_cntl;
806 uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL
807 uint32_t trap_en;
808};
809
810struct SET_GANG_SUBMIT {
811 uint64_t gang_context_addr;
812 uint64_t slave_gang_context_addr;
813 uint32_t gang_context_array_index;
814 uint32_t slave_gang_context_array_index;
815};
816
817enum MESAPI_MISC__CHANGE_CONFIG_OPTION {
818 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
819 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
820 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2,
821
822 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
823};
824
825struct CHANGE_CONFIG {
826 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode;
827 union {
828 struct {
829 uint32_t limit_single_process : 1;
830 uint32_t enable_hws_logging_buffer : 1;
831 uint32_t reserved : 30;
832 } bits;
833 uint32_t all;
834 } option;
835
836 struct {
837 uint32_t tdr_level;
838 uint32_t tdr_delay;
839 } tdr_config;
840};
841
842union MESAPI__MISC {
843 struct {
844 union MES_API_HEADER header;
845 enum MESAPI_MISC_OPCODE opcode;
846 struct MES_API_STATUS api_status;
847 union {
848 struct WRITE_REG write_reg;
849 struct INV_GART inv_gart;
850 struct QUERY_STATUS query_status;
851 struct READ_REG read_reg;
852 struct WAIT_REG_MEM wait_reg_mem;
853 struct SET_SHADER_DEBUGGER set_shader_debugger;
854 enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
855 struct CHANGE_CONFIG change_config;
856 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
857 };
858 uint64_t timestamp;
859 uint32_t doorbell_offset;
860 uint32_t os_fence;
861 };
862
863 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
864};
865
866union MESAPI__UPDATE_ROOT_PAGE_TABLE {
867 struct {
868 union MES_API_HEADER header;
869 uint64_t page_table_base_addr;
870 uint64_t process_context_addr;
871 struct MES_API_STATUS api_status;
872 uint64_t timestamp;
873 uint32_t process_context_array_index;
874 };
875
876 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
877};
878
879union MESAPI_AMD_LOG {
880 struct {
881 union MES_API_HEADER header;
882 uint64_t p_buffer_memory;
883 uint64_t p_buffer_size_used;
884 struct MES_API_STATUS api_status;
885 uint64_t timestamp;
886 };
887
888 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
889};
890
891enum MES_SE_MODE {
892 MES_SE_MODE_INVALID = 0,
893 MES_SE_MODE_SINGLE_SE = 1,
894 MES_SE_MODE_DUAL_SE = 2,
895 MES_SE_MODE_LOWER_POWER = 3,
896};
897
898union MESAPI__SET_SE_MODE {
899 struct {
900 union MES_API_HEADER header;
901 /* the new SE mode to apply*/
902 enum MES_SE_MODE new_se_mode;
903 /* the fence to make sure the ItCpgCtxtSync packet is completed */
904 uint64_t cpg_ctxt_sync_fence_addr;
905 uint32_t cpg_ctxt_sync_fence_value;
906 /* log_seq_time - Scheduler logs the switch seq start/end ts in the IH cookies */
907 union {
908 struct {
909 uint32_t log_seq_time : 1;
910 uint32_t reserved : 31;
911 };
912 uint32_t uint32_all;
913 };
914 struct MES_API_STATUS api_status;
915 };
916
917 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
918};
919
920union MESAPI__SET_GANG_SUBMIT {
921 struct {
922 union MES_API_HEADER header;
923 struct MES_API_STATUS api_status;
924 struct SET_GANG_SUBMIT set_gang_submit;
925 };
926
927 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
928};
929
930/*
931 * @inv_sel 0-select pasid as input to do the invalidation , 1-select vmid
932 * @flush_type 0-old style, 1-light weight, 2-heavyweight, 3-heavyweight2
933 * @inv_sel_id specific pasid when inv_sel is 0 and specific vmid if inv_sel is 1
934 * @hub_id 0-gc_hub, 1-mm_hub
935 */
936struct INV_TLBS {
937 uint8_t inv_sel;
938 uint8_t flush_type;
939 uint16_t inv_sel_id;
940 uint32_t hub_id;
941 /* If following two inv_range setting are all 0 , whole VM will be invalidated,
942 * otherwise only required range be invalidated
943 */
944 uint64_t inv_range_va_start;
945 uint64_t inv_range_size;
946 uint64_t reserved;
947};
948
949union MESAPI__INV_TLBS {
950 struct {
951 union MES_API_HEADER header;
952 struct MES_API_STATUS api_status;
953 struct INV_TLBS invalidate_tlbs;
954 };
955
956 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
957};
958
959#pragma pack(pop)
960
961#endif