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1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include "amdgpu.h"
26#include "amdgpu_atombios.h"
27#include "amdgpu_i2c.h"
28#include "amdgpu_dpm.h"
29#include "atom.h"
30#include "amd_pcie.h"
31#include "amdgpu_display.h"
32#include "hwmgr.h"
33#include <linux/power_supply.h>
34#include "amdgpu_smu.h"
35
36#define amdgpu_dpm_notify_ac_dc(adev) \
37 ((adev)->powerplay.pp_funcs->notify_ac_dc((adev)->powerplay.pp_handle))
38
39#define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev))
40
41int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
42{
43 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
44 int ret = 0;
45
46 if (!pp_funcs->get_sclk)
47 return 0;
48
49 mutex_lock(&adev->pm.mutex);
50 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle,
51 low);
52 mutex_unlock(&adev->pm.mutex);
53
54 return ret;
55}
56
57int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
58{
59 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
60 int ret = 0;
61
62 if (!pp_funcs->get_mclk)
63 return 0;
64
65 mutex_lock(&adev->pm.mutex);
66 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle,
67 low);
68 mutex_unlock(&adev->pm.mutex);
69
70 return ret;
71}
72
73int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
74 uint32_t block_type,
75 bool gate,
76 int inst)
77{
78 int ret = 0;
79 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
80 enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;
81 bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN;
82
83 mutex_lock(&adev->pm.mutex);
84
85 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state &&
86 (!is_vcn || adev->vcn.num_vcn_inst == 1)) {
87 dev_dbg(adev->dev, "IP block%d already in the target %s state!",
88 block_type, gate ? "gate" : "ungate");
89 goto out_unlock;
90 }
91
92 switch (block_type) {
93 case AMD_IP_BLOCK_TYPE_UVD:
94 case AMD_IP_BLOCK_TYPE_VCE:
95 case AMD_IP_BLOCK_TYPE_GFX:
96 case AMD_IP_BLOCK_TYPE_SDMA:
97 case AMD_IP_BLOCK_TYPE_JPEG:
98 case AMD_IP_BLOCK_TYPE_GMC:
99 case AMD_IP_BLOCK_TYPE_ACP:
100 case AMD_IP_BLOCK_TYPE_VPE:
101 case AMD_IP_BLOCK_TYPE_ISP:
102 if (pp_funcs && pp_funcs->set_powergating_by_smu)
103 ret = (pp_funcs->set_powergating_by_smu(
104 (adev)->powerplay.pp_handle, block_type, gate, 0));
105 break;
106 case AMD_IP_BLOCK_TYPE_VCN:
107 if (pp_funcs && pp_funcs->set_powergating_by_smu)
108 ret = (pp_funcs->set_powergating_by_smu(
109 (adev)->powerplay.pp_handle, block_type, gate, inst));
110 break;
111 default:
112 break;
113 }
114
115 if (!ret)
116 atomic_set(&adev->pm.pwr_state[block_type], pwr_state);
117
118out_unlock:
119 mutex_unlock(&adev->pm.mutex);
120
121 return ret;
122}
123
124int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev)
125{
126 struct smu_context *smu = adev->powerplay.pp_handle;
127 int ret = -EOPNOTSUPP;
128
129 mutex_lock(&adev->pm.mutex);
130 ret = smu_set_gfx_power_up_by_imu(smu);
131 mutex_unlock(&adev->pm.mutex);
132
133 msleep(10);
134
135 return ret;
136}
137
138int amdgpu_dpm_baco_enter(struct amdgpu_device *adev)
139{
140 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
141 void *pp_handle = adev->powerplay.pp_handle;
142 int ret = 0;
143
144 if (!pp_funcs || !pp_funcs->set_asic_baco_state)
145 return -ENOENT;
146
147 mutex_lock(&adev->pm.mutex);
148
149 /* enter BACO state */
150 ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
151
152 mutex_unlock(&adev->pm.mutex);
153
154 return ret;
155}
156
157int amdgpu_dpm_baco_exit(struct amdgpu_device *adev)
158{
159 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
160 void *pp_handle = adev->powerplay.pp_handle;
161 int ret = 0;
162
163 if (!pp_funcs || !pp_funcs->set_asic_baco_state)
164 return -ENOENT;
165
166 mutex_lock(&adev->pm.mutex);
167
168 /* exit BACO state */
169 ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
170
171 mutex_unlock(&adev->pm.mutex);
172
173 return ret;
174}
175
176int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
177 enum pp_mp1_state mp1_state)
178{
179 int ret = 0;
180 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
181
182 if (mp1_state == PP_MP1_STATE_FLR) {
183 /* VF lost access to SMU */
184 if (amdgpu_sriov_vf(adev))
185 adev->pm.dpm_enabled = false;
186 } else if (pp_funcs && pp_funcs->set_mp1_state) {
187 mutex_lock(&adev->pm.mutex);
188
189 ret = pp_funcs->set_mp1_state(
190 adev->powerplay.pp_handle,
191 mp1_state);
192
193 mutex_unlock(&adev->pm.mutex);
194 }
195
196 return ret;
197}
198
199int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev)
200{
201 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
202 void *pp_handle = adev->powerplay.pp_handle;
203 int ret;
204
205 if (!pp_funcs || !pp_funcs->get_asic_baco_capability)
206 return 0;
207 /* Don't use baco for reset in S3.
208 * This is a workaround for some platforms
209 * where entering BACO during suspend
210 * seems to cause reboots or hangs.
211 * This might be related to the fact that BACO controls
212 * power to the whole GPU including devices like audio and USB.
213 * Powering down/up everything may adversely affect these other
214 * devices. Needs more investigation.
215 */
216 if (adev->in_s3)
217 return 0;
218
219 mutex_lock(&adev->pm.mutex);
220
221 ret = pp_funcs->get_asic_baco_capability(pp_handle);
222
223 mutex_unlock(&adev->pm.mutex);
224
225 return ret;
226}
227
228int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev)
229{
230 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
231 void *pp_handle = adev->powerplay.pp_handle;
232 int ret = 0;
233
234 if (!pp_funcs || !pp_funcs->asic_reset_mode_2)
235 return -ENOENT;
236
237 mutex_lock(&adev->pm.mutex);
238
239 ret = pp_funcs->asic_reset_mode_2(pp_handle);
240
241 mutex_unlock(&adev->pm.mutex);
242
243 return ret;
244}
245
246int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev)
247{
248 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
249 void *pp_handle = adev->powerplay.pp_handle;
250 int ret = 0;
251
252 if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features)
253 return -ENOENT;
254
255 mutex_lock(&adev->pm.mutex);
256
257 ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle);
258
259 mutex_unlock(&adev->pm.mutex);
260
261 return ret;
262}
263
264int amdgpu_dpm_baco_reset(struct amdgpu_device *adev)
265{
266 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
267 void *pp_handle = adev->powerplay.pp_handle;
268 int ret = 0;
269
270 if (!pp_funcs || !pp_funcs->set_asic_baco_state)
271 return -ENOENT;
272
273 mutex_lock(&adev->pm.mutex);
274
275 /* enter BACO state */
276 ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
277 if (ret)
278 goto out;
279
280 /* exit BACO state */
281 ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
282
283out:
284 mutex_unlock(&adev->pm.mutex);
285 return ret;
286}
287
288bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev)
289{
290 struct smu_context *smu = adev->powerplay.pp_handle;
291 bool support_mode1_reset = false;
292
293 if (is_support_sw_smu(adev)) {
294 mutex_lock(&adev->pm.mutex);
295 support_mode1_reset = smu_mode1_reset_is_support(smu);
296 mutex_unlock(&adev->pm.mutex);
297 }
298
299 return support_mode1_reset;
300}
301
302int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev)
303{
304 struct smu_context *smu = adev->powerplay.pp_handle;
305 int ret = -EOPNOTSUPP;
306
307 if (is_support_sw_smu(adev)) {
308 mutex_lock(&adev->pm.mutex);
309 ret = smu_mode1_reset(smu);
310 mutex_unlock(&adev->pm.mutex);
311 }
312
313 return ret;
314}
315
316bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev)
317{
318 struct smu_context *smu = adev->powerplay.pp_handle;
319 bool support_link_reset = false;
320
321 if (is_support_sw_smu(adev)) {
322 mutex_lock(&adev->pm.mutex);
323 support_link_reset = smu_link_reset_is_support(smu);
324 mutex_unlock(&adev->pm.mutex);
325 }
326
327 return support_link_reset;
328}
329
330int amdgpu_dpm_link_reset(struct amdgpu_device *adev)
331{
332 struct smu_context *smu = adev->powerplay.pp_handle;
333 int ret = -EOPNOTSUPP;
334
335 if (is_support_sw_smu(adev)) {
336 mutex_lock(&adev->pm.mutex);
337 ret = smu_link_reset(smu);
338 mutex_unlock(&adev->pm.mutex);
339 }
340
341 return ret;
342}
343
344int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
345 enum PP_SMC_POWER_PROFILE type,
346 bool en)
347{
348 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
349 int ret = 0;
350
351 if (amdgpu_sriov_vf(adev) ||
352 amdgpu_in_reset(adev))
353 return 0;
354
355 if (pp_funcs && pp_funcs->switch_power_profile) {
356 mutex_lock(&adev->pm.mutex);
357 ret = pp_funcs->switch_power_profile(
358 adev->powerplay.pp_handle, type, en);
359 mutex_unlock(&adev->pm.mutex);
360 }
361
362 return ret;
363}
364
365int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev,
366 bool pause)
367{
368 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
369 int ret = 0;
370
371 if (amdgpu_sriov_vf(adev) ||
372 amdgpu_in_reset(adev))
373 return 0;
374
375 if (pp_funcs && pp_funcs->pause_power_profile) {
376 mutex_lock(&adev->pm.mutex);
377 ret = pp_funcs->pause_power_profile(
378 adev->powerplay.pp_handle, pause);
379 mutex_unlock(&adev->pm.mutex);
380 }
381
382 return ret;
383}
384
385int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
386 uint32_t pstate)
387{
388 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
389 int ret = 0;
390
391 if (pp_funcs && pp_funcs->set_xgmi_pstate) {
392 mutex_lock(&adev->pm.mutex);
393 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
394 pstate);
395 mutex_unlock(&adev->pm.mutex);
396 }
397
398 return ret;
399}
400
401int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,
402 uint32_t cstate)
403{
404 int ret = 0;
405 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
406 void *pp_handle = adev->powerplay.pp_handle;
407
408 if (pp_funcs && pp_funcs->set_df_cstate) {
409 mutex_lock(&adev->pm.mutex);
410 ret = pp_funcs->set_df_cstate(pp_handle, cstate);
411 mutex_unlock(&adev->pm.mutex);
412 }
413
414 return ret;
415}
416
417ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev,
418 enum pp_pm_policy p_type, char *buf)
419{
420 struct smu_context *smu = adev->powerplay.pp_handle;
421 int ret = -EOPNOTSUPP;
422
423 if (is_support_sw_smu(adev)) {
424 mutex_lock(&adev->pm.mutex);
425 ret = smu_get_pm_policy_info(smu, p_type, buf);
426 mutex_unlock(&adev->pm.mutex);
427 }
428
429 return ret;
430}
431
432int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type,
433 int policy_level)
434{
435 struct smu_context *smu = adev->powerplay.pp_handle;
436 int ret = -EOPNOTSUPP;
437
438 if (is_support_sw_smu(adev)) {
439 mutex_lock(&adev->pm.mutex);
440 ret = smu_set_pm_policy(smu, policy_type, policy_level);
441 mutex_unlock(&adev->pm.mutex);
442 }
443
444 return ret;
445}
446
447int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev)
448{
449 void *pp_handle = adev->powerplay.pp_handle;
450 const struct amd_pm_funcs *pp_funcs =
451 adev->powerplay.pp_funcs;
452 int ret = 0;
453
454 if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) {
455 mutex_lock(&adev->pm.mutex);
456 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle);
457 mutex_unlock(&adev->pm.mutex);
458 }
459
460 return ret;
461}
462
463int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,
464 uint32_t msg_id)
465{
466 void *pp_handle = adev->powerplay.pp_handle;
467 const struct amd_pm_funcs *pp_funcs =
468 adev->powerplay.pp_funcs;
469 int ret = 0;
470
471 if (pp_funcs && pp_funcs->set_clockgating_by_smu) {
472 mutex_lock(&adev->pm.mutex);
473 ret = pp_funcs->set_clockgating_by_smu(pp_handle,
474 msg_id);
475 mutex_unlock(&adev->pm.mutex);
476 }
477
478 return ret;
479}
480
481int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev,
482 bool acquire)
483{
484 void *pp_handle = adev->powerplay.pp_handle;
485 const struct amd_pm_funcs *pp_funcs =
486 adev->powerplay.pp_funcs;
487 int ret = -EOPNOTSUPP;
488
489 if (pp_funcs && pp_funcs->smu_i2c_bus_access) {
490 mutex_lock(&adev->pm.mutex);
491 ret = pp_funcs->smu_i2c_bus_access(pp_handle,
492 acquire);
493 mutex_unlock(&adev->pm.mutex);
494 }
495
496 return ret;
497}
498
499void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
500{
501 if (adev->pm.dpm_enabled) {
502 mutex_lock(&adev->pm.mutex);
503 if (power_supply_is_system_supplied() > 0)
504 adev->pm.ac_power = true;
505 else
506 adev->pm.ac_power = false;
507
508 if (adev->powerplay.pp_funcs &&
509 adev->powerplay.pp_funcs->notify_ac_dc)
510 amdgpu_dpm_notify_ac_dc(adev);
511
512 if (is_support_sw_smu(adev))
513 smu_set_ac_dc(adev->powerplay.pp_handle, true);
514
515 mutex_unlock(&adev->pm.mutex);
516 }
517}
518
519int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
520 void *data, uint32_t *size)
521{
522 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
523 int ret = -EINVAL;
524
525 if (!data || !size)
526 return -EINVAL;
527
528 if (pp_funcs && pp_funcs->read_sensor) {
529 mutex_lock(&adev->pm.mutex);
530 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle,
531 sensor,
532 data,
533 size);
534 mutex_unlock(&adev->pm.mutex);
535 }
536
537 return ret;
538}
539
540int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit)
541{
542 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
543 int ret = -EOPNOTSUPP;
544
545 if (pp_funcs && pp_funcs->get_apu_thermal_limit) {
546 mutex_lock(&adev->pm.mutex);
547 ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit);
548 mutex_unlock(&adev->pm.mutex);
549 }
550
551 return ret;
552}
553
554int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit)
555{
556 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
557 int ret = -EOPNOTSUPP;
558
559 if (pp_funcs && pp_funcs->set_apu_thermal_limit) {
560 mutex_lock(&adev->pm.mutex);
561 ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit);
562 mutex_unlock(&adev->pm.mutex);
563 }
564
565 return ret;
566}
567
568void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev)
569{
570 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
571 int i;
572
573 if (!adev->pm.dpm_enabled)
574 return;
575
576 if (!pp_funcs->pm_compute_clocks)
577 return;
578
579 if (adev->mode_info.num_crtc)
580 amdgpu_display_bandwidth_update(adev);
581
582 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
583 struct amdgpu_ring *ring = adev->rings[i];
584 if (ring && ring->sched.ready)
585 amdgpu_fence_wait_empty(ring);
586 }
587
588 mutex_lock(&adev->pm.mutex);
589 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle);
590 mutex_unlock(&adev->pm.mutex);
591}
592
593void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
594{
595 int ret = 0;
596
597 if (adev->family == AMDGPU_FAMILY_SI) {
598 mutex_lock(&adev->pm.mutex);
599 if (enable) {
600 adev->pm.dpm.uvd_active = true;
601 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
602 } else {
603 adev->pm.dpm.uvd_active = false;
604 }
605 mutex_unlock(&adev->pm.mutex);
606
607 amdgpu_dpm_compute_clocks(adev);
608 return;
609 }
610
611 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable, 0);
612 if (ret)
613 drm_err(adev_to_drm(adev), "DPM %s uvd failed, ret = %d.\n",
614 enable ? "enable" : "disable", ret);
615}
616
617void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst)
618{
619 int ret = 0;
620
621 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, inst);
622 if (ret)
623 drm_err(adev_to_drm(adev), "DPM %s vcn failed, ret = %d.\n",
624 enable ? "enable" : "disable", ret);
625}
626
627void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
628{
629 int ret = 0;
630
631 if (adev->family == AMDGPU_FAMILY_SI) {
632 mutex_lock(&adev->pm.mutex);
633 if (enable) {
634 adev->pm.dpm.vce_active = true;
635 /* XXX select vce level based on ring/task */
636 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
637 } else {
638 adev->pm.dpm.vce_active = false;
639 }
640 mutex_unlock(&adev->pm.mutex);
641
642 amdgpu_dpm_compute_clocks(adev);
643 return;
644 }
645
646 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable, 0);
647 if (ret)
648 drm_err(adev_to_drm(adev), "DPM %s vce failed, ret = %d.\n",
649 enable ? "enable" : "disable", ret);
650}
651
652void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
653{
654 int ret = 0;
655
656 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable, 0);
657 if (ret)
658 drm_err(adev_to_drm(adev), "Dpm %s jpeg failed, ret = %d.\n",
659 enable ? "enable" : "disable", ret);
660}
661
662void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable)
663{
664 int ret = 0;
665
666 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable, 0);
667 if (ret)
668 drm_err(adev_to_drm(adev), "DPM %s vpe failed, ret = %d.\n",
669 enable ? "enable" : "disable", ret);
670}
671
672int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
673{
674 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
675 int r = 0;
676
677 if (!pp_funcs || !pp_funcs->load_firmware ||
678 (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU)))
679 return 0;
680
681 mutex_lock(&adev->pm.mutex);
682 r = pp_funcs->load_firmware(adev->powerplay.pp_handle);
683 if (r) {
684 pr_err("smu firmware loading failed\n");
685 goto out;
686 }
687
688 if (smu_version)
689 *smu_version = adev->pm.fw_version;
690
691out:
692 mutex_unlock(&adev->pm.mutex);
693 return r;
694}
695
696int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable)
697{
698 int ret = 0;
699
700 if (is_support_sw_smu(adev)) {
701 mutex_lock(&adev->pm.mutex);
702 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle,
703 enable);
704 mutex_unlock(&adev->pm.mutex);
705 }
706
707 return ret;
708}
709
710int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size)
711{
712 struct smu_context *smu = adev->powerplay.pp_handle;
713 int ret = 0;
714
715 if (!is_support_sw_smu(adev))
716 return -EOPNOTSUPP;
717
718 mutex_lock(&adev->pm.mutex);
719 ret = smu_send_hbm_bad_pages_num(smu, size);
720 mutex_unlock(&adev->pm.mutex);
721
722 return ret;
723}
724
725int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size)
726{
727 struct smu_context *smu = adev->powerplay.pp_handle;
728 int ret = 0;
729
730 if (!is_support_sw_smu(adev))
731 return -EOPNOTSUPP;
732
733 mutex_lock(&adev->pm.mutex);
734 ret = smu_send_hbm_bad_channel_flag(smu, size);
735 mutex_unlock(&adev->pm.mutex);
736
737 return ret;
738}
739
740int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev)
741{
742 struct smu_context *smu = adev->powerplay.pp_handle;
743 int ret;
744
745 if (!is_support_sw_smu(adev))
746 return -EOPNOTSUPP;
747
748 mutex_lock(&adev->pm.mutex);
749 ret = smu_send_rma_reason(smu);
750 mutex_unlock(&adev->pm.mutex);
751
752 return ret;
753}
754
755/**
756 * amdgpu_dpm_reset_sdma_is_supported - Check if SDMA reset is supported
757 * @adev: amdgpu_device pointer
758 *
759 * This function checks if the SMU supports resetting the SDMA engine.
760 * It returns false if the hardware does not support software SMU or
761 * if the feature is not supported.
762 */
763bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev)
764{
765 struct smu_context *smu = adev->powerplay.pp_handle;
766 bool ret;
767
768 if (!is_support_sw_smu(adev))
769 return false;
770
771 mutex_lock(&adev->pm.mutex);
772 ret = smu_reset_sdma_is_supported(smu);
773 mutex_unlock(&adev->pm.mutex);
774
775 return ret;
776}
777
778int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask)
779{
780 struct smu_context *smu = adev->powerplay.pp_handle;
781 int ret;
782
783 if (!is_support_sw_smu(adev))
784 return -EOPNOTSUPP;
785
786 mutex_lock(&adev->pm.mutex);
787 ret = smu_reset_sdma(smu, inst_mask);
788 mutex_unlock(&adev->pm.mutex);
789
790 return ret;
791}
792
793int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask)
794{
795 struct smu_context *smu = adev->powerplay.pp_handle;
796 int ret;
797
798 if (!is_support_sw_smu(adev))
799 return -EOPNOTSUPP;
800
801 mutex_lock(&adev->pm.mutex);
802 ret = smu_reset_vcn(smu, inst_mask);
803 mutex_unlock(&adev->pm.mutex);
804
805 return ret;
806}
807
808bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev)
809{
810 struct smu_context *smu = adev->powerplay.pp_handle;
811 bool ret;
812
813 if (!is_support_sw_smu(adev))
814 return false;
815
816 mutex_lock(&adev->pm.mutex);
817 ret = smu_reset_vcn_is_supported(smu);
818 mutex_unlock(&adev->pm.mutex);
819
820 return ret;
821}
822
823int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
824 enum pp_clock_type type,
825 uint32_t *min,
826 uint32_t *max)
827{
828 int ret = 0;
829
830 if (type != PP_SCLK)
831 return -EINVAL;
832
833 if (!is_support_sw_smu(adev))
834 return -EOPNOTSUPP;
835
836 mutex_lock(&adev->pm.mutex);
837 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle,
838 SMU_SCLK,
839 min,
840 max);
841 mutex_unlock(&adev->pm.mutex);
842
843 return ret;
844}
845
846int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,
847 enum pp_clock_type type,
848 uint32_t min,
849 uint32_t max)
850{
851 struct smu_context *smu = adev->powerplay.pp_handle;
852
853 if (!is_support_sw_smu(adev))
854 return -EOPNOTSUPP;
855
856 guard(mutex)(&adev->pm.mutex);
857
858 return smu_set_soft_freq_range(smu,
859 type,
860 min,
861 max);
862}
863
864int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev)
865{
866 struct smu_context *smu = adev->powerplay.pp_handle;
867 int ret = 0;
868
869 if (!is_support_sw_smu(adev))
870 return 0;
871
872 mutex_lock(&adev->pm.mutex);
873 ret = smu_write_watermarks_table(smu);
874 mutex_unlock(&adev->pm.mutex);
875
876 return ret;
877}
878
879int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev,
880 enum smu_event_type event,
881 uint64_t event_arg)
882{
883 struct smu_context *smu = adev->powerplay.pp_handle;
884 int ret = 0;
885
886 if (!is_support_sw_smu(adev))
887 return -EOPNOTSUPP;
888
889 mutex_lock(&adev->pm.mutex);
890 ret = smu_wait_for_event(smu, event, event_arg);
891 mutex_unlock(&adev->pm.mutex);
892
893 return ret;
894}
895
896int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value)
897{
898 struct smu_context *smu = adev->powerplay.pp_handle;
899 int ret = 0;
900
901 if (!is_support_sw_smu(adev))
902 return -EOPNOTSUPP;
903
904 mutex_lock(&adev->pm.mutex);
905 ret = smu_set_residency_gfxoff(smu, value);
906 mutex_unlock(&adev->pm.mutex);
907
908 return ret;
909}
910
911int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value)
912{
913 struct smu_context *smu = adev->powerplay.pp_handle;
914 int ret = 0;
915
916 if (!is_support_sw_smu(adev))
917 return -EOPNOTSUPP;
918
919 mutex_lock(&adev->pm.mutex);
920 ret = smu_get_residency_gfxoff(smu, value);
921 mutex_unlock(&adev->pm.mutex);
922
923 return ret;
924}
925
926int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value)
927{
928 struct smu_context *smu = adev->powerplay.pp_handle;
929 int ret = 0;
930
931 if (!is_support_sw_smu(adev))
932 return -EOPNOTSUPP;
933
934 mutex_lock(&adev->pm.mutex);
935 ret = smu_get_entrycount_gfxoff(smu, value);
936 mutex_unlock(&adev->pm.mutex);
937
938 return ret;
939}
940
941int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
942{
943 struct smu_context *smu = adev->powerplay.pp_handle;
944 int ret = 0;
945
946 if (!is_support_sw_smu(adev))
947 return -EOPNOTSUPP;
948
949 mutex_lock(&adev->pm.mutex);
950 ret = smu_get_status_gfxoff(smu, value);
951 mutex_unlock(&adev->pm.mutex);
952
953 return ret;
954}
955
956uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev)
957{
958 struct smu_context *smu = adev->powerplay.pp_handle;
959
960 if (!is_support_sw_smu(adev))
961 return 0;
962
963 return atomic64_read(&smu->throttle_int_counter);
964}
965
966/* amdgpu_dpm_gfx_state_change - Handle gfx power state change set
967 * @adev: amdgpu_device pointer
968 * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry)
969 *
970 */
971void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev,
972 enum gfx_change_state state)
973{
974 mutex_lock(&adev->pm.mutex);
975 if (adev->powerplay.pp_funcs &&
976 adev->powerplay.pp_funcs->gfx_state_change_set)
977 ((adev)->powerplay.pp_funcs->gfx_state_change_set(
978 (adev)->powerplay.pp_handle, state));
979 mutex_unlock(&adev->pm.mutex);
980}
981
982int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev,
983 void *umc_ecc)
984{
985 struct smu_context *smu = adev->powerplay.pp_handle;
986 int ret = 0;
987
988 if (!is_support_sw_smu(adev))
989 return -EOPNOTSUPP;
990
991 mutex_lock(&adev->pm.mutex);
992 ret = smu_get_ecc_info(smu, umc_ecc);
993 mutex_unlock(&adev->pm.mutex);
994
995 return ret;
996}
997
998struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev,
999 uint32_t idx)
1000{
1001 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1002 struct amd_vce_state *vstate = NULL;
1003
1004 if (!pp_funcs->get_vce_clock_state)
1005 return NULL;
1006
1007 mutex_lock(&adev->pm.mutex);
1008 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle,
1009 idx);
1010 mutex_unlock(&adev->pm.mutex);
1011
1012 return vstate;
1013}
1014
1015void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev,
1016 enum amd_pm_state_type *state)
1017{
1018 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1019
1020 mutex_lock(&adev->pm.mutex);
1021
1022 if (!pp_funcs->get_current_power_state) {
1023 *state = adev->pm.dpm.user_state;
1024 goto out;
1025 }
1026
1027 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle);
1028 if (*state < POWER_STATE_TYPE_DEFAULT ||
1029 *state > POWER_STATE_TYPE_INTERNAL_3DPERF)
1030 *state = adev->pm.dpm.user_state;
1031
1032out:
1033 mutex_unlock(&adev->pm.mutex);
1034}
1035
1036void amdgpu_dpm_set_power_state(struct amdgpu_device *adev,
1037 enum amd_pm_state_type state)
1038{
1039 mutex_lock(&adev->pm.mutex);
1040 adev->pm.dpm.user_state = state;
1041 mutex_unlock(&adev->pm.mutex);
1042
1043 if (is_support_sw_smu(adev))
1044 return;
1045
1046 if (amdgpu_dpm_dispatch_task(adev,
1047 AMD_PP_TASK_ENABLE_USER_STATE,
1048 &state) == -EOPNOTSUPP)
1049 amdgpu_dpm_compute_clocks(adev);
1050}
1051
1052enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev)
1053{
1054 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1055 enum amd_dpm_forced_level level;
1056
1057 if (!pp_funcs)
1058 return AMD_DPM_FORCED_LEVEL_AUTO;
1059
1060 mutex_lock(&adev->pm.mutex);
1061 if (pp_funcs->get_performance_level)
1062 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle);
1063 else
1064 level = adev->pm.dpm.forced_level;
1065 mutex_unlock(&adev->pm.mutex);
1066
1067 return level;
1068}
1069
1070static void amdgpu_dpm_enter_umd_state(struct amdgpu_device *adev)
1071{
1072 /* enter UMD Pstate */
1073 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
1074 AMD_PG_STATE_UNGATE);
1075 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
1076 AMD_CG_STATE_UNGATE);
1077}
1078
1079static void amdgpu_dpm_exit_umd_state(struct amdgpu_device *adev)
1080{
1081 /* exit UMD Pstate */
1082 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
1083 AMD_CG_STATE_GATE);
1084 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
1085 AMD_PG_STATE_GATE);
1086}
1087
1088int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
1089 enum amd_dpm_forced_level level)
1090{
1091 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1092 enum amd_dpm_forced_level current_level;
1093 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1094 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1095 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1096 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1097
1098 if (!pp_funcs || !pp_funcs->force_performance_level)
1099 return 0;
1100
1101 if (adev->pm.dpm.thermal_active)
1102 return -EINVAL;
1103
1104 current_level = amdgpu_dpm_get_performance_level(adev);
1105 if (current_level == level)
1106 return 0;
1107
1108 if (!(current_level & profile_mode_mask) &&
1109 (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT))
1110 return -EINVAL;
1111
1112 if (adev->asic_type == CHIP_RAVEN) {
1113 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
1114 if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1115 level == AMD_DPM_FORCED_LEVEL_MANUAL)
1116 amdgpu_gfx_off_ctrl(adev, false);
1117 else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL &&
1118 level != AMD_DPM_FORCED_LEVEL_MANUAL)
1119 amdgpu_gfx_off_ctrl(adev, true);
1120 }
1121 }
1122
1123 if (!(current_level & profile_mode_mask) && (level & profile_mode_mask))
1124 amdgpu_dpm_enter_umd_state(adev);
1125 else if ((current_level & profile_mode_mask) &&
1126 !(level & profile_mode_mask))
1127 amdgpu_dpm_exit_umd_state(adev);
1128
1129 mutex_lock(&adev->pm.mutex);
1130
1131 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle,
1132 level)) {
1133 mutex_unlock(&adev->pm.mutex);
1134 /* If new level failed, retain the umd state as before */
1135 if (!(current_level & profile_mode_mask) &&
1136 (level & profile_mode_mask))
1137 amdgpu_dpm_exit_umd_state(adev);
1138 else if ((current_level & profile_mode_mask) &&
1139 !(level & profile_mode_mask))
1140 amdgpu_dpm_enter_umd_state(adev);
1141
1142 return -EINVAL;
1143 }
1144
1145 adev->pm.dpm.forced_level = level;
1146
1147 mutex_unlock(&adev->pm.mutex);
1148
1149 return 0;
1150}
1151
1152int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev,
1153 struct pp_states_info *states)
1154{
1155 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1156 int ret = 0;
1157
1158 if (!pp_funcs->get_pp_num_states)
1159 return -EOPNOTSUPP;
1160
1161 mutex_lock(&adev->pm.mutex);
1162 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle,
1163 states);
1164 mutex_unlock(&adev->pm.mutex);
1165
1166 return ret;
1167}
1168
1169int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev,
1170 enum amd_pp_task task_id,
1171 enum amd_pm_state_type *user_state)
1172{
1173 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1174 int ret = 0;
1175
1176 if (!pp_funcs->dispatch_tasks)
1177 return -EOPNOTSUPP;
1178
1179 mutex_lock(&adev->pm.mutex);
1180 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle,
1181 task_id,
1182 user_state);
1183 mutex_unlock(&adev->pm.mutex);
1184
1185 return ret;
1186}
1187
1188static bool amdgpu_dpm_is_pp_table_allowed(struct amdgpu_device *adev)
1189{
1190 return !amdgpu_sriov_vf(adev) &&
1191 !(adev->flags & AMD_IS_APU) &&
1192 !adev->scpm_enabled;
1193}
1194
1195int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char *table,
1196 size_t size)
1197{
1198 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1199 char *pptable = NULL;
1200 int ret = 0;
1201
1202 if ((!table && size) || (table && !size))
1203 return -EINVAL;
1204
1205 if (!amdgpu_dpm_is_pp_table_allowed(adev) ||
1206 !pp_funcs->get_pp_table)
1207 return -EOPNOTSUPP;
1208
1209 mutex_lock(&adev->pm.mutex);
1210 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle,
1211 &pptable);
1212 if (ret > 0 && !pptable) {
1213 ret = -EINVAL;
1214 } else if (ret > 0 && table) {
1215 ret = min_t(size_t, ret, size);
1216 memcpy(table, pptable, ret);
1217 }
1218 mutex_unlock(&adev->pm.mutex);
1219
1220 return ret;
1221}
1222
1223int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev,
1224 uint32_t type,
1225 long *input,
1226 uint32_t size)
1227{
1228 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1229 int ret = 0;
1230
1231 if (!pp_funcs->set_fine_grain_clk_vol)
1232 return 0;
1233
1234 mutex_lock(&adev->pm.mutex);
1235 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle,
1236 type,
1237 input,
1238 size);
1239 mutex_unlock(&adev->pm.mutex);
1240
1241 return ret;
1242}
1243
1244int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev,
1245 uint32_t type,
1246 long *input,
1247 uint32_t size)
1248{
1249 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1250 int ret = 0;
1251
1252 if (!pp_funcs->odn_edit_dpm_table)
1253 return 0;
1254
1255 mutex_lock(&adev->pm.mutex);
1256 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle,
1257 type,
1258 input,
1259 size);
1260 mutex_unlock(&adev->pm.mutex);
1261
1262 return ret;
1263}
1264
1265int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev,
1266 enum pp_clock_type type,
1267 char *buf,
1268 int *offset)
1269{
1270 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1271 int ret = 0;
1272
1273 if (!pp_funcs->emit_clock_levels)
1274 return -ENOENT;
1275
1276 mutex_lock(&adev->pm.mutex);
1277 ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle,
1278 type,
1279 buf,
1280 offset);
1281 mutex_unlock(&adev->pm.mutex);
1282
1283 return ret;
1284}
1285
1286int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev,
1287 uint64_t ppfeature_masks)
1288{
1289 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1290 int ret = 0;
1291
1292 if (!pp_funcs->set_ppfeature_status)
1293 return 0;
1294
1295 mutex_lock(&adev->pm.mutex);
1296 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle,
1297 ppfeature_masks);
1298 mutex_unlock(&adev->pm.mutex);
1299
1300 return ret;
1301}
1302
1303int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf)
1304{
1305 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1306 int ret = 0;
1307
1308 if (!pp_funcs->get_ppfeature_status)
1309 return 0;
1310
1311 mutex_lock(&adev->pm.mutex);
1312 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle,
1313 buf);
1314 mutex_unlock(&adev->pm.mutex);
1315
1316 return ret;
1317}
1318
1319int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev,
1320 enum pp_clock_type type,
1321 uint32_t mask)
1322{
1323 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1324 int ret = 0;
1325
1326 if (!pp_funcs->force_clock_level)
1327 return 0;
1328
1329 mutex_lock(&adev->pm.mutex);
1330 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle,
1331 type,
1332 mask);
1333 mutex_unlock(&adev->pm.mutex);
1334
1335 return ret;
1336}
1337
1338int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev)
1339{
1340 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1341 int ret = 0;
1342
1343 if (!pp_funcs->get_sclk_od)
1344 return -EOPNOTSUPP;
1345
1346 mutex_lock(&adev->pm.mutex);
1347 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle);
1348 mutex_unlock(&adev->pm.mutex);
1349
1350 return ret;
1351}
1352
1353int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
1354{
1355 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1356
1357 if (is_support_sw_smu(adev))
1358 return -EOPNOTSUPP;
1359
1360 mutex_lock(&adev->pm.mutex);
1361 if (pp_funcs->set_sclk_od)
1362 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value);
1363 mutex_unlock(&adev->pm.mutex);
1364
1365 if (amdgpu_dpm_dispatch_task(adev,
1366 AMD_PP_TASK_READJUST_POWER_STATE,
1367 NULL) == -EOPNOTSUPP) {
1368 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1369 amdgpu_dpm_compute_clocks(adev);
1370 }
1371
1372 return 0;
1373}
1374
1375int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev)
1376{
1377 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1378 int ret = 0;
1379
1380 if (!pp_funcs->get_mclk_od)
1381 return -EOPNOTSUPP;
1382
1383 mutex_lock(&adev->pm.mutex);
1384 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle);
1385 mutex_unlock(&adev->pm.mutex);
1386
1387 return ret;
1388}
1389
1390int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
1391{
1392 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1393
1394 if (is_support_sw_smu(adev))
1395 return -EOPNOTSUPP;
1396
1397 mutex_lock(&adev->pm.mutex);
1398 if (pp_funcs->set_mclk_od)
1399 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value);
1400 mutex_unlock(&adev->pm.mutex);
1401
1402 if (amdgpu_dpm_dispatch_task(adev,
1403 AMD_PP_TASK_READJUST_POWER_STATE,
1404 NULL) == -EOPNOTSUPP) {
1405 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1406 amdgpu_dpm_compute_clocks(adev);
1407 }
1408
1409 return 0;
1410}
1411
1412int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev,
1413 char *buf)
1414{
1415 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1416 int ret = 0;
1417
1418 if (!pp_funcs->get_power_profile_mode)
1419 return -EOPNOTSUPP;
1420
1421 mutex_lock(&adev->pm.mutex);
1422 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle,
1423 buf);
1424 mutex_unlock(&adev->pm.mutex);
1425
1426 return ret;
1427}
1428
1429int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev,
1430 long *input, uint32_t size)
1431{
1432 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1433 int ret = 0;
1434
1435 if (!pp_funcs->set_power_profile_mode)
1436 return 0;
1437
1438 mutex_lock(&adev->pm.mutex);
1439 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle,
1440 input,
1441 size);
1442 mutex_unlock(&adev->pm.mutex);
1443
1444 return ret;
1445}
1446
1447ssize_t amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void *buf,
1448 size_t size)
1449{
1450 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1451 void *table;
1452 ssize_t ret;
1453
1454 if (!pp_funcs->get_gpu_metrics)
1455 return 0;
1456
1457 mutex_lock(&adev->pm.mutex);
1458 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle,
1459 &table);
1460 if (ret > 0) {
1461 ret = min_t(ssize_t, ret, size);
1462 memcpy(buf, table, ret);
1463 }
1464 mutex_unlock(&adev->pm.mutex);
1465
1466 return ret;
1467}
1468
1469ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics,
1470 size_t size)
1471{
1472 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1473 int ret = 0;
1474
1475 if (!pp_funcs->get_pm_metrics)
1476 return -EOPNOTSUPP;
1477
1478 mutex_lock(&adev->pm.mutex);
1479 ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics,
1480 size);
1481 mutex_unlock(&adev->pm.mutex);
1482
1483 return ret;
1484}
1485
1486int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev,
1487 uint32_t *fan_mode)
1488{
1489 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1490 int ret = 0;
1491
1492 if (!pp_funcs->get_fan_control_mode)
1493 return -EOPNOTSUPP;
1494
1495 mutex_lock(&adev->pm.mutex);
1496 ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle,
1497 fan_mode);
1498 mutex_unlock(&adev->pm.mutex);
1499
1500 return ret;
1501}
1502
1503int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev,
1504 uint32_t speed)
1505{
1506 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1507 int ret = 0;
1508
1509 if (!pp_funcs->set_fan_speed_pwm)
1510 return -EOPNOTSUPP;
1511
1512 mutex_lock(&adev->pm.mutex);
1513 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle,
1514 speed);
1515 mutex_unlock(&adev->pm.mutex);
1516
1517 return ret;
1518}
1519
1520int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev,
1521 uint32_t *speed)
1522{
1523 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1524 int ret = 0;
1525
1526 if (!pp_funcs->get_fan_speed_pwm)
1527 return -EOPNOTSUPP;
1528
1529 mutex_lock(&adev->pm.mutex);
1530 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle,
1531 speed);
1532 mutex_unlock(&adev->pm.mutex);
1533
1534 return ret;
1535}
1536
1537int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev,
1538 uint32_t *speed)
1539{
1540 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1541 int ret = 0;
1542
1543 if (!pp_funcs->get_fan_speed_rpm)
1544 return -EOPNOTSUPP;
1545
1546 mutex_lock(&adev->pm.mutex);
1547 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle,
1548 speed);
1549 mutex_unlock(&adev->pm.mutex);
1550
1551 return ret;
1552}
1553
1554int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev,
1555 uint32_t speed)
1556{
1557 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1558 int ret = 0;
1559
1560 if (!pp_funcs->set_fan_speed_rpm)
1561 return -EOPNOTSUPP;
1562
1563 mutex_lock(&adev->pm.mutex);
1564 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle,
1565 speed);
1566 mutex_unlock(&adev->pm.mutex);
1567
1568 return ret;
1569}
1570
1571int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev,
1572 uint32_t mode)
1573{
1574 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1575 int ret = 0;
1576
1577 if (!pp_funcs->set_fan_control_mode)
1578 return -EOPNOTSUPP;
1579
1580 mutex_lock(&adev->pm.mutex);
1581 ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle,
1582 mode);
1583 mutex_unlock(&adev->pm.mutex);
1584
1585 return ret;
1586}
1587
1588int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev,
1589 uint32_t *limit,
1590 enum pp_power_limit_level pp_limit_level,
1591 enum pp_power_type power_type)
1592{
1593 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1594 int ret = 0;
1595
1596 if (!pp_funcs->get_power_limit)
1597 return -EOPNOTSUPP;
1598
1599 mutex_lock(&adev->pm.mutex);
1600 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle,
1601 limit,
1602 pp_limit_level,
1603 power_type);
1604 mutex_unlock(&adev->pm.mutex);
1605
1606 return ret;
1607}
1608
1609int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev,
1610 uint32_t limit_type,
1611 uint32_t limit)
1612{
1613 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1614 int ret = 0;
1615
1616 if (!pp_funcs->set_power_limit)
1617 return -EINVAL;
1618
1619 mutex_lock(&adev->pm.mutex);
1620 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle,
1621 limit_type, limit);
1622 mutex_unlock(&adev->pm.mutex);
1623
1624 return ret;
1625}
1626
1627int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev)
1628{
1629 bool cclk_dpm_supported = false;
1630
1631 if (!is_support_sw_smu(adev))
1632 return false;
1633
1634 mutex_lock(&adev->pm.mutex);
1635 cclk_dpm_supported = is_support_cclk_dpm(adev);
1636 mutex_unlock(&adev->pm.mutex);
1637
1638 return (int)cclk_dpm_supported;
1639}
1640
1641int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
1642 struct seq_file *m)
1643{
1644 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1645
1646 if (!pp_funcs->debugfs_print_current_performance_level)
1647 return -EOPNOTSUPP;
1648
1649 mutex_lock(&adev->pm.mutex);
1650 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle,
1651 m);
1652 mutex_unlock(&adev->pm.mutex);
1653
1654 return 0;
1655}
1656
1657int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev,
1658 void **addr,
1659 size_t *size)
1660{
1661 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1662 int ret = 0;
1663
1664 if (!pp_funcs->get_smu_prv_buf_details)
1665 return -ENOSYS;
1666
1667 mutex_lock(&adev->pm.mutex);
1668 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle,
1669 addr,
1670 size);
1671 mutex_unlock(&adev->pm.mutex);
1672
1673 return ret;
1674}
1675
1676int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev)
1677{
1678 if (is_support_sw_smu(adev)) {
1679 struct smu_context *smu = adev->powerplay.pp_handle;
1680
1681 return (smu->od_enabled || smu->is_apu);
1682 } else {
1683 struct pp_hwmgr *hwmgr;
1684
1685 /*
1686 * dpm on some legacy asics don't carry od_enabled member
1687 * as its pp_handle is casted directly from adev.
1688 */
1689 if (amdgpu_dpm_is_legacy_dpm(adev))
1690 return false;
1691
1692 hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle;
1693
1694 return hwmgr->od_enabled;
1695 }
1696}
1697
1698int amdgpu_dpm_is_overdrive_enabled(struct amdgpu_device *adev)
1699{
1700 if (is_support_sw_smu(adev)) {
1701 struct smu_context *smu = adev->powerplay.pp_handle;
1702
1703 return smu->od_enabled;
1704 } else {
1705 struct pp_hwmgr *hwmgr;
1706
1707 /*
1708 * dpm on some legacy asics don't carry od_enabled member
1709 * as its pp_handle is casted directly from adev.
1710 */
1711 if (amdgpu_dpm_is_legacy_dpm(adev))
1712 return false;
1713
1714 hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle;
1715
1716 return hwmgr->od_enabled;
1717 }
1718}
1719
1720int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
1721 const char *buf,
1722 size_t size)
1723{
1724 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1725 int ret = 0;
1726
1727 if (!buf || !size)
1728 return -EINVAL;
1729
1730 if (!amdgpu_dpm_is_pp_table_allowed(adev) ||
1731 !pp_funcs->set_pp_table)
1732 return -EOPNOTSUPP;
1733
1734 mutex_lock(&adev->pm.mutex);
1735 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle,
1736 buf,
1737 size);
1738 mutex_unlock(&adev->pm.mutex);
1739
1740 return ret;
1741}
1742
1743int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev)
1744{
1745 struct smu_context *smu = adev->powerplay.pp_handle;
1746
1747 if (!is_support_sw_smu(adev))
1748 return INT_MAX;
1749
1750 return smu->cpu_core_num;
1751}
1752
1753void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev)
1754{
1755 if (!is_support_sw_smu(adev))
1756 return;
1757
1758 amdgpu_smu_stb_debug_fs_init(adev);
1759}
1760
1761int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev,
1762 const struct amd_pp_display_configuration *input)
1763{
1764 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1765 int ret = 0;
1766
1767 if (!pp_funcs->display_configuration_change)
1768 return 0;
1769
1770 mutex_lock(&adev->pm.mutex);
1771 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle,
1772 input);
1773 mutex_unlock(&adev->pm.mutex);
1774
1775 return ret;
1776}
1777
1778int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev,
1779 enum amd_pp_clock_type type,
1780 struct amd_pp_clocks *clocks)
1781{
1782 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1783 int ret = 0;
1784
1785 if (!pp_funcs->get_clock_by_type)
1786 return 0;
1787
1788 mutex_lock(&adev->pm.mutex);
1789 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle,
1790 type,
1791 clocks);
1792 mutex_unlock(&adev->pm.mutex);
1793
1794 return ret;
1795}
1796
1797int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev,
1798 struct amd_pp_simple_clock_info *clocks)
1799{
1800 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1801 int ret = 0;
1802
1803 if (!pp_funcs->get_display_mode_validation_clocks)
1804 return 0;
1805
1806 mutex_lock(&adev->pm.mutex);
1807 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle,
1808 clocks);
1809 mutex_unlock(&adev->pm.mutex);
1810
1811 return ret;
1812}
1813
1814int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev,
1815 enum amd_pp_clock_type type,
1816 struct pp_clock_levels_with_latency *clocks)
1817{
1818 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1819 int ret = 0;
1820
1821 if (!pp_funcs->get_clock_by_type_with_latency)
1822 return 0;
1823
1824 mutex_lock(&adev->pm.mutex);
1825 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle,
1826 type,
1827 clocks);
1828 mutex_unlock(&adev->pm.mutex);
1829
1830 return ret;
1831}
1832
1833int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev,
1834 enum amd_pp_clock_type type,
1835 struct pp_clock_levels_with_voltage *clocks)
1836{
1837 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1838 int ret = 0;
1839
1840 if (!pp_funcs->get_clock_by_type_with_voltage)
1841 return 0;
1842
1843 mutex_lock(&adev->pm.mutex);
1844 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle,
1845 type,
1846 clocks);
1847 mutex_unlock(&adev->pm.mutex);
1848
1849 return ret;
1850}
1851
1852int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev,
1853 void *clock_ranges)
1854{
1855 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1856 int ret = 0;
1857
1858 if (!pp_funcs->set_watermarks_for_clocks_ranges)
1859 return -EOPNOTSUPP;
1860
1861 mutex_lock(&adev->pm.mutex);
1862 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle,
1863 clock_ranges);
1864 mutex_unlock(&adev->pm.mutex);
1865
1866 return ret;
1867}
1868
1869int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev,
1870 struct pp_display_clock_request *clock)
1871{
1872 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1873 int ret = 0;
1874
1875 if (!pp_funcs->display_clock_voltage_request)
1876 return -EOPNOTSUPP;
1877
1878 mutex_lock(&adev->pm.mutex);
1879 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle,
1880 clock);
1881 mutex_unlock(&adev->pm.mutex);
1882
1883 return ret;
1884}
1885
1886int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev,
1887 struct amd_pp_clock_info *clocks)
1888{
1889 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1890 int ret = 0;
1891
1892 if (!pp_funcs->get_current_clocks)
1893 return -EOPNOTSUPP;
1894
1895 mutex_lock(&adev->pm.mutex);
1896 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle,
1897 clocks);
1898 mutex_unlock(&adev->pm.mutex);
1899
1900 return ret;
1901}
1902
1903void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev)
1904{
1905 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1906
1907 if (!pp_funcs->notify_smu_enable_pwe)
1908 return;
1909
1910 mutex_lock(&adev->pm.mutex);
1911 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle);
1912 mutex_unlock(&adev->pm.mutex);
1913}
1914
1915int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev,
1916 uint32_t count)
1917{
1918 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1919 int ret = 0;
1920
1921 if (!pp_funcs->set_active_display_count)
1922 return -EOPNOTSUPP;
1923
1924 mutex_lock(&adev->pm.mutex);
1925 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle,
1926 count);
1927 mutex_unlock(&adev->pm.mutex);
1928
1929 return ret;
1930}
1931
1932int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev,
1933 uint32_t clock)
1934{
1935 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1936 int ret = 0;
1937
1938 if (!pp_funcs->set_min_deep_sleep_dcefclk)
1939 return -EOPNOTSUPP;
1940
1941 mutex_lock(&adev->pm.mutex);
1942 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle,
1943 clock);
1944 mutex_unlock(&adev->pm.mutex);
1945
1946 return ret;
1947}
1948
1949void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev,
1950 uint32_t clock)
1951{
1952 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1953
1954 if (!pp_funcs->set_hard_min_dcefclk_by_freq)
1955 return;
1956
1957 mutex_lock(&adev->pm.mutex);
1958 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle,
1959 clock);
1960 mutex_unlock(&adev->pm.mutex);
1961}
1962
1963void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev,
1964 uint32_t clock)
1965{
1966 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1967
1968 if (!pp_funcs->set_hard_min_fclk_by_freq)
1969 return;
1970
1971 mutex_lock(&adev->pm.mutex);
1972 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle,
1973 clock);
1974 mutex_unlock(&adev->pm.mutex);
1975}
1976
1977int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev,
1978 bool disable_memory_clock_switch)
1979{
1980 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1981 int ret = 0;
1982
1983 if (!pp_funcs->display_disable_memory_clock_switch)
1984 return 0;
1985
1986 mutex_lock(&adev->pm.mutex);
1987 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle,
1988 disable_memory_clock_switch);
1989 mutex_unlock(&adev->pm.mutex);
1990
1991 return ret;
1992}
1993
1994int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev,
1995 struct pp_smu_nv_clock_table *max_clocks)
1996{
1997 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1998 int ret = 0;
1999
2000 if (!pp_funcs->get_max_sustainable_clocks_by_dc)
2001 return -EOPNOTSUPP;
2002
2003 mutex_lock(&adev->pm.mutex);
2004 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle,
2005 max_clocks);
2006 mutex_unlock(&adev->pm.mutex);
2007
2008 return ret;
2009}
2010
2011enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,
2012 unsigned int *clock_values_in_khz,
2013 unsigned int *num_states)
2014{
2015 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2016 int ret = 0;
2017
2018 if (!pp_funcs->get_uclk_dpm_states)
2019 return -EOPNOTSUPP;
2020
2021 mutex_lock(&adev->pm.mutex);
2022 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle,
2023 clock_values_in_khz,
2024 num_states);
2025 mutex_unlock(&adev->pm.mutex);
2026
2027 return ret;
2028}
2029
2030int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev,
2031 struct dpm_clocks *clock_table)
2032{
2033 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2034 int ret = 0;
2035
2036 if (!pp_funcs->get_dpm_clock_table)
2037 return -EOPNOTSUPP;
2038
2039 mutex_lock(&adev->pm.mutex);
2040 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle,
2041 clock_table);
2042 mutex_unlock(&adev->pm.mutex);
2043
2044 return ret;
2045}
2046
2047/**
2048 * amdgpu_dpm_get_temp_metrics - Retrieve metrics for a specific compute
2049 * partition
2050 * @adev: Pointer to the device.
2051 * @type: Identifier for the temperature type metrics to be fetched.
2052 * @table: Pointer to a buffer where the metrics will be stored. If NULL, the
2053 * function returns the size of the metrics structure.
2054 *
2055 * This function retrieves metrics for a specific temperature type, If the
2056 * table parameter is NULL, the function returns the size of the metrics
2057 * structure without populating it.
2058 *
2059 * Return: Size of the metrics structure on success, or a negative error code on failure.
2060 */
2061ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev,
2062 enum smu_temp_metric_type type, void *table)
2063{
2064 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2065 int ret;
2066
2067 if (!pp_funcs->get_temp_metrics ||
2068 !amdgpu_dpm_is_temp_metrics_supported(adev, type))
2069 return -EOPNOTSUPP;
2070
2071 mutex_lock(&adev->pm.mutex);
2072 ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table);
2073 mutex_unlock(&adev->pm.mutex);
2074
2075 return ret;
2076}
2077
2078/**
2079 * amdgpu_dpm_is_temp_metrics_supported - Return if specific temperature metrics support
2080 * is available
2081 * @adev: Pointer to the device.
2082 * @type: Identifier for the temperature type metrics to be fetched.
2083 *
2084 * This function returns metrics if specific temperature metrics type is supported or not.
2085 *
2086 * Return: True in case of metrics type supported else false.
2087 */
2088bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev,
2089 enum smu_temp_metric_type type)
2090{
2091 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2092 bool support_temp_metrics = false;
2093
2094 if (!pp_funcs->temp_metrics_is_supported)
2095 return support_temp_metrics;
2096
2097 if (is_support_sw_smu(adev)) {
2098 mutex_lock(&adev->pm.mutex);
2099 support_temp_metrics =
2100 pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type);
2101 mutex_unlock(&adev->pm.mutex);
2102 }
2103
2104 return support_temp_metrics;
2105}
2106
2107/**
2108 * amdgpu_dpm_get_xcp_metrics - Retrieve metrics for a specific compute
2109 * partition
2110 * @adev: Pointer to the device.
2111 * @xcp_id: Identifier of the XCP for which metrics are to be retrieved.
2112 * @table: Pointer to a buffer where the metrics will be stored. If NULL, the
2113 * function returns the size of the metrics structure.
2114 *
2115 * This function retrieves metrics for a specific XCP, including details such as
2116 * VCN/JPEG activity, clock frequencies, and other performance metrics. If the
2117 * table parameter is NULL, the function returns the size of the metrics
2118 * structure without populating it.
2119 *
2120 * Return: Size of the metrics structure on success, or a negative error code on failure.
2121 */
2122ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id,
2123 void *table)
2124{
2125 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2126 int ret = 0;
2127
2128 if (!pp_funcs->get_xcp_metrics)
2129 return 0;
2130
2131 mutex_lock(&adev->pm.mutex);
2132 ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id,
2133 table);
2134 mutex_unlock(&adev->pm.mutex);
2135
2136 return ret;
2137}