| 1 | |
| 2 | * Copyright 2017 Advanced Micro Devices, Inc.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice shall be included in
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| 12 | * all copies or substantial portions of the Software.
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| 13 | *
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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| 20 | * OTHER DEALINGS IN THE SOFTWARE.
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| 21 | *
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| 22 | * Authors: Rafał Miłecki <[email protected]>
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| 23 | * Alex Deucher <[email protected]>
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| 24 |
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| 25 |
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| 26 | #include "amdgpu.h"
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| 27 | #include "amdgpu_drv.h"
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| 28 | #include "amdgpu_pm.h"
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| 29 | #include "amdgpu_dpm.h"
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| 30 | #include "atom.h"
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| 31 | #include <linux/pci.h>
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| 32 | #include <linux/hwmon.h>
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| 33 | #include <linux/hwmon-sysfs.h>
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| 34 | #include <linux/nospec.h>
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| 35 | #include <linux/pm_runtime.h>
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| 36 | #include <linux/string_choices.h>
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| 37 | #include <linux/units.h>
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| 38 | #include <asm/processor.h>
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| 39 |
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| 40 | #define MAX_NUM_OF_FEATURES_PER_SUBSET 8
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| 41 | #define MAX_NUM_OF_SUBSETS 8
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| 42 |
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| 43 | #define DEVICE_ATTR_IS(_name) (attr_id == device_attr_id__##_name)
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| 44 |
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| 45 | struct od_attribute {
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| 46 | struct kobj_attribute attribute;
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| 47 | struct list_head entry;
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| 48 | };
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| 49 |
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| 50 | struct od_kobj {
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| 51 | struct kobject kobj;
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| 52 | struct list_head entry;
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| 53 | struct list_head attribute;
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| 54 | void *priv;
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| 55 | };
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| 56 |
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| 57 | struct od_feature_ops {
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| 58 | umode_t (*is_visible)(struct amdgpu_device *adev);
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| 59 | ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
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| 60 | char *buf);
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| 61 | ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
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| 62 | const char *buf, size_t count);
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| 63 | };
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| 64 |
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| 65 | struct od_feature_item {
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| 66 | const char *name;
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| 67 | struct od_feature_ops ops;
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| 68 | };
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| 69 |
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| 70 | struct od_feature_container {
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| 71 | char *name;
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| 72 | struct od_feature_ops ops;
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| 73 | struct od_feature_item sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET];
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| 74 | };
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| 75 |
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| 76 | struct od_feature_set {
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| 77 | struct od_feature_container containers[MAX_NUM_OF_SUBSETS];
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| 78 | };
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| 79 |
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| 80 | static const struct hwmon_temp_label {
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| 81 | enum PP_HWMON_TEMP channel;
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| 82 | const char *label;
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| 83 | } temp_label[] = {
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| 84 | {PP_TEMP_EDGE, "edge"},
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| 85 | {PP_TEMP_JUNCTION, "junction"},
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| 86 | {PP_TEMP_MEM, "mem"},
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| 87 | };
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| 88 |
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| 89 | const char * const amdgpu_pp_profile_name[] = {
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| 90 | "BOOTUP_DEFAULT",
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| 91 | "3D_FULL_SCREEN",
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| 92 | "POWER_SAVING",
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| 93 | "VIDEO",
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| 94 | "VR",
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| 95 | "COMPUTE",
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| 96 | "CUSTOM",
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| 97 | "WINDOW_3D",
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| 98 | "CAPPED",
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| 99 | "UNCAPPED",
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| 100 | };
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| 101 |
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| 102 | static int amdgpu_pm_parse_long_params(char *str, long *params,
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| 103 | uint32_t max_params,
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| 104 | uint32_t *num_params)
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| 105 | {
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| 106 | const char delimiter[] = { ' ', '\n', '\0' };
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| 107 | uint32_t count = 0;
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| 108 | char *sub_str;
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| 109 | int ret;
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| 110 |
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| 111 | if (!params || !num_params)
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| 112 | return -EINVAL;
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| 113 |
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| 114 | while ((sub_str = strsep(&str, delimiter)) != NULL) {
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| 115 | if (strlen(sub_str) == 0)
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| 116 | continue;
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| 117 | if (count >= max_params)
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| 118 | return -EINVAL;
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| 119 | ret = kstrtol(sub_str, 0, ¶ms[count]);
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| 120 | if (ret)
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| 121 | return -EINVAL;
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| 122 | count++;
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| 123 | if (!str)
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| 124 | break;
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| 125 | while (isspace(*str))
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| 126 | str++;
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| 127 | }
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| 128 | *num_params = count;
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| 129 |
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| 130 | return 0;
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| 131 | }
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| 132 |
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| 133 | |
| 134 | * amdgpu_pm_dev_state_check - Check if device can be accessed.
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| 135 | * @adev: Target device.
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| 136 | * @runpm: Check runpm status for suspend state checks.
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| 137 | *
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| 138 | * Checks the state of the @adev for access. Return 0 if the device is
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| 139 | * accessible or a negative error code otherwise.
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| 140 |
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| 141 | static int amdgpu_pm_dev_state_check(struct amdgpu_device *adev, bool runpm)
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| 142 | {
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| 143 | bool runpm_check = runpm ? adev->in_runpm : false;
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| 144 | bool full_init = (adev->init_lvl->level == AMDGPU_INIT_LEVEL_DEFAULT);
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| 145 |
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| 146 | if (amdgpu_in_reset(adev) || !full_init)
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| 147 | return -EBUSY;
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| 148 |
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| 149 | if (adev->in_suspend && !runpm_check)
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| 150 | return -EBUSY;
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| 151 |
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| 152 | return 0;
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| 153 | }
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| 154 |
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| 155 | |
| 156 | * amdgpu_pm_get_access - Check if device can be accessed, resume if needed.
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| 157 | * @adev: Target device.
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| 158 | *
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| 159 | * Checks the state of the @adev for access. Use runtime pm API to resume if
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| 160 | * needed. Return 0 if the device is accessible or a negative error code
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| 161 | * otherwise.
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| 162 |
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| 163 | static int amdgpu_pm_get_access(struct amdgpu_device *adev)
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| 164 | {
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| 165 | int ret;
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| 166 |
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| 167 | ret = amdgpu_pm_dev_state_check(adev, true);
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| 168 | if (ret)
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| 169 | return ret;
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| 170 |
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| 171 | return pm_runtime_resume_and_get(adev->dev);
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| 172 | }
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| 173 |
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| 174 | |
| 175 | * amdgpu_pm_get_access_if_active - Check if device is active for access.
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| 176 | * @adev: Target device.
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| 177 | *
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| 178 | * Checks the state of the @adev for access. Use runtime pm API to determine
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| 179 | * if device is active. Allow access only if device is active.Return 0 if the
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| 180 | * device is accessible or a negative error code otherwise.
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| 181 |
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| 182 | static int amdgpu_pm_get_access_if_active(struct amdgpu_device *adev)
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| 183 | {
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| 184 | int ret;
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| 185 |
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| 186 |
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| 187 | ret = amdgpu_pm_dev_state_check(adev, false);
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| 188 | if (ret)
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| 189 | return ret;
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| 190 |
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| 191 | |
| 192 | * Allow only if device is active. If runpm is disabled also, as in
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| 193 | * kernels without CONFIG_PM, allow access.
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| 194 |
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| 195 | ret = pm_runtime_get_if_active(adev->dev);
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| 196 | if (!ret)
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| 197 | return -EPERM;
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| 198 |
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| 199 | return 0;
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| 200 | }
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| 201 |
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| 202 | |
| 203 | * amdgpu_pm_put_access - Put to auto suspend mode after a device access.
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| 204 | * @adev: Target device.
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| 205 | *
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| 206 | * Should be paired with amdgpu_pm_get_access* calls
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| 207 |
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| 208 | static inline void amdgpu_pm_put_access(struct amdgpu_device *adev)
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| 209 | {
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| 210 | pm_runtime_put_autosuspend(adev->dev);
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| 211 | }
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| 212 |
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| 213 | |
| 214 | * DOC: power_dpm_state
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| 215 | *
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| 216 | * The power_dpm_state file is a legacy interface and is only provided for
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| 217 | * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
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| 218 | * certain power related parameters. The file power_dpm_state is used for this.
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| 219 | * It accepts the following arguments:
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| 220 | *
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| 221 | * - battery
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| 222 | *
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| 223 | * - balanced
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| 224 | *
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| 225 | * - performance
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| 226 | *
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| 227 | * battery
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| 228 | *
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| 229 | * On older GPUs, the vbios provided a special power state for battery
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| 230 | * operation. Selecting battery switched to this state. This is no
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| 231 | * longer provided on newer GPUs so the option does nothing in that case.
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| 232 | *
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| 233 | * balanced
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| 234 | *
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| 235 | * On older GPUs, the vbios provided a special power state for balanced
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| 236 | * operation. Selecting balanced switched to this state. This is no
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| 237 | * longer provided on newer GPUs so the option does nothing in that case.
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| 238 | *
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| 239 | * performance
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| 240 | *
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| 241 | * On older GPUs, the vbios provided a special power state for performance
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| 242 | * operation. Selecting performance switched to this state. This is no
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| 243 | * longer provided on newer GPUs so the option does nothing in that case.
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| 244 | *
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| 245 |
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| 246 |
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| 247 | static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
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| 248 | struct device_attribute *attr,
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| 249 | char *buf)
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| 250 | {
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| 251 | struct drm_device *ddev = dev_get_drvdata(dev);
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| 252 | struct amdgpu_device *adev = drm_to_adev(ddev);
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| 253 | enum amd_pm_state_type pm;
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| 254 | int ret;
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| 255 |
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| 256 | ret = amdgpu_pm_get_access_if_active(adev);
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| 257 | if (ret)
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| 258 | return ret;
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| 259 |
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| 260 | amdgpu_dpm_get_current_power_state(adev, &pm);
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| 261 |
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| 262 | amdgpu_pm_put_access(adev);
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| 263 |
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| 264 | return sysfs_emit(buf, "%s\n",
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| 265 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
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| 266 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
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| 267 | }
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| 268 |
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| 269 | static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
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| 270 | struct device_attribute *attr,
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| 271 | const char *buf,
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| 272 | size_t count)
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| 273 | {
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| 274 | struct drm_device *ddev = dev_get_drvdata(dev);
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| 275 | struct amdgpu_device *adev = drm_to_adev(ddev);
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| 276 | enum amd_pm_state_type state;
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| 277 | int ret;
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| 278 |
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| 279 |
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| 280 | if (count == 0 || sysfs_streq(buf, ""))
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| 281 | return -EINVAL;
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| 282 |
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| 283 | if (sysfs_streq(buf, "battery"))
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| 284 | state = POWER_STATE_TYPE_BATTERY;
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| 285 | else if (sysfs_streq(buf, "balanced"))
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| 286 | state = POWER_STATE_TYPE_BALANCED;
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| 287 | else if (sysfs_streq(buf, "performance"))
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| 288 | state = POWER_STATE_TYPE_PERFORMANCE;
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| 289 | else
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| 290 | return -EINVAL;
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| 291 |
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| 292 | ret = amdgpu_pm_get_access(adev);
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| 293 | if (ret < 0)
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| 294 | return ret;
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| 295 |
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| 296 | amdgpu_dpm_set_power_state(adev, state);
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| 297 |
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| 298 | amdgpu_pm_put_access(adev);
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| 299 |
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| 300 | return count;
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| 301 | }
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| 302 |
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| 303 |
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| 304 | |
| 305 | * DOC: power_dpm_force_performance_level
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| 306 | *
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| 307 | * The amdgpu driver provides a sysfs API for adjusting certain power
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| 308 | * related parameters. The file power_dpm_force_performance_level is
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| 309 | * used for this. It accepts the following arguments:
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| 310 | *
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| 311 | * - auto
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| 312 | *
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| 313 | * - low
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| 314 | *
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| 315 | * - high
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| 316 | *
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| 317 | * - manual
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| 318 | *
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| 319 | * - profile_standard
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| 320 | *
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| 321 | * - profile_min_sclk
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| 322 | *
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| 323 | * - profile_min_mclk
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| 324 | *
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| 325 | * - profile_peak
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| 326 | *
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| 327 | * auto
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| 328 | *
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| 329 | * When auto is selected, the driver will attempt to dynamically select
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| 330 | * the optimal power profile for current conditions in the driver.
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| 331 | *
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| 332 | * low
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| 333 | *
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| 334 | * When low is selected, the clocks are forced to the lowest power state.
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| 335 | *
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| 336 | * high
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| 337 | *
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| 338 | * When high is selected, the clocks are forced to the highest power state.
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| 339 | *
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| 340 | * manual
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| 341 | *
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| 342 | * When manual is selected, the user can manually adjust which power states
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| 343 | * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
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| 344 | * and pp_dpm_pcie files and adjust the power state transition heuristics
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| 345 | * via the pp_power_profile_mode sysfs file.
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| 346 | *
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| 347 | * profile_standard
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| 348 | * profile_min_sclk
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| 349 | * profile_min_mclk
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| 350 | * profile_peak
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| 351 | *
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| 352 | * When the profiling modes are selected, clock and power gating are
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| 353 | * disabled and the clocks are set for different profiling cases. This
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| 354 | * mode is recommended for profiling specific work loads where you do
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| 355 | * not want clock or power gating for clock fluctuation to interfere
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| 356 | * with your results. profile_standard sets the clocks to a fixed clock
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| 357 | * level which varies from asic to asic. profile_min_sclk forces the sclk
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| 358 | * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
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| 359 | * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
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| 360 | *
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| 361 |
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| 362 |
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| 363 | static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
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| 364 | struct device_attribute *attr,
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| 365 | char *buf)
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| 366 | {
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| 367 | struct drm_device *ddev = dev_get_drvdata(dev);
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| 368 | struct amdgpu_device *adev = drm_to_adev(ddev);
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| 369 | enum amd_dpm_forced_level level = 0xff;
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| 370 | int ret;
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| 371 |
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| 372 | ret = amdgpu_pm_get_access_if_active(adev);
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| 373 | if (ret)
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| 374 | return ret;
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| 375 |
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| 376 | level = amdgpu_dpm_get_performance_level(adev);
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| 377 |
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| 378 | amdgpu_pm_put_access(adev);
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| 379 |
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| 380 | return sysfs_emit(buf, "%s\n",
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| 381 | (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
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| 382 | (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
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| 383 | (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
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| 384 | (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
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| 385 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
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| 386 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
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| 387 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
|
| 388 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
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| 389 | (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
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| 390 | "unknown");
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| 391 | }
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| 392 |
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| 393 | static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
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| 394 | struct device_attribute *attr,
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| 395 | const char *buf,
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| 396 | size_t count)
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| 397 | {
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| 398 | struct drm_device *ddev = dev_get_drvdata(dev);
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| 399 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 400 | enum amd_dpm_forced_level level;
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| 401 | int ret = 0;
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| 402 |
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| 403 |
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| 404 | if (count == 0 || sysfs_streq(buf, ""))
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| 405 | return -EINVAL;
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| 406 |
|
| 407 | if (sysfs_streq(buf, "low"))
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| 408 | level = AMD_DPM_FORCED_LEVEL_LOW;
|
| 409 | else if (sysfs_streq(buf, "high"))
|
| 410 | level = AMD_DPM_FORCED_LEVEL_HIGH;
|
| 411 | else if (sysfs_streq(buf, "auto"))
|
| 412 | level = AMD_DPM_FORCED_LEVEL_AUTO;
|
| 413 | else if (sysfs_streq(buf, "manual"))
|
| 414 | level = AMD_DPM_FORCED_LEVEL_MANUAL;
|
| 415 | else if (sysfs_streq(buf, "profile_exit"))
|
| 416 | level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
|
| 417 | else if (sysfs_streq(buf, "profile_standard"))
|
| 418 | level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
|
| 419 | else if (sysfs_streq(buf, "profile_min_sclk"))
|
| 420 | level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
|
| 421 | else if (sysfs_streq(buf, "profile_min_mclk"))
|
| 422 | level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
|
| 423 | else if (sysfs_streq(buf, "profile_peak"))
|
| 424 | level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
|
| 425 | else if (sysfs_streq(buf, "perf_determinism"))
|
| 426 | level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
|
| 427 | else
|
| 428 | return -EINVAL;
|
| 429 |
|
| 430 | ret = amdgpu_pm_get_access(adev);
|
| 431 | if (ret < 0)
|
| 432 | return ret;
|
| 433 |
|
| 434 | mutex_lock(&adev->pm.stable_pstate_ctx_lock);
|
| 435 | if (amdgpu_dpm_force_performance_level(adev, level)) {
|
| 436 | amdgpu_pm_put_access(adev);
|
| 437 | mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
|
| 438 | return -EINVAL;
|
| 439 | }
|
| 440 |
|
| 441 | adev->pm.stable_pstate_ctx = NULL;
|
| 442 | mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
|
| 443 |
|
| 444 | amdgpu_pm_put_access(adev);
|
| 445 |
|
| 446 | return count;
|
| 447 | }
|
| 448 |
|
| 449 | static ssize_t amdgpu_get_pp_num_states(struct device *dev,
|
| 450 | struct device_attribute *attr,
|
| 451 | char *buf)
|
| 452 | {
|
| 453 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 454 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 455 | struct pp_states_info data;
|
| 456 | uint32_t i;
|
| 457 | int buf_len, ret;
|
| 458 |
|
| 459 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 460 | if (ret)
|
| 461 | return ret;
|
| 462 |
|
| 463 | if (amdgpu_dpm_get_pp_num_states(adev, &data))
|
| 464 | memset(&data, 0, sizeof(data));
|
| 465 |
|
| 466 | amdgpu_pm_put_access(adev);
|
| 467 |
|
| 468 | buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
|
| 469 | for (i = 0; i < data.nums; i++)
|
| 470 | buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
|
| 471 | (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
|
| 472 | (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
|
| 473 | (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
|
| 474 | (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
|
| 475 |
|
| 476 | return buf_len;
|
| 477 | }
|
| 478 |
|
| 479 | static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
|
| 480 | struct device_attribute *attr,
|
| 481 | char *buf)
|
| 482 | {
|
| 483 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 484 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 485 | struct pp_states_info data = {0};
|
| 486 | enum amd_pm_state_type pm = 0;
|
| 487 | int i = 0, ret = 0;
|
| 488 |
|
| 489 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 490 | if (ret)
|
| 491 | return ret;
|
| 492 |
|
| 493 | amdgpu_dpm_get_current_power_state(adev, &pm);
|
| 494 |
|
| 495 | ret = amdgpu_dpm_get_pp_num_states(adev, &data);
|
| 496 |
|
| 497 | amdgpu_pm_put_access(adev);
|
| 498 |
|
| 499 | if (ret)
|
| 500 | return ret;
|
| 501 |
|
| 502 | for (i = 0; i < data.nums; i++) {
|
| 503 | if (pm == data.states[i])
|
| 504 | break;
|
| 505 | }
|
| 506 |
|
| 507 | if (i == data.nums)
|
| 508 | i = -EINVAL;
|
| 509 |
|
| 510 | return sysfs_emit(buf, "%d\n", i);
|
| 511 | }
|
| 512 |
|
| 513 | static ssize_t amdgpu_get_pp_force_state(struct device *dev,
|
| 514 | struct device_attribute *attr,
|
| 515 | char *buf)
|
| 516 | {
|
| 517 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 518 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 519 |
|
| 520 | if (adev->pm.pp_force_state_enabled)
|
| 521 | return amdgpu_get_pp_cur_state(dev, attr, buf);
|
| 522 | else
|
| 523 | return sysfs_emit(buf, "\n");
|
| 524 | }
|
| 525 |
|
| 526 | static ssize_t amdgpu_set_pp_force_state(struct device *dev,
|
| 527 | struct device_attribute *attr,
|
| 528 | const char *buf,
|
| 529 | size_t count)
|
| 530 | {
|
| 531 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 532 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 533 | enum amd_pm_state_type state = 0;
|
| 534 | struct pp_states_info data;
|
| 535 | unsigned long idx;
|
| 536 | int ret;
|
| 537 |
|
| 538 | adev->pm.pp_force_state_enabled = false;
|
| 539 |
|
| 540 | if (strlen(buf) == 1)
|
| 541 | return count;
|
| 542 |
|
| 543 | ret = kstrtoul(buf, 0, &idx);
|
| 544 | if (ret || idx >= ARRAY_SIZE(data.states))
|
| 545 | return -EINVAL;
|
| 546 |
|
| 547 | idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
|
| 548 |
|
| 549 | ret = amdgpu_pm_get_access(adev);
|
| 550 | if (ret < 0)
|
| 551 | return ret;
|
| 552 |
|
| 553 | ret = amdgpu_dpm_get_pp_num_states(adev, &data);
|
| 554 | if (ret)
|
| 555 | goto err_out;
|
| 556 |
|
| 557 | state = data.states[idx];
|
| 558 |
|
| 559 |
|
| 560 | if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
|
| 561 | state != POWER_STATE_TYPE_DEFAULT) {
|
| 562 | ret = amdgpu_dpm_dispatch_task(adev,
|
| 563 | AMD_PP_TASK_ENABLE_USER_STATE, &state);
|
| 564 | if (ret)
|
| 565 | goto err_out;
|
| 566 |
|
| 567 | adev->pm.pp_force_state_enabled = true;
|
| 568 | }
|
| 569 |
|
| 570 | amdgpu_pm_put_access(adev);
|
| 571 |
|
| 572 | return count;
|
| 573 |
|
| 574 | err_out:
|
| 575 | amdgpu_pm_put_access(adev);
|
| 576 |
|
| 577 | return ret;
|
| 578 | }
|
| 579 |
|
| 580 | |
| 581 | * DOC: pp_table
|
| 582 | *
|
| 583 | * The amdgpu driver provides a sysfs API for uploading new powerplay
|
| 584 | * tables. The file pp_table is used for this. Reading the file
|
| 585 | * will dump the current power play table. Writing to the file
|
| 586 | * will attempt to upload a new powerplay table and re-initialize
|
| 587 | * powerplay using that new table.
|
| 588 | *
|
| 589 |
|
| 590 |
|
| 591 | static ssize_t amdgpu_get_pp_table(struct device *dev,
|
| 592 | struct device_attribute *attr,
|
| 593 | char *buf)
|
| 594 | {
|
| 595 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 596 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 597 | int size, ret;
|
| 598 |
|
| 599 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 600 | if (ret)
|
| 601 | return ret;
|
| 602 |
|
| 603 | size = amdgpu_dpm_get_pp_table(adev, buf, PAGE_SIZE - 1);
|
| 604 |
|
| 605 | amdgpu_pm_put_access(adev);
|
| 606 |
|
| 607 | if (size <= 0)
|
| 608 | return size;
|
| 609 |
|
| 610 | return size;
|
| 611 | }
|
| 612 |
|
| 613 | static ssize_t amdgpu_set_pp_table(struct device *dev,
|
| 614 | struct device_attribute *attr,
|
| 615 | const char *buf,
|
| 616 | size_t count)
|
| 617 | {
|
| 618 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 619 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 620 | int ret = 0;
|
| 621 |
|
| 622 | ret = amdgpu_pm_get_access(adev);
|
| 623 | if (ret < 0)
|
| 624 | return ret;
|
| 625 |
|
| 626 | ret = amdgpu_dpm_set_pp_table(adev, buf, count);
|
| 627 |
|
| 628 | amdgpu_pm_put_access(adev);
|
| 629 |
|
| 630 | if (ret)
|
| 631 | return ret;
|
| 632 |
|
| 633 | return count;
|
| 634 | }
|
| 635 |
|
| 636 | |
| 637 | * DOC: pp_od_clk_voltage
|
| 638 | *
|
| 639 | * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
|
| 640 | * in each power level within a power state. The pp_od_clk_voltage is used for
|
| 641 | * this.
|
| 642 | *
|
| 643 | * Note that the actual memory controller clock rate are exposed, not
|
| 644 | * the effective memory clock of the DRAMs. To translate it, use the
|
| 645 | * following formula:
|
| 646 | *
|
| 647 | * Clock conversion (Mhz):
|
| 648 | *
|
| 649 | * HBM: effective_memory_clock = memory_controller_clock * 1
|
| 650 | *
|
| 651 | * G5: effective_memory_clock = memory_controller_clock * 1
|
| 652 | *
|
| 653 | * G6: effective_memory_clock = memory_controller_clock * 2
|
| 654 | *
|
| 655 | * DRAM data rate (MT/s):
|
| 656 | *
|
| 657 | * HBM: effective_memory_clock * 2 = data_rate
|
| 658 | *
|
| 659 | * G5: effective_memory_clock * 4 = data_rate
|
| 660 | *
|
| 661 | * G6: effective_memory_clock * 8 = data_rate
|
| 662 | *
|
| 663 | * Bandwidth (MB/s):
|
| 664 | *
|
| 665 | * data_rate * vram_bit_width / 8 = memory_bandwidth
|
| 666 | *
|
| 667 | * Some examples:
|
| 668 | *
|
| 669 | * G5 on RX460:
|
| 670 | *
|
| 671 | * memory_controller_clock = 1750 Mhz
|
| 672 | *
|
| 673 | * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
|
| 674 | *
|
| 675 | * data rate = 1750 * 4 = 7000 MT/s
|
| 676 | *
|
| 677 | * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
|
| 678 | *
|
| 679 | * G6 on RX5700:
|
| 680 | *
|
| 681 | * memory_controller_clock = 875 Mhz
|
| 682 | *
|
| 683 | * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
|
| 684 | *
|
| 685 | * data rate = 1750 * 8 = 14000 MT/s
|
| 686 | *
|
| 687 | * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
|
| 688 | *
|
| 689 | * < For Vega10 and previous ASICs >
|
| 690 | *
|
| 691 | * Reading the file will display:
|
| 692 | *
|
| 693 | * - a list of engine clock levels and voltages labeled OD_SCLK
|
| 694 | *
|
| 695 | * - a list of memory clock levels and voltages labeled OD_MCLK
|
| 696 | *
|
| 697 | * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
|
| 698 | *
|
| 699 | * To manually adjust these settings, first select manual using
|
| 700 | * power_dpm_force_performance_level. Enter a new value for each
|
| 701 | * level by writing a string that contains "s/m level clock voltage" to
|
| 702 | * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
|
| 703 | * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
|
| 704 | * 810 mV. When you have edited all of the states as needed, write
|
| 705 | * "c" (commit) to the file to commit your changes. If you want to reset to the
|
| 706 | * default power levels, write "r" (reset) to the file to reset them.
|
| 707 | *
|
| 708 | *
|
| 709 | * < For Vega20 and newer ASICs >
|
| 710 | *
|
| 711 | * Reading the file will display:
|
| 712 | *
|
| 713 | * - minimum and maximum engine clock labeled OD_SCLK
|
| 714 | *
|
| 715 | * - minimum(not available for Vega20 and Navi1x) and maximum memory
|
| 716 | * clock labeled OD_MCLK
|
| 717 | *
|
| 718 | * - minimum and maximum fabric clock labeled OD_FCLK (SMU13)
|
| 719 | *
|
| 720 | * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
|
| 721 | * They can be used to calibrate the sclk voltage curve. This is
|
| 722 | * available for Vega20 and NV1X.
|
| 723 | *
|
| 724 | * - voltage offset(in mV) applied on target voltage calculation.
|
| 725 | * This is available for Sienna Cichlid, Navy Flounder, Dimgrey
|
| 726 | * Cavefish and some later SMU13 ASICs. For these ASICs, the target
|
| 727 | * voltage calculation can be illustrated by "voltage = voltage
|
| 728 | * calculated from v/f curve + overdrive vddgfx offset"
|
| 729 | *
|
| 730 | * - a list of valid ranges for sclk, mclk, voltage curve points
|
| 731 | * or voltage offset labeled OD_RANGE
|
| 732 | *
|
| 733 | * < For APUs >
|
| 734 | *
|
| 735 | * Reading the file will display:
|
| 736 | *
|
| 737 | * - minimum and maximum engine clock labeled OD_SCLK
|
| 738 | *
|
| 739 | * - a list of valid ranges for sclk labeled OD_RANGE
|
| 740 | *
|
| 741 | * < For VanGogh >
|
| 742 | *
|
| 743 | * Reading the file will display:
|
| 744 | *
|
| 745 | * - minimum and maximum engine clock labeled OD_SCLK
|
| 746 | * - minimum and maximum core clocks labeled OD_CCLK
|
| 747 | *
|
| 748 | * - a list of valid ranges for sclk and cclk labeled OD_RANGE
|
| 749 | *
|
| 750 | * To manually adjust these settings:
|
| 751 | *
|
| 752 | * - First select manual using power_dpm_force_performance_level
|
| 753 | *
|
| 754 | * - For clock frequency setting, enter a new value by writing a
|
| 755 | * string that contains "s/m/f index clock" to the file. The index
|
| 756 | * should be 0 if to set minimum clock. And 1 if to set maximum
|
| 757 | * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
|
| 758 | * "m 1 800" will update maximum mclk to be 800Mhz. "f 1 1600" will
|
| 759 | * update maximum fabric clock to be 1600Mhz. For core
|
| 760 | * clocks on VanGogh, the string contains "p core index clock".
|
| 761 | * E.g., "p 2 0 800" would set the minimum core clock on core
|
| 762 | * 2 to 800Mhz.
|
| 763 | *
|
| 764 | * For sclk voltage curve supported by Vega20 and NV1X, enter the new
|
| 765 | * values by writing a string that contains "vc point clock voltage"
|
| 766 | * to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300
|
| 767 | * 600" will update point1 with clock set as 300Mhz and voltage as 600mV.
|
| 768 | * "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and
|
| 769 | * voltage 1000mV.
|
| 770 | *
|
| 771 | * For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey
|
| 772 | * Cavefish and some later SMU13 ASICs, enter the new value by writing a
|
| 773 | * string that contains "vo offset". E.g., "vo -10" will update the extra
|
| 774 | * voltage offset applied to the whole v/f curve line as -10mv.
|
| 775 | *
|
| 776 | * - When you have edited all of the states as needed, write "c" (commit)
|
| 777 | * to the file to commit your changes
|
| 778 | *
|
| 779 | * - If you want to reset to the default power levels, write "r" (reset)
|
| 780 | * to the file to reset them
|
| 781 | *
|
| 782 |
|
| 783 |
|
| 784 | static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
|
| 785 | struct device_attribute *attr,
|
| 786 | const char *buf,
|
| 787 | size_t count)
|
| 788 | {
|
| 789 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 790 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 791 | int ret;
|
| 792 | uint32_t parameter_size = 0;
|
| 793 | long parameter[64];
|
| 794 | char buf_cpy[128];
|
| 795 | char *tmp_str;
|
| 796 | uint32_t type;
|
| 797 |
|
| 798 | if (count > 127 || count == 0)
|
| 799 | return -EINVAL;
|
| 800 |
|
| 801 | if (*buf == 's')
|
| 802 | type = PP_OD_EDIT_SCLK_VDDC_TABLE;
|
| 803 | else if (*buf == 'p')
|
| 804 | type = PP_OD_EDIT_CCLK_VDDC_TABLE;
|
| 805 | else if (*buf == 'm')
|
| 806 | type = PP_OD_EDIT_MCLK_VDDC_TABLE;
|
| 807 | else if (*buf == 'f')
|
| 808 | type = PP_OD_EDIT_FCLK_TABLE;
|
| 809 | else if (*buf == 'r')
|
| 810 | type = PP_OD_RESTORE_DEFAULT_TABLE;
|
| 811 | else if (*buf == 'c')
|
| 812 | type = PP_OD_COMMIT_DPM_TABLE;
|
| 813 | else if (!strncmp(buf, "vc", 2))
|
| 814 | type = PP_OD_EDIT_VDDC_CURVE;
|
| 815 | else if (!strncmp(buf, "vo", 2))
|
| 816 | type = PP_OD_EDIT_VDDGFX_OFFSET;
|
| 817 | else
|
| 818 | return -EINVAL;
|
| 819 |
|
| 820 | memcpy(buf_cpy, buf, count);
|
| 821 | buf_cpy[count] = 0;
|
| 822 |
|
| 823 | tmp_str = buf_cpy;
|
| 824 |
|
| 825 | if ((type == PP_OD_EDIT_VDDC_CURVE) ||
|
| 826 | (type == PP_OD_EDIT_VDDGFX_OFFSET))
|
| 827 | tmp_str++;
|
| 828 | while (isspace(*++tmp_str));
|
| 829 |
|
| 830 | ret = amdgpu_pm_parse_long_params(
|
| 831 | tmp_str, parameter, ARRAY_SIZE(parameter), ¶meter_size);
|
| 832 | if (ret)
|
| 833 | return ret;
|
| 834 |
|
| 835 | ret = amdgpu_pm_get_access(adev);
|
| 836 | if (ret < 0)
|
| 837 | return ret;
|
| 838 |
|
| 839 | if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
|
| 840 | type,
|
| 841 | parameter,
|
| 842 | parameter_size))
|
| 843 | goto err_out;
|
| 844 |
|
| 845 | if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
|
| 846 | parameter, parameter_size))
|
| 847 | goto err_out;
|
| 848 |
|
| 849 | if (type == PP_OD_COMMIT_DPM_TABLE) {
|
| 850 | if (amdgpu_dpm_dispatch_task(adev,
|
| 851 | AMD_PP_TASK_READJUST_POWER_STATE,
|
| 852 | NULL))
|
| 853 | goto err_out;
|
| 854 | }
|
| 855 |
|
| 856 | amdgpu_pm_put_access(adev);
|
| 857 |
|
| 858 | return count;
|
| 859 |
|
| 860 | err_out:
|
| 861 | amdgpu_pm_put_access(adev);
|
| 862 |
|
| 863 | return -EINVAL;
|
| 864 | }
|
| 865 |
|
| 866 | static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
|
| 867 | struct device_attribute *attr,
|
| 868 | char *buf)
|
| 869 | {
|
| 870 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 871 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 872 | int size = 0;
|
| 873 | int ret;
|
| 874 | enum pp_clock_type od_clocks[] = {
|
| 875 | OD_SCLK,
|
| 876 | OD_MCLK,
|
| 877 | OD_FCLK,
|
| 878 | OD_VDDC_CURVE,
|
| 879 | OD_RANGE,
|
| 880 | OD_VDDGFX_OFFSET,
|
| 881 | OD_CCLK,
|
| 882 | };
|
| 883 | uint clk_index;
|
| 884 |
|
| 885 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 886 | if (ret)
|
| 887 | return ret;
|
| 888 |
|
| 889 | for (clk_index = 0 ; clk_index < ARRAY_SIZE(od_clocks) ; clk_index++) {
|
| 890 | amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
|
| 891 | if (unlikely(size >= (PAGE_SIZE - 1)))
|
| 892 | break;
|
| 893 | }
|
| 894 |
|
| 895 | if (size == 0)
|
| 896 | size = sysfs_emit(buf, "\n");
|
| 897 |
|
| 898 | amdgpu_pm_put_access(adev);
|
| 899 |
|
| 900 | return size;
|
| 901 | }
|
| 902 |
|
| 903 | |
| 904 | * DOC: pp_features
|
| 905 | *
|
| 906 | * The amdgpu driver provides a sysfs API for adjusting what powerplay
|
| 907 | * features to be enabled. The file pp_features is used for this. And
|
| 908 | * this is only available for Vega10 and later dGPUs.
|
| 909 | *
|
| 910 | * Reading back the file will show you the followings:
|
| 911 | * - Current ppfeature masks
|
| 912 | * - List of the all supported powerplay features with their naming,
|
| 913 | * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
|
| 914 | *
|
| 915 | * To manually enable or disable a specific feature, just set or clear
|
| 916 | * the corresponding bit from original ppfeature masks and input the
|
| 917 | * new ppfeature masks.
|
| 918 |
|
| 919 | static ssize_t amdgpu_set_pp_features(struct device *dev,
|
| 920 | struct device_attribute *attr,
|
| 921 | const char *buf,
|
| 922 | size_t count)
|
| 923 | {
|
| 924 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 925 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 926 | uint64_t featuremask;
|
| 927 | int ret;
|
| 928 |
|
| 929 |
|
| 930 | if (count == 0 || sysfs_streq(buf, ""))
|
| 931 | return -EINVAL;
|
| 932 |
|
| 933 | ret = kstrtou64(buf, 0, &featuremask);
|
| 934 | if (ret)
|
| 935 | return -EINVAL;
|
| 936 |
|
| 937 | ret = amdgpu_pm_get_access(adev);
|
| 938 | if (ret < 0)
|
| 939 | return ret;
|
| 940 |
|
| 941 | ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
|
| 942 |
|
| 943 | amdgpu_pm_put_access(adev);
|
| 944 |
|
| 945 | if (ret)
|
| 946 | return -EINVAL;
|
| 947 |
|
| 948 | return count;
|
| 949 | }
|
| 950 |
|
| 951 | static ssize_t amdgpu_get_pp_features(struct device *dev,
|
| 952 | struct device_attribute *attr,
|
| 953 | char *buf)
|
| 954 | {
|
| 955 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 956 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 957 | ssize_t size;
|
| 958 | int ret;
|
| 959 |
|
| 960 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 961 | if (ret)
|
| 962 | return ret;
|
| 963 |
|
| 964 | size = amdgpu_dpm_get_ppfeature_status(adev, buf);
|
| 965 | if (size <= 0)
|
| 966 | size = sysfs_emit(buf, "\n");
|
| 967 |
|
| 968 | amdgpu_pm_put_access(adev);
|
| 969 |
|
| 970 | return size;
|
| 971 | }
|
| 972 |
|
| 973 | |
| 974 | * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
|
| 975 | *
|
| 976 | * The amdgpu driver provides a sysfs API for adjusting what power levels
|
| 977 | * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk,
|
| 978 | * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
|
| 979 | * this.
|
| 980 | *
|
| 981 | * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
|
| 982 | * Vega10 and later ASICs.
|
| 983 | * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
|
| 984 | *
|
| 985 | * Reading back the files will show you the available power levels within
|
| 986 | * the power state and the clock information for those levels. If deep sleep is
|
| 987 | * applied to a clock, the level will be denoted by a special level 'S:'
|
| 988 | * E.g., ::
|
| 989 | *
|
| 990 | * S: 19Mhz *
|
| 991 | * 0: 615Mhz
|
| 992 | * 1: 800Mhz
|
| 993 | * 2: 888Mhz
|
| 994 | * 3: 1000Mhz
|
| 995 | *
|
| 996 | *
|
| 997 | * To manually adjust these states, first select manual using
|
| 998 | * power_dpm_force_performance_level.
|
| 999 | * Secondly, enter a new value for each level by inputing a string that
|
| 1000 | * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
|
| 1001 | * E.g.,
|
| 1002 | *
|
| 1003 | * .. code-block:: bash
|
| 1004 | *
|
| 1005 | * echo "4 5 6" > pp_dpm_sclk
|
| 1006 | *
|
| 1007 | * will enable sclk levels 4, 5, and 6.
|
| 1008 | *
|
| 1009 | * NOTE: change to the dcefclk max dpm level is not supported now
|
| 1010 |
|
| 1011 |
|
| 1012 | static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
|
| 1013 | enum pp_clock_type type,
|
| 1014 | char *buf)
|
| 1015 | {
|
| 1016 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1017 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1018 | int size = 0;
|
| 1019 | int ret = 0;
|
| 1020 |
|
| 1021 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 1022 | if (ret)
|
| 1023 | return ret;
|
| 1024 |
|
| 1025 | ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
|
| 1026 | if (ret) {
|
| 1027 | size = ret;
|
| 1028 | goto out_pm_put;
|
| 1029 | }
|
| 1030 |
|
| 1031 | if (size == 0)
|
| 1032 | size = sysfs_emit(buf, "\n");
|
| 1033 |
|
| 1034 | out_pm_put:
|
| 1035 | amdgpu_pm_put_access(adev);
|
| 1036 |
|
| 1037 | return size;
|
| 1038 | }
|
| 1039 |
|
| 1040 | |
| 1041 | * Worst case: 32 bits individually specified, in octal at 12 characters
|
| 1042 | * per line (+1 for \n).
|
| 1043 |
|
| 1044 | #define AMDGPU_MASK_BUF_MAX (32 * 13)
|
| 1045 |
|
| 1046 | static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
|
| 1047 | {
|
| 1048 | int ret;
|
| 1049 | unsigned long level;
|
| 1050 | char *sub_str = NULL;
|
| 1051 | char *tmp;
|
| 1052 | char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
|
| 1053 | const char delimiter[3] = {' ', '\n', '\0'};
|
| 1054 | size_t bytes;
|
| 1055 |
|
| 1056 | *mask = 0;
|
| 1057 |
|
| 1058 |
|
| 1059 | if (count == 0 || sysfs_streq(buf, ""))
|
| 1060 | return -EINVAL;
|
| 1061 |
|
| 1062 | bytes = min(count, sizeof(buf_cpy) - 1);
|
| 1063 | memcpy(buf_cpy, buf, bytes);
|
| 1064 | buf_cpy[bytes] = '\0';
|
| 1065 | tmp = buf_cpy;
|
| 1066 | while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
|
| 1067 | if (strlen(sub_str)) {
|
| 1068 | ret = kstrtoul(sub_str, 0, &level);
|
| 1069 | if (ret || level > 31)
|
| 1070 | return -EINVAL;
|
| 1071 | *mask |= 1 << level;
|
| 1072 | } else
|
| 1073 | break;
|
| 1074 | }
|
| 1075 |
|
| 1076 | return 0;
|
| 1077 | }
|
| 1078 |
|
| 1079 | static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
|
| 1080 | enum pp_clock_type type,
|
| 1081 | const char *buf,
|
| 1082 | size_t count)
|
| 1083 | {
|
| 1084 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1085 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1086 | int ret;
|
| 1087 | uint32_t mask = 0;
|
| 1088 |
|
| 1089 | ret = amdgpu_read_mask(buf, count, &mask);
|
| 1090 | if (ret)
|
| 1091 | return ret;
|
| 1092 |
|
| 1093 | ret = amdgpu_pm_get_access(adev);
|
| 1094 | if (ret < 0)
|
| 1095 | return ret;
|
| 1096 |
|
| 1097 | ret = amdgpu_dpm_force_clock_level(adev, type, mask);
|
| 1098 |
|
| 1099 | amdgpu_pm_put_access(adev);
|
| 1100 |
|
| 1101 | if (ret)
|
| 1102 | return -EINVAL;
|
| 1103 |
|
| 1104 | return count;
|
| 1105 | }
|
| 1106 |
|
| 1107 | static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
|
| 1108 | struct device_attribute *attr,
|
| 1109 | char *buf)
|
| 1110 | {
|
| 1111 | return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
|
| 1112 | }
|
| 1113 |
|
| 1114 | static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
|
| 1115 | struct device_attribute *attr,
|
| 1116 | const char *buf,
|
| 1117 | size_t count)
|
| 1118 | {
|
| 1119 | return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
|
| 1120 | }
|
| 1121 |
|
| 1122 | static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
|
| 1123 | struct device_attribute *attr,
|
| 1124 | char *buf)
|
| 1125 | {
|
| 1126 | return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
|
| 1127 | }
|
| 1128 |
|
| 1129 | static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
|
| 1130 | struct device_attribute *attr,
|
| 1131 | const char *buf,
|
| 1132 | size_t count)
|
| 1133 | {
|
| 1134 | return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
|
| 1135 | }
|
| 1136 |
|
| 1137 | static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
|
| 1138 | struct device_attribute *attr,
|
| 1139 | char *buf)
|
| 1140 | {
|
| 1141 | return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
|
| 1142 | }
|
| 1143 |
|
| 1144 | static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
|
| 1145 | struct device_attribute *attr,
|
| 1146 | const char *buf,
|
| 1147 | size_t count)
|
| 1148 | {
|
| 1149 | return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
|
| 1150 | }
|
| 1151 |
|
| 1152 | static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
|
| 1153 | struct device_attribute *attr,
|
| 1154 | char *buf)
|
| 1155 | {
|
| 1156 | return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
|
| 1157 | }
|
| 1158 |
|
| 1159 | static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
|
| 1160 | struct device_attribute *attr,
|
| 1161 | const char *buf,
|
| 1162 | size_t count)
|
| 1163 | {
|
| 1164 | return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
|
| 1165 | }
|
| 1166 |
|
| 1167 | static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
|
| 1168 | struct device_attribute *attr,
|
| 1169 | char *buf)
|
| 1170 | {
|
| 1171 | return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
|
| 1172 | }
|
| 1173 |
|
| 1174 | static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
|
| 1175 | struct device_attribute *attr,
|
| 1176 | const char *buf,
|
| 1177 | size_t count)
|
| 1178 | {
|
| 1179 | return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
|
| 1180 | }
|
| 1181 |
|
| 1182 | static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
|
| 1183 | struct device_attribute *attr,
|
| 1184 | char *buf)
|
| 1185 | {
|
| 1186 | return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
|
| 1187 | }
|
| 1188 |
|
| 1189 | static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
|
| 1190 | struct device_attribute *attr,
|
| 1191 | const char *buf,
|
| 1192 | size_t count)
|
| 1193 | {
|
| 1194 | return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
|
| 1195 | }
|
| 1196 |
|
| 1197 | static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
|
| 1198 | struct device_attribute *attr,
|
| 1199 | char *buf)
|
| 1200 | {
|
| 1201 | return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
|
| 1202 | }
|
| 1203 |
|
| 1204 | static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
|
| 1205 | struct device_attribute *attr,
|
| 1206 | const char *buf,
|
| 1207 | size_t count)
|
| 1208 | {
|
| 1209 | return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
|
| 1210 | }
|
| 1211 |
|
| 1212 | static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
|
| 1213 | struct device_attribute *attr,
|
| 1214 | char *buf)
|
| 1215 | {
|
| 1216 | return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
|
| 1217 | }
|
| 1218 |
|
| 1219 | static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
|
| 1220 | struct device_attribute *attr,
|
| 1221 | const char *buf,
|
| 1222 | size_t count)
|
| 1223 | {
|
| 1224 | return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
|
| 1225 | }
|
| 1226 |
|
| 1227 | static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
|
| 1228 | struct device_attribute *attr,
|
| 1229 | char *buf)
|
| 1230 | {
|
| 1231 | return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
|
| 1232 | }
|
| 1233 |
|
| 1234 | static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
|
| 1235 | struct device_attribute *attr,
|
| 1236 | const char *buf,
|
| 1237 | size_t count)
|
| 1238 | {
|
| 1239 | return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
|
| 1240 | }
|
| 1241 |
|
| 1242 | static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
|
| 1243 | struct device_attribute *attr,
|
| 1244 | char *buf)
|
| 1245 | {
|
| 1246 | return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
|
| 1247 | }
|
| 1248 |
|
| 1249 | static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
|
| 1250 | struct device_attribute *attr,
|
| 1251 | const char *buf,
|
| 1252 | size_t count)
|
| 1253 | {
|
| 1254 | return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
|
| 1255 | }
|
| 1256 |
|
| 1257 | static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
|
| 1258 | struct device_attribute *attr,
|
| 1259 | char *buf)
|
| 1260 | {
|
| 1261 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1262 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1263 | uint32_t value = 0;
|
| 1264 | int ret;
|
| 1265 |
|
| 1266 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 1267 | if (ret)
|
| 1268 | return ret;
|
| 1269 |
|
| 1270 | value = amdgpu_dpm_get_sclk_od(adev);
|
| 1271 |
|
| 1272 | amdgpu_pm_put_access(adev);
|
| 1273 |
|
| 1274 | return sysfs_emit(buf, "%d\n", value);
|
| 1275 | }
|
| 1276 |
|
| 1277 | static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
|
| 1278 | struct device_attribute *attr,
|
| 1279 | const char *buf,
|
| 1280 | size_t count)
|
| 1281 | {
|
| 1282 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1283 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1284 | int ret;
|
| 1285 | long int value;
|
| 1286 |
|
| 1287 | ret = kstrtol(buf, 0, &value);
|
| 1288 |
|
| 1289 | if (ret)
|
| 1290 | return -EINVAL;
|
| 1291 |
|
| 1292 | ret = amdgpu_pm_get_access(adev);
|
| 1293 | if (ret < 0)
|
| 1294 | return ret;
|
| 1295 |
|
| 1296 | amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
|
| 1297 |
|
| 1298 | amdgpu_pm_put_access(adev);
|
| 1299 |
|
| 1300 | return count;
|
| 1301 | }
|
| 1302 |
|
| 1303 | static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
|
| 1304 | struct device_attribute *attr,
|
| 1305 | char *buf)
|
| 1306 | {
|
| 1307 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1308 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1309 | uint32_t value = 0;
|
| 1310 | int ret;
|
| 1311 |
|
| 1312 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 1313 | if (ret)
|
| 1314 | return ret;
|
| 1315 |
|
| 1316 | value = amdgpu_dpm_get_mclk_od(adev);
|
| 1317 |
|
| 1318 | amdgpu_pm_put_access(adev);
|
| 1319 |
|
| 1320 | return sysfs_emit(buf, "%d\n", value);
|
| 1321 | }
|
| 1322 |
|
| 1323 | static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
|
| 1324 | struct device_attribute *attr,
|
| 1325 | const char *buf,
|
| 1326 | size_t count)
|
| 1327 | {
|
| 1328 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1329 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1330 | int ret;
|
| 1331 | long int value;
|
| 1332 |
|
| 1333 | ret = kstrtol(buf, 0, &value);
|
| 1334 |
|
| 1335 | if (ret)
|
| 1336 | return -EINVAL;
|
| 1337 |
|
| 1338 | ret = amdgpu_pm_get_access(adev);
|
| 1339 | if (ret < 0)
|
| 1340 | return ret;
|
| 1341 |
|
| 1342 | amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
|
| 1343 |
|
| 1344 | amdgpu_pm_put_access(adev);
|
| 1345 |
|
| 1346 | return count;
|
| 1347 | }
|
| 1348 |
|
| 1349 | |
| 1350 | * DOC: pp_power_profile_mode
|
| 1351 | *
|
| 1352 | * The amdgpu driver provides a sysfs API for adjusting the heuristics
|
| 1353 | * related to switching between power levels in a power state. The file
|
| 1354 | * pp_power_profile_mode is used for this.
|
| 1355 | *
|
| 1356 | * Reading this file outputs a list of all of the predefined power profiles
|
| 1357 | * and the relevant heuristics settings for that profile.
|
| 1358 | *
|
| 1359 | * To select a profile or create a custom profile, first select manual using
|
| 1360 | * power_dpm_force_performance_level. Writing the number of a predefined
|
| 1361 | * profile to pp_power_profile_mode will enable those heuristics. To
|
| 1362 | * create a custom set of heuristics, write a string of numbers to the file
|
| 1363 | * starting with the number of the custom profile along with a setting
|
| 1364 | * for each heuristic parameter. Due to differences across asic families
|
| 1365 | * the heuristic parameters vary from family to family. Additionally,
|
| 1366 | * you can apply the custom heuristics to different clock domains. Each
|
| 1367 | * clock domain is considered a distinct operation so if you modify the
|
| 1368 | * gfxclk heuristics and then the memclk heuristics, the all of the
|
| 1369 | * custom heuristics will be retained until you switch to another profile.
|
| 1370 | *
|
| 1371 |
|
| 1372 |
|
| 1373 | static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
|
| 1374 | struct device_attribute *attr,
|
| 1375 | char *buf)
|
| 1376 | {
|
| 1377 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1378 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1379 | ssize_t size;
|
| 1380 | int ret;
|
| 1381 |
|
| 1382 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 1383 | if (ret)
|
| 1384 | return ret;
|
| 1385 |
|
| 1386 | size = amdgpu_dpm_get_power_profile_mode(adev, buf);
|
| 1387 | if (size <= 0)
|
| 1388 | size = sysfs_emit(buf, "\n");
|
| 1389 |
|
| 1390 | amdgpu_pm_put_access(adev);
|
| 1391 |
|
| 1392 | return size;
|
| 1393 | }
|
| 1394 |
|
| 1395 |
|
| 1396 | static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
|
| 1397 | struct device_attribute *attr,
|
| 1398 | const char *buf,
|
| 1399 | size_t count)
|
| 1400 | {
|
| 1401 | int ret;
|
| 1402 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1403 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1404 | uint32_t parameter_size = 0;
|
| 1405 | long parameter[64];
|
| 1406 | char buf_cpy[128];
|
| 1407 | char tmp[2];
|
| 1408 | long int profile_mode = 0;
|
| 1409 |
|
| 1410 |
|
| 1411 | if (count == 0 || sysfs_streq(buf, ""))
|
| 1412 | return -EINVAL;
|
| 1413 |
|
| 1414 | tmp[0] = *(buf++);
|
| 1415 | tmp[1] = '\0';
|
| 1416 | ret = kstrtol(tmp, 0, &profile_mode);
|
| 1417 | if (ret)
|
| 1418 | return -EINVAL;
|
| 1419 |
|
| 1420 | if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
|
| 1421 | if (count < 2 || count > sizeof(buf_cpy))
|
| 1422 | return -EINVAL;
|
| 1423 | while (isspace(*buf))
|
| 1424 | buf++;
|
| 1425 | strscpy(buf_cpy, buf, sizeof(buf_cpy));
|
| 1426 | ret = amdgpu_pm_parse_long_params(buf_cpy, parameter,
|
| 1427 | ARRAY_SIZE(parameter) - 1,
|
| 1428 | ¶meter_size);
|
| 1429 | if (ret)
|
| 1430 | return ret;
|
| 1431 | }
|
| 1432 | parameter[parameter_size] = profile_mode;
|
| 1433 |
|
| 1434 | ret = amdgpu_pm_get_access(adev);
|
| 1435 | if (ret < 0)
|
| 1436 | return ret;
|
| 1437 |
|
| 1438 | ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
|
| 1439 |
|
| 1440 | amdgpu_pm_put_access(adev);
|
| 1441 |
|
| 1442 | if (!ret)
|
| 1443 | return count;
|
| 1444 |
|
| 1445 | return -EINVAL;
|
| 1446 | }
|
| 1447 |
|
| 1448 | static int amdgpu_pm_get_sensor_generic(struct amdgpu_device *adev,
|
| 1449 | enum amd_pp_sensors sensor,
|
| 1450 | void *query)
|
| 1451 | {
|
| 1452 | int r, size = sizeof(uint32_t);
|
| 1453 |
|
| 1454 | r = amdgpu_pm_get_access_if_active(adev);
|
| 1455 | if (r)
|
| 1456 | return r;
|
| 1457 |
|
| 1458 |
|
| 1459 | r = amdgpu_dpm_read_sensor(adev, sensor, query, &size);
|
| 1460 |
|
| 1461 | amdgpu_pm_put_access(adev);
|
| 1462 |
|
| 1463 | return r;
|
| 1464 | }
|
| 1465 |
|
| 1466 | |
| 1467 | * DOC: gpu_busy_percent
|
| 1468 | *
|
| 1469 | * The amdgpu driver provides a sysfs API for reading how busy the GPU
|
| 1470 | * is as a percentage. The file gpu_busy_percent is used for this.
|
| 1471 | * The SMU firmware computes a percentage of load based on the
|
| 1472 | * aggregate activity level in the IP cores.
|
| 1473 |
|
| 1474 | static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
|
| 1475 | struct device_attribute *attr,
|
| 1476 | char *buf)
|
| 1477 | {
|
| 1478 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1479 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1480 | unsigned int value;
|
| 1481 | int r;
|
| 1482 |
|
| 1483 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value);
|
| 1484 | if (r)
|
| 1485 | return r;
|
| 1486 |
|
| 1487 | return sysfs_emit(buf, "%d\n", value);
|
| 1488 | }
|
| 1489 |
|
| 1490 | |
| 1491 | * DOC: mem_busy_percent
|
| 1492 | *
|
| 1493 | * The amdgpu driver provides a sysfs API for reading how busy the VRAM
|
| 1494 | * is as a percentage. The file mem_busy_percent is used for this.
|
| 1495 | * The SMU firmware computes a percentage of load based on the
|
| 1496 | * aggregate activity level in the IP cores.
|
| 1497 |
|
| 1498 | static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
|
| 1499 | struct device_attribute *attr,
|
| 1500 | char *buf)
|
| 1501 | {
|
| 1502 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1503 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1504 | unsigned int value;
|
| 1505 | int r;
|
| 1506 |
|
| 1507 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value);
|
| 1508 | if (r)
|
| 1509 | return r;
|
| 1510 |
|
| 1511 | return sysfs_emit(buf, "%d\n", value);
|
| 1512 | }
|
| 1513 |
|
| 1514 | |
| 1515 | * DOC: vcn_busy_percent
|
| 1516 | *
|
| 1517 | * The amdgpu driver provides a sysfs API for reading how busy the VCN
|
| 1518 | * is as a percentage. The file vcn_busy_percent is used for this.
|
| 1519 | * The SMU firmware computes a percentage of load based on the
|
| 1520 | * aggregate activity level in the IP cores.
|
| 1521 |
|
| 1522 | static ssize_t amdgpu_get_vcn_busy_percent(struct device *dev,
|
| 1523 | struct device_attribute *attr,
|
| 1524 | char *buf)
|
| 1525 | {
|
| 1526 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1527 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1528 | unsigned int value;
|
| 1529 | int r;
|
| 1530 |
|
| 1531 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VCN_LOAD, &value);
|
| 1532 | if (r)
|
| 1533 | return r;
|
| 1534 |
|
| 1535 | return sysfs_emit(buf, "%d\n", value);
|
| 1536 | }
|
| 1537 |
|
| 1538 | |
| 1539 | * DOC: pcie_bw
|
| 1540 | *
|
| 1541 | * The amdgpu driver provides a sysfs API for estimating how much data
|
| 1542 | * has been received and sent by the GPU in the last second through PCIe.
|
| 1543 | * The file pcie_bw is used for this.
|
| 1544 | * The Perf counters count the number of received and sent messages and return
|
| 1545 | * those values, as well as the maximum payload size of a PCIe packet (mps).
|
| 1546 | * Note that it is not possible to easily and quickly obtain the size of each
|
| 1547 | * packet transmitted, so we output the max payload size (mps) to allow for
|
| 1548 | * quick estimation of the PCIe bandwidth usage
|
| 1549 |
|
| 1550 | static ssize_t amdgpu_get_pcie_bw(struct device *dev,
|
| 1551 | struct device_attribute *attr,
|
| 1552 | char *buf)
|
| 1553 | {
|
| 1554 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1555 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1556 | uint64_t count0 = 0, count1 = 0;
|
| 1557 | int ret;
|
| 1558 |
|
| 1559 | if (adev->flags & AMD_IS_APU)
|
| 1560 | return -ENODATA;
|
| 1561 |
|
| 1562 | if (!adev->asic_funcs->get_pcie_usage)
|
| 1563 | return -ENODATA;
|
| 1564 |
|
| 1565 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 1566 | if (ret)
|
| 1567 | return ret;
|
| 1568 |
|
| 1569 | amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
|
| 1570 |
|
| 1571 | amdgpu_pm_put_access(adev);
|
| 1572 |
|
| 1573 | return sysfs_emit(buf, "%llu %llu %i\n",
|
| 1574 | count0, count1, pcie_get_mps(adev->pdev));
|
| 1575 | }
|
| 1576 |
|
| 1577 | |
| 1578 | * DOC: unique_id
|
| 1579 | *
|
| 1580 | * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
|
| 1581 | * The file unique_id is used for this.
|
| 1582 | * This will provide a Unique ID that will persist from machine to machine
|
| 1583 | *
|
| 1584 | * NOTE: This will only work for GFX9 and newer. This file will be absent
|
| 1585 | * on unsupported ASICs (GFX8 and older)
|
| 1586 |
|
| 1587 | static ssize_t amdgpu_get_unique_id(struct device *dev,
|
| 1588 | struct device_attribute *attr,
|
| 1589 | char *buf)
|
| 1590 | {
|
| 1591 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1592 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1593 |
|
| 1594 | if (adev->unique_id)
|
| 1595 | return sysfs_emit(buf, "%016llx\n", adev->unique_id);
|
| 1596 |
|
| 1597 | return 0;
|
| 1598 | }
|
| 1599 |
|
| 1600 | |
| 1601 | * DOC: thermal_throttling_logging
|
| 1602 | *
|
| 1603 | * Thermal throttling pulls down the clock frequency and thus the performance.
|
| 1604 | * It's an useful mechanism to protect the chip from overheating. Since it
|
| 1605 | * impacts performance, the user controls whether it is enabled and if so,
|
| 1606 | * the log frequency.
|
| 1607 | *
|
| 1608 | * Reading back the file shows you the status(enabled or disabled) and
|
| 1609 | * the interval(in seconds) between each thermal logging.
|
| 1610 | *
|
| 1611 | * Writing an integer to the file, sets a new logging interval, in seconds.
|
| 1612 | * The value should be between 1 and 3600. If the value is less than 1,
|
| 1613 | * thermal logging is disabled. Values greater than 3600 are ignored.
|
| 1614 |
|
| 1615 | static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
|
| 1616 | struct device_attribute *attr,
|
| 1617 | char *buf)
|
| 1618 | {
|
| 1619 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1620 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1621 |
|
| 1622 | return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
|
| 1623 | adev_to_drm(adev)->unique,
|
| 1624 | str_enabled_disabled(atomic_read(&adev->throttling_logging_enabled)),
|
| 1625 | adev->throttling_logging_rs.interval / HZ + 1);
|
| 1626 | }
|
| 1627 |
|
| 1628 | static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
|
| 1629 | struct device_attribute *attr,
|
| 1630 | const char *buf,
|
| 1631 | size_t count)
|
| 1632 | {
|
| 1633 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1634 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1635 | long throttling_logging_interval;
|
| 1636 | int ret = 0;
|
| 1637 |
|
| 1638 | ret = kstrtol(buf, 0, &throttling_logging_interval);
|
| 1639 | if (ret)
|
| 1640 | return ret;
|
| 1641 |
|
| 1642 |
|
| 1643 | if (throttling_logging_interval < 0)
|
| 1644 | return -EINVAL;
|
| 1645 |
|
| 1646 | if (throttling_logging_interval > 3600)
|
| 1647 | return -EINVAL;
|
| 1648 |
|
| 1649 | if (throttling_logging_interval > 0) {
|
| 1650 | |
| 1651 | * Reset the ratelimit timer internals.
|
| 1652 | * This can effectively restart the timer.
|
| 1653 |
|
| 1654 | ratelimit_state_reset_interval(&adev->throttling_logging_rs,
|
| 1655 | (throttling_logging_interval - 1) * HZ);
|
| 1656 | atomic_set(&adev->throttling_logging_enabled, 1);
|
| 1657 | } else {
|
| 1658 | atomic_set(&adev->throttling_logging_enabled, 0);
|
| 1659 | }
|
| 1660 |
|
| 1661 | return count;
|
| 1662 | }
|
| 1663 |
|
| 1664 | |
| 1665 | * DOC: apu_thermal_cap
|
| 1666 | *
|
| 1667 | * The amdgpu driver provides a sysfs API for retrieving/updating thermal
|
| 1668 | * limit temperature in millidegrees Celsius
|
| 1669 | *
|
| 1670 | * Reading back the file shows you core limit value
|
| 1671 | *
|
| 1672 | * Writing an integer to the file, sets a new thermal limit. The value
|
| 1673 | * should be between 0 and 100. If the value is less than 0 or greater
|
| 1674 | * than 100, then the write request will be ignored.
|
| 1675 |
|
| 1676 | static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
|
| 1677 | struct device_attribute *attr,
|
| 1678 | char *buf)
|
| 1679 | {
|
| 1680 | int ret, size;
|
| 1681 | u32 limit;
|
| 1682 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1683 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1684 |
|
| 1685 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 1686 | if (ret)
|
| 1687 | return ret;
|
| 1688 |
|
| 1689 | ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
|
| 1690 | if (!ret)
|
| 1691 | size = sysfs_emit(buf, "%u\n", limit);
|
| 1692 | else
|
| 1693 | size = sysfs_emit(buf, "failed to get thermal limit\n");
|
| 1694 |
|
| 1695 | amdgpu_pm_put_access(adev);
|
| 1696 |
|
| 1697 | return size;
|
| 1698 | }
|
| 1699 |
|
| 1700 | static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
|
| 1701 | struct device_attribute *attr,
|
| 1702 | const char *buf,
|
| 1703 | size_t count)
|
| 1704 | {
|
| 1705 | int ret;
|
| 1706 | u32 value;
|
| 1707 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1708 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1709 |
|
| 1710 | ret = kstrtou32(buf, 10, &value);
|
| 1711 | if (ret)
|
| 1712 | return ret;
|
| 1713 |
|
| 1714 | if (value > 100) {
|
| 1715 | dev_err(dev, "Invalid argument !\n");
|
| 1716 | return -EINVAL;
|
| 1717 | }
|
| 1718 |
|
| 1719 | ret = amdgpu_pm_get_access(adev);
|
| 1720 | if (ret < 0)
|
| 1721 | return ret;
|
| 1722 |
|
| 1723 | ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
|
| 1724 | if (ret) {
|
| 1725 | amdgpu_pm_put_access(adev);
|
| 1726 | dev_err(dev, "failed to update thermal limit\n");
|
| 1727 | return ret;
|
| 1728 | }
|
| 1729 |
|
| 1730 | amdgpu_pm_put_access(adev);
|
| 1731 |
|
| 1732 | return count;
|
| 1733 | }
|
| 1734 |
|
| 1735 | static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev,
|
| 1736 | struct amdgpu_device_attr *attr,
|
| 1737 | uint32_t mask,
|
| 1738 | enum amdgpu_device_attr_states *states)
|
| 1739 | {
|
| 1740 | if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP)
|
| 1741 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1742 |
|
| 1743 | return 0;
|
| 1744 | }
|
| 1745 |
|
| 1746 | static ssize_t amdgpu_get_pm_metrics(struct device *dev,
|
| 1747 | struct device_attribute *attr, char *buf)
|
| 1748 | {
|
| 1749 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1750 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1751 | ssize_t size = 0;
|
| 1752 | int ret;
|
| 1753 |
|
| 1754 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 1755 | if (ret)
|
| 1756 | return ret;
|
| 1757 |
|
| 1758 | size = amdgpu_dpm_get_pm_metrics(adev, buf, PAGE_SIZE);
|
| 1759 |
|
| 1760 | amdgpu_pm_put_access(adev);
|
| 1761 |
|
| 1762 | return size;
|
| 1763 | }
|
| 1764 |
|
| 1765 | |
| 1766 | * DOC: gpu_metrics
|
| 1767 | *
|
| 1768 | * The amdgpu driver provides a sysfs API for retrieving current gpu
|
| 1769 | * metrics data. The file gpu_metrics is used for this. Reading the
|
| 1770 | * file will dump all the current gpu metrics data.
|
| 1771 | *
|
| 1772 | * These data include temperature, frequency, engines utilization,
|
| 1773 | * power consume, throttler status, fan speed and cpu core statistics(
|
| 1774 | * available for APU only). That's it will give a snapshot of all sensors
|
| 1775 | * at the same time.
|
| 1776 |
|
| 1777 | static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
|
| 1778 | struct device_attribute *attr,
|
| 1779 | char *buf)
|
| 1780 | {
|
| 1781 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1782 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1783 | ssize_t size = 0;
|
| 1784 | int ret;
|
| 1785 |
|
| 1786 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 1787 | if (ret)
|
| 1788 | return ret;
|
| 1789 |
|
| 1790 | size = amdgpu_dpm_get_gpu_metrics(adev, buf, PAGE_SIZE - 1);
|
| 1791 | if (size <= 0)
|
| 1792 | goto out;
|
| 1793 |
|
| 1794 | out:
|
| 1795 | amdgpu_pm_put_access(adev);
|
| 1796 |
|
| 1797 | return size;
|
| 1798 | }
|
| 1799 |
|
| 1800 | static int amdgpu_show_powershift_percent(struct device *dev,
|
| 1801 | char *buf, enum amd_pp_sensors sensor)
|
| 1802 | {
|
| 1803 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1804 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1805 | uint32_t ss_power;
|
| 1806 | int r = 0, i;
|
| 1807 |
|
| 1808 | r = amdgpu_pm_get_sensor_generic(adev, sensor, (void *)&ss_power);
|
| 1809 | if (r == -EOPNOTSUPP) {
|
| 1810 |
|
| 1811 | adev = NULL;
|
| 1812 | mutex_lock(&mgpu_info.mutex);
|
| 1813 | for (i = 0; i < mgpu_info.num_gpu; i++) {
|
| 1814 | if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
|
| 1815 | adev = mgpu_info.gpu_ins[i].adev;
|
| 1816 | break;
|
| 1817 | }
|
| 1818 | }
|
| 1819 | mutex_unlock(&mgpu_info.mutex);
|
| 1820 | if (adev)
|
| 1821 | r = amdgpu_pm_get_sensor_generic(adev, sensor, (void *)&ss_power);
|
| 1822 | }
|
| 1823 |
|
| 1824 | if (r)
|
| 1825 | return r;
|
| 1826 |
|
| 1827 | return sysfs_emit(buf, "%u%%\n", ss_power);
|
| 1828 | }
|
| 1829 |
|
| 1830 | |
| 1831 | * DOC: smartshift_apu_power
|
| 1832 | *
|
| 1833 | * The amdgpu driver provides a sysfs API for reporting APU power
|
| 1834 | * shift in percentage if platform supports smartshift. Value 0 means that
|
| 1835 | * there is no powershift and values between [1-100] means that the power
|
| 1836 | * is shifted to APU, the percentage of boost is with respect to APU power
|
| 1837 | * limit on the platform.
|
| 1838 |
|
| 1839 |
|
| 1840 | static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
|
| 1841 | char *buf)
|
| 1842 | {
|
| 1843 | return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE);
|
| 1844 | }
|
| 1845 |
|
| 1846 | |
| 1847 | * DOC: smartshift_dgpu_power
|
| 1848 | *
|
| 1849 | * The amdgpu driver provides a sysfs API for reporting dGPU power
|
| 1850 | * shift in percentage if platform supports smartshift. Value 0 means that
|
| 1851 | * there is no powershift and values between [1-100] means that the power is
|
| 1852 | * shifted to dGPU, the percentage of boost is with respect to dGPU power
|
| 1853 | * limit on the platform.
|
| 1854 |
|
| 1855 |
|
| 1856 | static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
|
| 1857 | char *buf)
|
| 1858 | {
|
| 1859 | return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE);
|
| 1860 | }
|
| 1861 |
|
| 1862 | |
| 1863 | * DOC: smartshift_bias
|
| 1864 | *
|
| 1865 | * The amdgpu driver provides a sysfs API for reporting the
|
| 1866 | * smartshift(SS2.0) bias level. The value ranges from -100 to 100
|
| 1867 | * and the default is 0. -100 sets maximum preference to APU
|
| 1868 | * and 100 sets max perference to dGPU.
|
| 1869 |
|
| 1870 |
|
| 1871 | static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
|
| 1872 | struct device_attribute *attr,
|
| 1873 | char *buf)
|
| 1874 | {
|
| 1875 | int r = 0;
|
| 1876 |
|
| 1877 | r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
|
| 1878 |
|
| 1879 | return r;
|
| 1880 | }
|
| 1881 |
|
| 1882 | static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
|
| 1883 | struct device_attribute *attr,
|
| 1884 | const char *buf, size_t count)
|
| 1885 | {
|
| 1886 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 1887 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 1888 | int r;
|
| 1889 | int bias = 0;
|
| 1890 |
|
| 1891 | r = kstrtoint(buf, 10, &bias);
|
| 1892 | if (r)
|
| 1893 | return r;
|
| 1894 |
|
| 1895 | r = amdgpu_pm_get_access(adev);
|
| 1896 | if (r < 0)
|
| 1897 | return r;
|
| 1898 |
|
| 1899 | if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
|
| 1900 | bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
|
| 1901 | else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
|
| 1902 | bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
|
| 1903 |
|
| 1904 | amdgpu_smartshift_bias = bias;
|
| 1905 |
|
| 1906 |
|
| 1907 |
|
| 1908 | amdgpu_pm_put_access(adev);
|
| 1909 |
|
| 1910 | return count;
|
| 1911 | }
|
| 1912 |
|
| 1913 | static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
|
| 1914 | uint32_t mask, enum amdgpu_device_attr_states *states)
|
| 1915 | {
|
| 1916 | if (!amdgpu_device_supports_smart_shift(adev))
|
| 1917 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1918 |
|
| 1919 | return 0;
|
| 1920 | }
|
| 1921 |
|
| 1922 | static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
|
| 1923 | uint32_t mask, enum amdgpu_device_attr_states *states)
|
| 1924 | {
|
| 1925 | uint32_t ss_power;
|
| 1926 |
|
| 1927 | if (!amdgpu_device_supports_smart_shift(adev))
|
| 1928 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1929 | else if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
|
| 1930 | (void *)&ss_power))
|
| 1931 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1932 | else if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
|
| 1933 | (void *)&ss_power))
|
| 1934 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1935 |
|
| 1936 | return 0;
|
| 1937 | }
|
| 1938 |
|
| 1939 | static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
|
| 1940 | uint32_t mask, enum amdgpu_device_attr_states *states)
|
| 1941 | {
|
| 1942 | *states = ATTR_STATE_SUPPORTED;
|
| 1943 |
|
| 1944 | if (!amdgpu_dpm_is_overdrive_supported(adev)) {
|
| 1945 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1946 | return 0;
|
| 1947 | }
|
| 1948 |
|
| 1949 |
|
| 1950 | if (amdgpu_is_multi_aid(adev)) {
|
| 1951 | if (amdgpu_sriov_multi_vf_mode(adev))
|
| 1952 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1953 | return 0;
|
| 1954 | }
|
| 1955 |
|
| 1956 | if (!(attr->flags & mask))
|
| 1957 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1958 |
|
| 1959 | return 0;
|
| 1960 | }
|
| 1961 |
|
| 1962 | static int pp_dpm_dcefclk_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
|
| 1963 | uint32_t mask, enum amdgpu_device_attr_states *states)
|
| 1964 | {
|
| 1965 | struct device_attribute *dev_attr = &attr->dev_attr;
|
| 1966 | uint32_t gc_ver;
|
| 1967 |
|
| 1968 | *states = ATTR_STATE_SUPPORTED;
|
| 1969 |
|
| 1970 | if (!(attr->flags & mask)) {
|
| 1971 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1972 | return 0;
|
| 1973 | }
|
| 1974 |
|
| 1975 | gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
|
| 1976 |
|
| 1977 | if ((gc_ver == IP_VERSION(11, 0, 3) && amdgpu_sriov_is_pp_one_vf(adev)) ||
|
| 1978 | gc_ver < IP_VERSION(9, 0, 0) ||
|
| 1979 | !amdgpu_device_has_display_hardware(adev))
|
| 1980 | *states = ATTR_STATE_UNSUPPORTED;
|
| 1981 |
|
| 1982 | |
| 1983 | * setting should not be allowed from VF if not in one VF mode.
|
| 1984 |
|
| 1985 | if (gc_ver >= IP_VERSION(10, 0, 0) ||
|
| 1986 | (amdgpu_sriov_multi_vf_mode(adev))) {
|
| 1987 | dev_attr->attr.mode &= ~S_IWUGO;
|
| 1988 | dev_attr->store = NULL;
|
| 1989 | }
|
| 1990 |
|
| 1991 | return 0;
|
| 1992 | }
|
| 1993 |
|
| 1994 | static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
|
| 1995 | uint32_t mask, enum amdgpu_device_attr_states *states)
|
| 1996 | {
|
| 1997 | struct device_attribute *dev_attr = &attr->dev_attr;
|
| 1998 | enum amdgpu_device_attr_id attr_id = attr->attr_id;
|
| 1999 | uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
|
| 2000 | uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
|
| 2001 |
|
| 2002 | *states = ATTR_STATE_SUPPORTED;
|
| 2003 |
|
| 2004 | if (!(attr->flags & mask)) {
|
| 2005 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2006 | return 0;
|
| 2007 | }
|
| 2008 |
|
| 2009 | if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
|
| 2010 | if (gc_ver < IP_VERSION(9, 0, 0))
|
| 2011 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2012 | } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
|
| 2013 | if (mp1_ver < IP_VERSION(10, 0, 0))
|
| 2014 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2015 | } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
|
| 2016 | if (!(gc_ver == IP_VERSION(10, 3, 1) ||
|
| 2017 | gc_ver == IP_VERSION(10, 3, 3) ||
|
| 2018 | gc_ver == IP_VERSION(10, 3, 6) ||
|
| 2019 | gc_ver == IP_VERSION(10, 3, 7) ||
|
| 2020 | gc_ver == IP_VERSION(10, 3, 0) ||
|
| 2021 | gc_ver == IP_VERSION(10, 1, 2) ||
|
| 2022 | gc_ver == IP_VERSION(11, 0, 0) ||
|
| 2023 | gc_ver == IP_VERSION(11, 0, 1) ||
|
| 2024 | gc_ver == IP_VERSION(11, 0, 4) ||
|
| 2025 | gc_ver == IP_VERSION(11, 5, 0) ||
|
| 2026 | gc_ver == IP_VERSION(11, 5, 1) ||
|
| 2027 | gc_ver == IP_VERSION(11, 0, 2) ||
|
| 2028 | gc_ver == IP_VERSION(11, 0, 3) ||
|
| 2029 | amdgpu_is_multi_aid(adev)))
|
| 2030 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2031 | } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
|
| 2032 | if (!((gc_ver == IP_VERSION(10, 3, 1) ||
|
| 2033 | gc_ver == IP_VERSION(10, 3, 0) ||
|
| 2034 | gc_ver == IP_VERSION(11, 0, 2) ||
|
| 2035 | gc_ver == IP_VERSION(11, 0, 3) ||
|
| 2036 | gc_ver == IP_VERSION(11, 5, 1)) && adev->vcn.num_vcn_inst >= 2))
|
| 2037 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2038 | } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
|
| 2039 | if (!(gc_ver == IP_VERSION(10, 3, 1) ||
|
| 2040 | gc_ver == IP_VERSION(10, 3, 3) ||
|
| 2041 | gc_ver == IP_VERSION(10, 3, 6) ||
|
| 2042 | gc_ver == IP_VERSION(10, 3, 7) ||
|
| 2043 | gc_ver == IP_VERSION(10, 3, 0) ||
|
| 2044 | gc_ver == IP_VERSION(10, 1, 2) ||
|
| 2045 | gc_ver == IP_VERSION(11, 0, 0) ||
|
| 2046 | gc_ver == IP_VERSION(11, 0, 1) ||
|
| 2047 | gc_ver == IP_VERSION(11, 0, 4) ||
|
| 2048 | gc_ver == IP_VERSION(11, 5, 0) ||
|
| 2049 | gc_ver == IP_VERSION(11, 5, 1) ||
|
| 2050 | gc_ver == IP_VERSION(11, 0, 2) ||
|
| 2051 | gc_ver == IP_VERSION(11, 0, 3) ||
|
| 2052 | amdgpu_is_multi_aid(adev)))
|
| 2053 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2054 | } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
|
| 2055 | if (!((gc_ver == IP_VERSION(10, 3, 1) ||
|
| 2056 | gc_ver == IP_VERSION(10, 3, 0) ||
|
| 2057 | gc_ver == IP_VERSION(11, 0, 2) ||
|
| 2058 | gc_ver == IP_VERSION(11, 0, 3) ||
|
| 2059 | gc_ver == IP_VERSION(11, 5, 1)) && adev->vcn.num_vcn_inst >= 2))
|
| 2060 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2061 | } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
|
| 2062 | if (amdgpu_is_multi_aid(adev))
|
| 2063 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2064 | }
|
| 2065 |
|
| 2066 | switch (gc_ver) {
|
| 2067 | case IP_VERSION(9, 4, 1):
|
| 2068 |
|
| 2069 | if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
|
| 2070 | DEVICE_ATTR_IS(pp_dpm_socclk) ||
|
| 2071 | DEVICE_ATTR_IS(pp_dpm_fclk)) {
|
| 2072 | dev_attr->attr.mode &= ~S_IWUGO;
|
| 2073 | dev_attr->store = NULL;
|
| 2074 | }
|
| 2075 | break;
|
| 2076 | case IP_VERSION(9, 4, 2):
|
| 2077 | if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
|
| 2078 | DEVICE_ATTR_IS(pp_dpm_socclk)) {
|
| 2079 | |
| 2080 | * not allow to set dpm level directly
|
| 2081 | dev_attr->attr.mode &= ~S_IWUGO;
|
| 2082 | dev_attr->store = NULL;
|
| 2083 | } else if (DEVICE_ATTR_IS(pp_dpm_fclk) ||
|
| 2084 | DEVICE_ATTR_IS(pp_dpm_pcie)) {
|
| 2085 |
|
| 2086 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2087 | }
|
| 2088 | break;
|
| 2089 | default:
|
| 2090 | break;
|
| 2091 | }
|
| 2092 |
|
| 2093 |
|
| 2094 | if (amdgpu_sriov_vf(adev) && amdgpu_sriov_is_pp_one_vf(adev)) {
|
| 2095 | dev_attr->attr.mode &= ~S_IWUGO;
|
| 2096 | dev_attr->store = NULL;
|
| 2097 | }
|
| 2098 |
|
| 2099 | return 0;
|
| 2100 | }
|
| 2101 |
|
| 2102 | |
| 2103 | * DOC: board
|
| 2104 | *
|
| 2105 | * Certain SOCs can support various board attributes reporting. This is useful
|
| 2106 | * for user application to monitor various board reated attributes.
|
| 2107 | *
|
| 2108 | * The amdgpu driver provides a sysfs API for reporting board attributes. Presently,
|
| 2109 | * nine types of attributes are reported. Baseboard temperature and
|
| 2110 | * gpu board temperature are reported as binary files. Npm status, current node power limit,
|
| 2111 | * max node power limit, node power, global ppt residency, baseboard_power, baseboard_power_limit
|
| 2112 | * is reported as ASCII text file.
|
| 2113 | *
|
| 2114 | * * .. code-block:: console
|
| 2115 | *
|
| 2116 | * hexdump /sys/bus/pci/devices/.../board/baseboard_temp
|
| 2117 | *
|
| 2118 | * hexdump /sys/bus/pci/devices/.../board/gpuboard_temp
|
| 2119 | *
|
| 2120 | * hexdump /sys/bus/pci/devices/.../board/npm_status
|
| 2121 | *
|
| 2122 | * hexdump /sys/bus/pci/devices/.../board/cur_node_power_limit
|
| 2123 | *
|
| 2124 | * hexdump /sys/bus/pci/devices/.../board/max_node_power_limit
|
| 2125 | *
|
| 2126 | * hexdump /sys/bus/pci/devices/.../board/node_power
|
| 2127 | *
|
| 2128 | * hexdump /sys/bus/pci/devices/.../board/global_ppt_resid
|
| 2129 | *
|
| 2130 | * hexdump /sys/bus/pci/devices/.../board/baseboard_power
|
| 2131 | *
|
| 2132 | * hexdump /sys/bus/pci/devices/.../board/baseboard_power_limit
|
| 2133 |
|
| 2134 |
|
| 2135 | |
| 2136 | * DOC: baseboard_temp
|
| 2137 | *
|
| 2138 | * The amdgpu driver provides a sysfs API for retrieving current baseboard
|
| 2139 | * temperature metrics data. The file baseboard_temp is used for this.
|
| 2140 | * Reading the file will dump all the current baseboard temperature metrics data.
|
| 2141 |
|
| 2142 | static ssize_t amdgpu_get_baseboard_temp_metrics(struct device *dev,
|
| 2143 | struct device_attribute *attr, char *buf)
|
| 2144 | {
|
| 2145 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2146 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2147 | ssize_t size;
|
| 2148 | int ret;
|
| 2149 |
|
| 2150 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 2151 | if (ret)
|
| 2152 | return ret;
|
| 2153 |
|
| 2154 | size = amdgpu_dpm_get_temp_metrics(adev, SMU_TEMP_METRIC_BASEBOARD, NULL);
|
| 2155 | if (size <= 0)
|
| 2156 | goto out;
|
| 2157 | if (size >= PAGE_SIZE) {
|
| 2158 | ret = -ENOSPC;
|
| 2159 | goto out;
|
| 2160 | }
|
| 2161 |
|
| 2162 | amdgpu_dpm_get_temp_metrics(adev, SMU_TEMP_METRIC_BASEBOARD, buf);
|
| 2163 |
|
| 2164 | out:
|
| 2165 | amdgpu_pm_put_access(adev);
|
| 2166 |
|
| 2167 | if (ret)
|
| 2168 | return ret;
|
| 2169 |
|
| 2170 | return size;
|
| 2171 | }
|
| 2172 |
|
| 2173 | |
| 2174 | * DOC: gpuboard_temp
|
| 2175 | *
|
| 2176 | * The amdgpu driver provides a sysfs API for retrieving current gpuboard
|
| 2177 | * temperature metrics data. The file gpuboard_temp is used for this.
|
| 2178 | * Reading the file will dump all the current gpuboard temperature metrics data.
|
| 2179 |
|
| 2180 | static ssize_t amdgpu_get_gpuboard_temp_metrics(struct device *dev,
|
| 2181 | struct device_attribute *attr, char *buf)
|
| 2182 | {
|
| 2183 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2184 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2185 | ssize_t size;
|
| 2186 | int ret;
|
| 2187 |
|
| 2188 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 2189 | if (ret)
|
| 2190 | return ret;
|
| 2191 |
|
| 2192 | size = amdgpu_dpm_get_temp_metrics(adev, SMU_TEMP_METRIC_GPUBOARD, NULL);
|
| 2193 | if (size <= 0)
|
| 2194 | goto out;
|
| 2195 | if (size >= PAGE_SIZE) {
|
| 2196 | ret = -ENOSPC;
|
| 2197 | goto out;
|
| 2198 | }
|
| 2199 |
|
| 2200 | amdgpu_dpm_get_temp_metrics(adev, SMU_TEMP_METRIC_GPUBOARD, buf);
|
| 2201 |
|
| 2202 | out:
|
| 2203 | amdgpu_pm_put_access(adev);
|
| 2204 |
|
| 2205 | if (ret)
|
| 2206 | return ret;
|
| 2207 |
|
| 2208 | return size;
|
| 2209 | }
|
| 2210 |
|
| 2211 | |
| 2212 | * DOC: cur_node_power_limit
|
| 2213 | *
|
| 2214 | * The amdgpu driver provides a sysfs API for retrieving current node power limit.
|
| 2215 | * The file cur_node_power_limit is used for this.
|
| 2216 |
|
| 2217 | static ssize_t amdgpu_show_cur_node_power_limit(struct device *dev,
|
| 2218 | struct device_attribute *attr, char *buf)
|
| 2219 | {
|
| 2220 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2221 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2222 | u32 nplimit;
|
| 2223 | int r;
|
| 2224 |
|
| 2225 |
|
| 2226 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_NODEPOWERLIMIT,
|
| 2227 | (void *)&nplimit);
|
| 2228 | if (r)
|
| 2229 | return r;
|
| 2230 |
|
| 2231 | return sysfs_emit(buf, "%u\n", nplimit);
|
| 2232 | }
|
| 2233 |
|
| 2234 | |
| 2235 | * DOC: node_power
|
| 2236 | *
|
| 2237 | * The amdgpu driver provides a sysfs API for retrieving current node power.
|
| 2238 | * The file node_power is used for this.
|
| 2239 |
|
| 2240 | static ssize_t amdgpu_show_node_power(struct device *dev,
|
| 2241 | struct device_attribute *attr, char *buf)
|
| 2242 | {
|
| 2243 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2244 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2245 | u32 npower;
|
| 2246 | int r;
|
| 2247 |
|
| 2248 |
|
| 2249 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_NODEPOWER,
|
| 2250 | (void *)&npower);
|
| 2251 | if (r)
|
| 2252 | return r;
|
| 2253 |
|
| 2254 | return sysfs_emit(buf, "%u\n", npower);
|
| 2255 | }
|
| 2256 |
|
| 2257 | |
| 2258 | * DOC: npm_status
|
| 2259 | *
|
| 2260 | * The amdgpu driver provides a sysfs API for retrieving current node power management status.
|
| 2261 | * The file npm_status is used for this. It shows the status as enabled or disabled based on
|
| 2262 | * current node power value. If node power is zero, status is disabled else enabled.
|
| 2263 |
|
| 2264 | static ssize_t amdgpu_show_npm_status(struct device *dev,
|
| 2265 | struct device_attribute *attr, char *buf)
|
| 2266 | {
|
| 2267 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2268 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2269 | u32 npower;
|
| 2270 | int r;
|
| 2271 |
|
| 2272 |
|
| 2273 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_NODEPOWER,
|
| 2274 | (void *)&npower);
|
| 2275 | if (r)
|
| 2276 | return r;
|
| 2277 |
|
| 2278 | return sysfs_emit(buf, "%s\n", str_enabled_disabled(npower));
|
| 2279 | }
|
| 2280 |
|
| 2281 | |
| 2282 | * DOC: global_ppt_resid
|
| 2283 | *
|
| 2284 | * The amdgpu driver provides a sysfs API for retrieving global ppt residency.
|
| 2285 | * The file global_ppt_resid is used for this.
|
| 2286 |
|
| 2287 | static ssize_t amdgpu_show_global_ppt_resid(struct device *dev,
|
| 2288 | struct device_attribute *attr, char *buf)
|
| 2289 | {
|
| 2290 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2291 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2292 | u32 gpptresid;
|
| 2293 | int r;
|
| 2294 |
|
| 2295 |
|
| 2296 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPPTRESIDENCY,
|
| 2297 | (void *)&gpptresid);
|
| 2298 | if (r)
|
| 2299 | return r;
|
| 2300 |
|
| 2301 | return sysfs_emit(buf, "%u\n", gpptresid);
|
| 2302 | }
|
| 2303 |
|
| 2304 | |
| 2305 | * DOC: max_node_power_limit
|
| 2306 | *
|
| 2307 | * The amdgpu driver provides a sysfs API for retrieving maximum node power limit.
|
| 2308 | * The file max_node_power_limit is used for this.
|
| 2309 |
|
| 2310 | static ssize_t amdgpu_show_max_node_power_limit(struct device *dev,
|
| 2311 | struct device_attribute *attr, char *buf)
|
| 2312 | {
|
| 2313 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2314 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2315 | u32 max_nplimit;
|
| 2316 | int r;
|
| 2317 |
|
| 2318 |
|
| 2319 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT,
|
| 2320 | (void *)&max_nplimit);
|
| 2321 | if (r)
|
| 2322 | return r;
|
| 2323 |
|
| 2324 | return sysfs_emit(buf, "%u\n", max_nplimit);
|
| 2325 | }
|
| 2326 |
|
| 2327 | |
| 2328 | * DOC: baseboard_power
|
| 2329 | *
|
| 2330 | * The amdgpu driver provides a sysfs API for retrieving current ubb power in watts.
|
| 2331 | * The file baseboard_power is used for this.
|
| 2332 |
|
| 2333 | static ssize_t amdgpu_show_baseboard_power(struct device *dev,
|
| 2334 | struct device_attribute *attr, char *buf)
|
| 2335 | {
|
| 2336 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2337 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2338 | u32 ubbpower;
|
| 2339 | int r;
|
| 2340 |
|
| 2341 |
|
| 2342 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_UBB_POWER,
|
| 2343 | (void *)&ubbpower);
|
| 2344 | if (r)
|
| 2345 | return r;
|
| 2346 |
|
| 2347 | return sysfs_emit(buf, "%u\n", ubbpower);
|
| 2348 | }
|
| 2349 |
|
| 2350 | |
| 2351 | * DOC: baseboard_power_limit
|
| 2352 | *
|
| 2353 | * The amdgpu driver provides a sysfs API for retrieving threshold ubb power in watts.
|
| 2354 | * The file baseboard_power_limit is used for this.
|
| 2355 |
|
| 2356 | static ssize_t amdgpu_show_baseboard_power_limit(struct device *dev,
|
| 2357 | struct device_attribute *attr, char *buf)
|
| 2358 | {
|
| 2359 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2360 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2361 | u32 ubbpowerlimit;
|
| 2362 | int r;
|
| 2363 |
|
| 2364 |
|
| 2365 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_UBB_POWER_LIMIT,
|
| 2366 | (void *)&ubbpowerlimit);
|
| 2367 | if (r)
|
| 2368 | return r;
|
| 2369 |
|
| 2370 | return sysfs_emit(buf, "%u\n", ubbpowerlimit);
|
| 2371 | }
|
| 2372 |
|
| 2373 | static DEVICE_ATTR(baseboard_temp, 0444, amdgpu_get_baseboard_temp_metrics, NULL);
|
| 2374 | static DEVICE_ATTR(gpuboard_temp, 0444, amdgpu_get_gpuboard_temp_metrics, NULL);
|
| 2375 | static DEVICE_ATTR(cur_node_power_limit, 0444, amdgpu_show_cur_node_power_limit, NULL);
|
| 2376 | static DEVICE_ATTR(node_power, 0444, amdgpu_show_node_power, NULL);
|
| 2377 | static DEVICE_ATTR(global_ppt_resid, 0444, amdgpu_show_global_ppt_resid, NULL);
|
| 2378 | static DEVICE_ATTR(max_node_power_limit, 0444, amdgpu_show_max_node_power_limit, NULL);
|
| 2379 | static DEVICE_ATTR(npm_status, 0444, amdgpu_show_npm_status, NULL);
|
| 2380 | static DEVICE_ATTR(baseboard_power, 0444, amdgpu_show_baseboard_power, NULL);
|
| 2381 | static DEVICE_ATTR(baseboard_power_limit, 0444, amdgpu_show_baseboard_power_limit, NULL);
|
| 2382 |
|
| 2383 | static struct attribute *board_attrs[] = {
|
| 2384 | &dev_attr_baseboard_temp.attr,
|
| 2385 | &dev_attr_gpuboard_temp.attr,
|
| 2386 | NULL
|
| 2387 | };
|
| 2388 |
|
| 2389 | static umode_t amdgpu_board_attr_visible(struct kobject *kobj, struct attribute *attr, int n)
|
| 2390 | {
|
| 2391 | struct device *dev = kobj_to_dev(kobj);
|
| 2392 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2393 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2394 |
|
| 2395 | if (attr == &dev_attr_baseboard_temp.attr) {
|
| 2396 | if (!amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_BASEBOARD))
|
| 2397 | return 0;
|
| 2398 | }
|
| 2399 |
|
| 2400 | if (attr == &dev_attr_gpuboard_temp.attr) {
|
| 2401 | if (!amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_GPUBOARD))
|
| 2402 | return 0;
|
| 2403 | }
|
| 2404 |
|
| 2405 | return attr->mode;
|
| 2406 | }
|
| 2407 |
|
| 2408 | const struct attribute_group amdgpu_board_attr_group = {
|
| 2409 | .name = "board",
|
| 2410 | .attrs = board_attrs,
|
| 2411 | .is_visible = amdgpu_board_attr_visible,
|
| 2412 | };
|
| 2413 |
|
| 2414 |
|
| 2415 | struct amdgpu_pm_policy_attr {
|
| 2416 | struct device_attribute dev_attr;
|
| 2417 | enum pp_pm_policy id;
|
| 2418 | };
|
| 2419 |
|
| 2420 | |
| 2421 | * DOC: pm_policy
|
| 2422 | *
|
| 2423 | * Certain SOCs can support different power policies to optimize application
|
| 2424 | * performance. However, this policy is provided only at SOC level and not at a
|
| 2425 | * per-process level. This is useful especially when entire SOC is utilized for
|
| 2426 | * dedicated workload.
|
| 2427 | *
|
| 2428 | * The amdgpu driver provides a sysfs API for selecting the policy. Presently,
|
| 2429 | * only two types of policies are supported through this interface.
|
| 2430 | *
|
| 2431 | * Pstate Policy Selection - This is to select different Pstate profiles which
|
| 2432 | * decides clock/throttling preferences.
|
| 2433 | *
|
| 2434 | * XGMI PLPD Policy Selection - When multiple devices are connected over XGMI,
|
| 2435 | * this helps to select policy to be applied for per link power down.
|
| 2436 | *
|
| 2437 | * The list of available policies and policy levels vary between SOCs. They can
|
| 2438 | * be viewed under pm_policy node directory. If SOC doesn't support any policy,
|
| 2439 | * this node won't be available. The different policies supported will be
|
| 2440 | * available as separate nodes under pm_policy.
|
| 2441 | *
|
| 2442 | * cat /sys/bus/pci/devices/.../pm_policy/<policy_type>
|
| 2443 | *
|
| 2444 | * Reading the policy file shows the different levels supported. The level which
|
| 2445 | * is applied presently is denoted by * (asterisk). E.g.,
|
| 2446 | *
|
| 2447 | * .. code-block:: console
|
| 2448 | *
|
| 2449 | * cat /sys/bus/pci/devices/.../pm_policy/soc_pstate
|
| 2450 | * 0 : soc_pstate_default
|
| 2451 | * 1 : soc_pstate_0
|
| 2452 | * 2 : soc_pstate_1*
|
| 2453 | * 3 : soc_pstate_2
|
| 2454 | *
|
| 2455 | * cat /sys/bus/pci/devices/.../pm_policy/xgmi_plpd
|
| 2456 | * 0 : plpd_disallow
|
| 2457 | * 1 : plpd_default
|
| 2458 | * 2 : plpd_optimized*
|
| 2459 | *
|
| 2460 | * To apply a specific policy
|
| 2461 | *
|
| 2462 | * "echo <level> > /sys/bus/pci/devices/.../pm_policy/<policy_type>"
|
| 2463 | *
|
| 2464 | * For the levels listed in the example above, to select "plpd_optimized" for
|
| 2465 | * XGMI and "soc_pstate_2" for soc pstate policy -
|
| 2466 | *
|
| 2467 | * .. code-block:: console
|
| 2468 | *
|
| 2469 | * echo "2" > /sys/bus/pci/devices/.../pm_policy/xgmi_plpd
|
| 2470 | * echo "3" > /sys/bus/pci/devices/.../pm_policy/soc_pstate
|
| 2471 | *
|
| 2472 |
|
| 2473 | static ssize_t amdgpu_get_pm_policy_attr(struct device *dev,
|
| 2474 | struct device_attribute *attr,
|
| 2475 | char *buf)
|
| 2476 | {
|
| 2477 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2478 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2479 | struct amdgpu_pm_policy_attr *policy_attr;
|
| 2480 |
|
| 2481 | policy_attr =
|
| 2482 | container_of(attr, struct amdgpu_pm_policy_attr, dev_attr);
|
| 2483 |
|
| 2484 | return amdgpu_dpm_get_pm_policy_info(adev, policy_attr->id, buf);
|
| 2485 | }
|
| 2486 |
|
| 2487 | static ssize_t amdgpu_set_pm_policy_attr(struct device *dev,
|
| 2488 | struct device_attribute *attr,
|
| 2489 | const char *buf, size_t count)
|
| 2490 | {
|
| 2491 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2492 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2493 | struct amdgpu_pm_policy_attr *policy_attr;
|
| 2494 | int ret, num_params = 0;
|
| 2495 | char delimiter[] = " \n\t";
|
| 2496 | char tmp_buf[128];
|
| 2497 | char *tmp, *param;
|
| 2498 | long val;
|
| 2499 |
|
| 2500 | count = min(count, sizeof(tmp_buf));
|
| 2501 | memcpy(tmp_buf, buf, count);
|
| 2502 | tmp_buf[count - 1] = '\0';
|
| 2503 | tmp = tmp_buf;
|
| 2504 |
|
| 2505 | tmp = skip_spaces(tmp);
|
| 2506 | while ((param = strsep(&tmp, delimiter))) {
|
| 2507 | if (!strlen(param)) {
|
| 2508 | tmp = skip_spaces(tmp);
|
| 2509 | continue;
|
| 2510 | }
|
| 2511 | ret = kstrtol(param, 0, &val);
|
| 2512 | if (ret)
|
| 2513 | return -EINVAL;
|
| 2514 | num_params++;
|
| 2515 | if (num_params > 1)
|
| 2516 | return -EINVAL;
|
| 2517 | }
|
| 2518 |
|
| 2519 | if (num_params != 1)
|
| 2520 | return -EINVAL;
|
| 2521 |
|
| 2522 | policy_attr =
|
| 2523 | container_of(attr, struct amdgpu_pm_policy_attr, dev_attr);
|
| 2524 |
|
| 2525 | ret = amdgpu_pm_get_access(adev);
|
| 2526 | if (ret < 0)
|
| 2527 | return ret;
|
| 2528 |
|
| 2529 | ret = amdgpu_dpm_set_pm_policy(adev, policy_attr->id, val);
|
| 2530 |
|
| 2531 | amdgpu_pm_put_access(adev);
|
| 2532 |
|
| 2533 | if (ret)
|
| 2534 | return ret;
|
| 2535 |
|
| 2536 | return count;
|
| 2537 | }
|
| 2538 |
|
| 2539 | #define AMDGPU_PM_POLICY_ATTR(_name, _id) \
|
| 2540 | static struct amdgpu_pm_policy_attr pm_policy_attr_##_name = { \
|
| 2541 | .dev_attr = __ATTR(_name, 0644, amdgpu_get_pm_policy_attr, \
|
| 2542 | amdgpu_set_pm_policy_attr), \
|
| 2543 | .id = PP_PM_POLICY_##_id, \
|
| 2544 | }
|
| 2545 |
|
| 2546 | #define AMDGPU_PM_POLICY_ATTR_VAR(_name) pm_policy_attr_##_name.dev_attr.attr
|
| 2547 |
|
| 2548 | AMDGPU_PM_POLICY_ATTR(soc_pstate, SOC_PSTATE);
|
| 2549 | AMDGPU_PM_POLICY_ATTR(xgmi_plpd, XGMI_PLPD);
|
| 2550 |
|
| 2551 | static struct attribute *pm_policy_attrs[] = {
|
| 2552 | &AMDGPU_PM_POLICY_ATTR_VAR(soc_pstate),
|
| 2553 | &AMDGPU_PM_POLICY_ATTR_VAR(xgmi_plpd),
|
| 2554 | NULL
|
| 2555 | };
|
| 2556 |
|
| 2557 | static umode_t amdgpu_pm_policy_attr_visible(struct kobject *kobj,
|
| 2558 | struct attribute *attr, int n)
|
| 2559 | {
|
| 2560 | struct device *dev = kobj_to_dev(kobj);
|
| 2561 | struct drm_device *ddev = dev_get_drvdata(dev);
|
| 2562 | struct amdgpu_device *adev = drm_to_adev(ddev);
|
| 2563 | struct amdgpu_pm_policy_attr *policy_attr;
|
| 2564 |
|
| 2565 | policy_attr =
|
| 2566 | container_of(attr, struct amdgpu_pm_policy_attr, dev_attr.attr);
|
| 2567 |
|
| 2568 | if (amdgpu_dpm_get_pm_policy_info(adev, policy_attr->id, NULL) ==
|
| 2569 | -ENOENT)
|
| 2570 | return 0;
|
| 2571 |
|
| 2572 | return attr->mode;
|
| 2573 | }
|
| 2574 |
|
| 2575 | const struct attribute_group amdgpu_pm_policy_attr_group = {
|
| 2576 | .name = "pm_policy",
|
| 2577 | .attrs = pm_policy_attrs,
|
| 2578 | .is_visible = amdgpu_pm_policy_attr_visible,
|
| 2579 | };
|
| 2580 |
|
| 2581 | static struct amdgpu_device_attr amdgpu_device_attrs[] = {
|
| 2582 | AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2583 | AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2584 | AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2585 | AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2586 | AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2587 | AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC),
|
| 2588 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2589 | .attr_update = pp_dpm_clk_default_attr_update),
|
| 2590 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2591 | .attr_update = pp_dpm_clk_default_attr_update),
|
| 2592 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2593 | .attr_update = pp_dpm_clk_default_attr_update),
|
| 2594 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2595 | .attr_update = pp_dpm_clk_default_attr_update),
|
| 2596 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2597 | .attr_update = pp_dpm_clk_default_attr_update),
|
| 2598 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2599 | .attr_update = pp_dpm_clk_default_attr_update),
|
| 2600 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2601 | .attr_update = pp_dpm_clk_default_attr_update),
|
| 2602 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2603 | .attr_update = pp_dpm_clk_default_attr_update),
|
| 2604 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2605 | .attr_update = pp_dpm_dcefclk_attr_update),
|
| 2606 | AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF,
|
| 2607 | .attr_update = pp_dpm_clk_default_attr_update),
|
| 2608 | AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC),
|
| 2609 | AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC),
|
| 2610 | AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2611 | AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC,
|
| 2612 | .attr_update = pp_od_clk_voltage_attr_update),
|
| 2613 | AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2614 | AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2615 | AMDGPU_DEVICE_ATTR_RO(vcn_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2616 | AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC),
|
| 2617 | AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2618 | AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2619 | AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2620 | AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2621 | AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
|
| 2622 | AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC,
|
| 2623 | .attr_update = ss_power_attr_update),
|
| 2624 | AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC,
|
| 2625 | .attr_update = ss_power_attr_update),
|
| 2626 | AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC,
|
| 2627 | .attr_update = ss_bias_attr_update),
|
| 2628 | AMDGPU_DEVICE_ATTR_RO(pm_metrics, ATTR_FLAG_BASIC,
|
| 2629 | .attr_update = amdgpu_pm_metrics_attr_update),
|
| 2630 | };
|
| 2631 |
|
| 2632 | static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
|
| 2633 | uint32_t mask, enum amdgpu_device_attr_states *states)
|
| 2634 | {
|
| 2635 | struct device_attribute *dev_attr = &attr->dev_attr;
|
| 2636 | enum amdgpu_device_attr_id attr_id = attr->attr_id;
|
| 2637 | uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
|
| 2638 |
|
| 2639 | if (!(attr->flags & mask)) {
|
| 2640 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2641 | return 0;
|
| 2642 | }
|
| 2643 |
|
| 2644 | if (DEVICE_ATTR_IS(mem_busy_percent)) {
|
| 2645 | if ((adev->flags & AMD_IS_APU &&
|
| 2646 | gc_ver != IP_VERSION(9, 4, 3)) ||
|
| 2647 | gc_ver == IP_VERSION(9, 0, 1))
|
| 2648 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2649 | } else if (DEVICE_ATTR_IS(vcn_busy_percent)) {
|
| 2650 | if (!(gc_ver == IP_VERSION(9, 3, 0) ||
|
| 2651 | gc_ver == IP_VERSION(10, 3, 1) ||
|
| 2652 | gc_ver == IP_VERSION(10, 3, 3) ||
|
| 2653 | gc_ver == IP_VERSION(10, 3, 6) ||
|
| 2654 | gc_ver == IP_VERSION(10, 3, 7) ||
|
| 2655 | gc_ver == IP_VERSION(11, 0, 0) ||
|
| 2656 | gc_ver == IP_VERSION(11, 0, 1) ||
|
| 2657 | gc_ver == IP_VERSION(11, 0, 2) ||
|
| 2658 | gc_ver == IP_VERSION(11, 0, 3) ||
|
| 2659 | gc_ver == IP_VERSION(11, 0, 4) ||
|
| 2660 | gc_ver == IP_VERSION(11, 5, 0) ||
|
| 2661 | gc_ver == IP_VERSION(11, 5, 1) ||
|
| 2662 | gc_ver == IP_VERSION(11, 5, 2) ||
|
| 2663 | gc_ver == IP_VERSION(11, 5, 3) ||
|
| 2664 | gc_ver == IP_VERSION(12, 0, 0) ||
|
| 2665 | gc_ver == IP_VERSION(12, 0, 1)))
|
| 2666 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2667 | } else if (DEVICE_ATTR_IS(pcie_bw)) {
|
| 2668 |
|
| 2669 | if (adev->flags & AMD_IS_APU ||
|
| 2670 | !adev->asic_funcs->get_pcie_usage)
|
| 2671 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2672 | } else if (DEVICE_ATTR_IS(unique_id)) {
|
| 2673 | switch (gc_ver) {
|
| 2674 | case IP_VERSION(9, 0, 1):
|
| 2675 | case IP_VERSION(9, 4, 0):
|
| 2676 | case IP_VERSION(9, 4, 1):
|
| 2677 | case IP_VERSION(9, 4, 2):
|
| 2678 | case IP_VERSION(9, 4, 3):
|
| 2679 | case IP_VERSION(9, 4, 4):
|
| 2680 | case IP_VERSION(9, 5, 0):
|
| 2681 | case IP_VERSION(10, 3, 0):
|
| 2682 | case IP_VERSION(11, 0, 0):
|
| 2683 | case IP_VERSION(11, 0, 1):
|
| 2684 | case IP_VERSION(11, 0, 2):
|
| 2685 | case IP_VERSION(11, 0, 3):
|
| 2686 | case IP_VERSION(12, 0, 0):
|
| 2687 | case IP_VERSION(12, 0, 1):
|
| 2688 | case IP_VERSION(12, 1, 0):
|
| 2689 | *states = ATTR_STATE_SUPPORTED;
|
| 2690 | break;
|
| 2691 | default:
|
| 2692 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2693 | }
|
| 2694 | } else if (DEVICE_ATTR_IS(pp_features)) {
|
| 2695 | if ((adev->flags & AMD_IS_APU &&
|
| 2696 | gc_ver != IP_VERSION(9, 4, 3)) ||
|
| 2697 | gc_ver < IP_VERSION(9, 0, 0))
|
| 2698 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2699 |
|
| 2700 | if (adev->scpm_enabled) {
|
| 2701 | dev_attr->attr.mode &= ~S_IWUGO;
|
| 2702 | dev_attr->store = NULL;
|
| 2703 | }
|
| 2704 | } else if (DEVICE_ATTR_IS(gpu_metrics)) {
|
| 2705 | if (gc_ver < IP_VERSION(9, 1, 0))
|
| 2706 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2707 | } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
|
| 2708 | if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
|
| 2709 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2710 | else if ((gc_ver == IP_VERSION(10, 3, 0) ||
|
| 2711 | gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev))
|
| 2712 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2713 | } else if (DEVICE_ATTR_IS(pp_mclk_od)) {
|
| 2714 | if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP)
|
| 2715 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2716 | } else if (DEVICE_ATTR_IS(pp_sclk_od)) {
|
| 2717 | if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP)
|
| 2718 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2719 | } else if (DEVICE_ATTR_IS(apu_thermal_cap)) {
|
| 2720 | u32 limit;
|
| 2721 |
|
| 2722 | if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) ==
|
| 2723 | -EOPNOTSUPP)
|
| 2724 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2725 | } else if (DEVICE_ATTR_IS(pp_table)) {
|
| 2726 | int ret;
|
| 2727 |
|
| 2728 | ret = amdgpu_dpm_get_pp_table(adev, NULL, 0);
|
| 2729 | if (ret <= 0)
|
| 2730 | *states = ATTR_STATE_UNSUPPORTED;
|
| 2731 | else
|
| 2732 | *states = ATTR_STATE_SUPPORTED;
|
| 2733 | }
|
| 2734 |
|
| 2735 | switch (gc_ver) {
|
| 2736 | case IP_VERSION(10, 3, 0):
|
| 2737 | if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
|
| 2738 | amdgpu_sriov_vf(adev)) {
|
| 2739 | dev_attr->attr.mode &= ~0222;
|
| 2740 | dev_attr->store = NULL;
|
| 2741 | }
|
| 2742 | break;
|
| 2743 | default:
|
| 2744 | break;
|
| 2745 | }
|
| 2746 |
|
| 2747 | return 0;
|
| 2748 | }
|
| 2749 |
|
| 2750 |
|
| 2751 | static int amdgpu_device_attr_create(struct amdgpu_device *adev,
|
| 2752 | struct amdgpu_device_attr *attr,
|
| 2753 | uint32_t mask, struct list_head *attr_list)
|
| 2754 | {
|
| 2755 | int ret = 0;
|
| 2756 | enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
|
| 2757 | struct amdgpu_device_attr_entry *attr_entry;
|
| 2758 | struct device_attribute *dev_attr;
|
| 2759 | const char *name;
|
| 2760 |
|
| 2761 | int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
|
| 2762 | uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
|
| 2763 |
|
| 2764 | if (!attr)
|
| 2765 | return -EINVAL;
|
| 2766 |
|
| 2767 | dev_attr = &attr->dev_attr;
|
| 2768 | name = dev_attr->attr.name;
|
| 2769 |
|
| 2770 | attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
|
| 2771 |
|
| 2772 | ret = attr_update(adev, attr, mask, &attr_states);
|
| 2773 | if (ret) {
|
| 2774 | dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
|
| 2775 | name, ret);
|
| 2776 | return ret;
|
| 2777 | }
|
| 2778 |
|
| 2779 | if (attr_states == ATTR_STATE_UNSUPPORTED)
|
| 2780 | return 0;
|
| 2781 |
|
| 2782 | ret = device_create_file(adev->dev, dev_attr);
|
| 2783 | if (ret) {
|
| 2784 | dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
|
| 2785 | name, ret);
|
| 2786 | }
|
| 2787 |
|
| 2788 | attr_entry = kmalloc_obj(*attr_entry);
|
| 2789 | if (!attr_entry)
|
| 2790 | return -ENOMEM;
|
| 2791 |
|
| 2792 | attr_entry->attr = attr;
|
| 2793 | INIT_LIST_HEAD(&attr_entry->entry);
|
| 2794 |
|
| 2795 | list_add_tail(&attr_entry->entry, attr_list);
|
| 2796 |
|
| 2797 | return ret;
|
| 2798 | }
|
| 2799 |
|
| 2800 | static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
|
| 2801 | {
|
| 2802 | struct device_attribute *dev_attr = &attr->dev_attr;
|
| 2803 |
|
| 2804 | device_remove_file(adev->dev, dev_attr);
|
| 2805 | }
|
| 2806 |
|
| 2807 | static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
|
| 2808 | struct list_head *attr_list);
|
| 2809 |
|
| 2810 | static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
|
| 2811 | struct amdgpu_device_attr *attrs,
|
| 2812 | uint32_t counts,
|
| 2813 | uint32_t mask,
|
| 2814 | struct list_head *attr_list)
|
| 2815 | {
|
| 2816 | int ret = 0;
|
| 2817 | uint32_t i = 0;
|
| 2818 |
|
| 2819 | for (i = 0; i < counts; i++) {
|
| 2820 | ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
|
| 2821 | if (ret)
|
| 2822 | goto failed;
|
| 2823 | }
|
| 2824 |
|
| 2825 | return 0;
|
| 2826 |
|
| 2827 | failed:
|
| 2828 | amdgpu_device_attr_remove_groups(adev, attr_list);
|
| 2829 |
|
| 2830 | return ret;
|
| 2831 | }
|
| 2832 |
|
| 2833 | static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
|
| 2834 | struct list_head *attr_list)
|
| 2835 | {
|
| 2836 | struct amdgpu_device_attr_entry *entry, *entry_tmp;
|
| 2837 |
|
| 2838 | if (list_empty(attr_list))
|
| 2839 | return ;
|
| 2840 |
|
| 2841 | list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
|
| 2842 | amdgpu_device_attr_remove(adev, entry->attr);
|
| 2843 | list_del(&entry->entry);
|
| 2844 | kfree(entry);
|
| 2845 | }
|
| 2846 | }
|
| 2847 |
|
| 2848 | static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
|
| 2849 | struct device_attribute *attr,
|
| 2850 | char *buf)
|
| 2851 | {
|
| 2852 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 2853 | int channel = to_sensor_dev_attr(attr)->index;
|
| 2854 | int r, temp = 0;
|
| 2855 |
|
| 2856 | if (channel >= PP_TEMP_MAX)
|
| 2857 | return -EINVAL;
|
| 2858 |
|
| 2859 | switch (channel) {
|
| 2860 | case PP_TEMP_JUNCTION:
|
| 2861 |
|
| 2862 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
|
| 2863 | (void *)&temp);
|
| 2864 | break;
|
| 2865 | case PP_TEMP_EDGE:
|
| 2866 |
|
| 2867 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
|
| 2868 | (void *)&temp);
|
| 2869 | break;
|
| 2870 | case PP_TEMP_MEM:
|
| 2871 |
|
| 2872 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
|
| 2873 | (void *)&temp);
|
| 2874 | break;
|
| 2875 | default:
|
| 2876 | r = -EINVAL;
|
| 2877 | break;
|
| 2878 | }
|
| 2879 |
|
| 2880 | if (r)
|
| 2881 | return r;
|
| 2882 |
|
| 2883 | return sysfs_emit(buf, "%d\n", temp);
|
| 2884 | }
|
| 2885 |
|
| 2886 | static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
|
| 2887 | struct device_attribute *attr,
|
| 2888 | char *buf)
|
| 2889 | {
|
| 2890 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 2891 | int hyst = to_sensor_dev_attr(attr)->index;
|
| 2892 | int temp;
|
| 2893 |
|
| 2894 | if (hyst)
|
| 2895 | temp = adev->pm.dpm.thermal.min_temp;
|
| 2896 | else
|
| 2897 | temp = adev->pm.dpm.thermal.max_temp;
|
| 2898 |
|
| 2899 | return sysfs_emit(buf, "%d\n", temp);
|
| 2900 | }
|
| 2901 |
|
| 2902 | static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
|
| 2903 | struct device_attribute *attr,
|
| 2904 | char *buf)
|
| 2905 | {
|
| 2906 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 2907 | int hyst = to_sensor_dev_attr(attr)->index;
|
| 2908 | int temp;
|
| 2909 |
|
| 2910 | if (hyst)
|
| 2911 | temp = adev->pm.dpm.thermal.min_hotspot_temp;
|
| 2912 | else
|
| 2913 | temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
|
| 2914 |
|
| 2915 | return sysfs_emit(buf, "%d\n", temp);
|
| 2916 | }
|
| 2917 |
|
| 2918 | static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
|
| 2919 | struct device_attribute *attr,
|
| 2920 | char *buf)
|
| 2921 | {
|
| 2922 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 2923 | int hyst = to_sensor_dev_attr(attr)->index;
|
| 2924 | int temp;
|
| 2925 |
|
| 2926 | if (hyst)
|
| 2927 | temp = adev->pm.dpm.thermal.min_mem_temp;
|
| 2928 | else
|
| 2929 | temp = adev->pm.dpm.thermal.max_mem_crit_temp;
|
| 2930 |
|
| 2931 | return sysfs_emit(buf, "%d\n", temp);
|
| 2932 | }
|
| 2933 |
|
| 2934 | static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
|
| 2935 | struct device_attribute *attr,
|
| 2936 | char *buf)
|
| 2937 | {
|
| 2938 | int channel = to_sensor_dev_attr(attr)->index;
|
| 2939 |
|
| 2940 | if (channel >= PP_TEMP_MAX)
|
| 2941 | return -EINVAL;
|
| 2942 |
|
| 2943 | return sysfs_emit(buf, "%s\n", temp_label[channel].label);
|
| 2944 | }
|
| 2945 |
|
| 2946 | static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
|
| 2947 | struct device_attribute *attr,
|
| 2948 | char *buf)
|
| 2949 | {
|
| 2950 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 2951 | int channel = to_sensor_dev_attr(attr)->index;
|
| 2952 | int temp = 0;
|
| 2953 |
|
| 2954 | if (channel >= PP_TEMP_MAX)
|
| 2955 | return -EINVAL;
|
| 2956 |
|
| 2957 | switch (channel) {
|
| 2958 | case PP_TEMP_JUNCTION:
|
| 2959 | temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
|
| 2960 | break;
|
| 2961 | case PP_TEMP_EDGE:
|
| 2962 | temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
|
| 2963 | break;
|
| 2964 | case PP_TEMP_MEM:
|
| 2965 | temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
|
| 2966 | break;
|
| 2967 | }
|
| 2968 |
|
| 2969 | return sysfs_emit(buf, "%d\n", temp);
|
| 2970 | }
|
| 2971 |
|
| 2972 | static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
|
| 2973 | struct device_attribute *attr,
|
| 2974 | char *buf)
|
| 2975 | {
|
| 2976 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 2977 | u32 pwm_mode = 0;
|
| 2978 | int ret;
|
| 2979 |
|
| 2980 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 2981 | if (ret)
|
| 2982 | return ret;
|
| 2983 |
|
| 2984 | ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
|
| 2985 |
|
| 2986 | amdgpu_pm_put_access(adev);
|
| 2987 |
|
| 2988 | if (ret)
|
| 2989 | return -EINVAL;
|
| 2990 |
|
| 2991 | return sysfs_emit(buf, "%u\n", pwm_mode);
|
| 2992 | }
|
| 2993 |
|
| 2994 | static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
|
| 2995 | struct device_attribute *attr,
|
| 2996 | const char *buf,
|
| 2997 | size_t count)
|
| 2998 | {
|
| 2999 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3000 | int err, ret;
|
| 3001 | u32 pwm_mode;
|
| 3002 | int value;
|
| 3003 |
|
| 3004 | err = kstrtoint(buf, 10, &value);
|
| 3005 | if (err)
|
| 3006 | return err;
|
| 3007 |
|
| 3008 | if (value == 0)
|
| 3009 | pwm_mode = AMD_FAN_CTRL_NONE;
|
| 3010 | else if (value == 1)
|
| 3011 | pwm_mode = AMD_FAN_CTRL_MANUAL;
|
| 3012 | else if (value == 2)
|
| 3013 | pwm_mode = AMD_FAN_CTRL_AUTO;
|
| 3014 | else
|
| 3015 | return -EINVAL;
|
| 3016 |
|
| 3017 | ret = amdgpu_pm_get_access(adev);
|
| 3018 | if (ret < 0)
|
| 3019 | return ret;
|
| 3020 |
|
| 3021 | ret = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
|
| 3022 |
|
| 3023 | amdgpu_pm_put_access(adev);
|
| 3024 |
|
| 3025 | if (ret)
|
| 3026 | return -EINVAL;
|
| 3027 |
|
| 3028 | return count;
|
| 3029 | }
|
| 3030 |
|
| 3031 | static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
|
| 3032 | struct device_attribute *attr,
|
| 3033 | char *buf)
|
| 3034 | {
|
| 3035 | return sysfs_emit(buf, "%i\n", 0);
|
| 3036 | }
|
| 3037 |
|
| 3038 | static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
|
| 3039 | struct device_attribute *attr,
|
| 3040 | char *buf)
|
| 3041 | {
|
| 3042 | return sysfs_emit(buf, "%i\n", 255);
|
| 3043 | }
|
| 3044 |
|
| 3045 | static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
|
| 3046 | struct device_attribute *attr,
|
| 3047 | const char *buf, size_t count)
|
| 3048 | {
|
| 3049 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3050 | int err;
|
| 3051 | u32 value;
|
| 3052 | u32 pwm_mode;
|
| 3053 |
|
| 3054 | err = kstrtou32(buf, 10, &value);
|
| 3055 | if (err)
|
| 3056 | return err;
|
| 3057 |
|
| 3058 | err = amdgpu_pm_get_access(adev);
|
| 3059 | if (err < 0)
|
| 3060 | return err;
|
| 3061 |
|
| 3062 | err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
|
| 3063 | if (err)
|
| 3064 | goto out;
|
| 3065 |
|
| 3066 | if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
|
| 3067 | pr_info("manual fan speed control should be enabled first\n");
|
| 3068 | err = -EINVAL;
|
| 3069 | goto out;
|
| 3070 | }
|
| 3071 |
|
| 3072 | err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
|
| 3073 |
|
| 3074 | out:
|
| 3075 | amdgpu_pm_put_access(adev);
|
| 3076 |
|
| 3077 | if (err)
|
| 3078 | return err;
|
| 3079 |
|
| 3080 | return count;
|
| 3081 | }
|
| 3082 |
|
| 3083 | static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
|
| 3084 | struct device_attribute *attr,
|
| 3085 | char *buf)
|
| 3086 | {
|
| 3087 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3088 | int err;
|
| 3089 | u32 speed = 0;
|
| 3090 |
|
| 3091 | err = amdgpu_pm_get_access_if_active(adev);
|
| 3092 | if (err)
|
| 3093 | return err;
|
| 3094 |
|
| 3095 | err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
|
| 3096 |
|
| 3097 | amdgpu_pm_put_access(adev);
|
| 3098 |
|
| 3099 | if (err)
|
| 3100 | return err;
|
| 3101 |
|
| 3102 | return sysfs_emit(buf, "%i\n", speed);
|
| 3103 | }
|
| 3104 |
|
| 3105 | static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
|
| 3106 | struct device_attribute *attr,
|
| 3107 | char *buf)
|
| 3108 | {
|
| 3109 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3110 | int err;
|
| 3111 | u32 speed = 0;
|
| 3112 |
|
| 3113 | err = amdgpu_pm_get_access_if_active(adev);
|
| 3114 | if (err)
|
| 3115 | return err;
|
| 3116 |
|
| 3117 | err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
|
| 3118 |
|
| 3119 | amdgpu_pm_put_access(adev);
|
| 3120 |
|
| 3121 | if (err)
|
| 3122 | return err;
|
| 3123 |
|
| 3124 | return sysfs_emit(buf, "%i\n", speed);
|
| 3125 | }
|
| 3126 |
|
| 3127 | static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
|
| 3128 | struct device_attribute *attr,
|
| 3129 | char *buf)
|
| 3130 | {
|
| 3131 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3132 | u32 min_rpm = 0;
|
| 3133 | int r;
|
| 3134 |
|
| 3135 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
|
| 3136 | (void *)&min_rpm);
|
| 3137 |
|
| 3138 | if (r)
|
| 3139 | return r;
|
| 3140 |
|
| 3141 | return sysfs_emit(buf, "%d\n", min_rpm);
|
| 3142 | }
|
| 3143 |
|
| 3144 | static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
|
| 3145 | struct device_attribute *attr,
|
| 3146 | char *buf)
|
| 3147 | {
|
| 3148 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3149 | u32 max_rpm = 0;
|
| 3150 | int r;
|
| 3151 |
|
| 3152 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
|
| 3153 | (void *)&max_rpm);
|
| 3154 |
|
| 3155 | if (r)
|
| 3156 | return r;
|
| 3157 |
|
| 3158 | return sysfs_emit(buf, "%d\n", max_rpm);
|
| 3159 | }
|
| 3160 |
|
| 3161 | static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
|
| 3162 | struct device_attribute *attr,
|
| 3163 | char *buf)
|
| 3164 | {
|
| 3165 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3166 | int err;
|
| 3167 | u32 rpm = 0;
|
| 3168 |
|
| 3169 | err = amdgpu_pm_get_access_if_active(adev);
|
| 3170 | if (err)
|
| 3171 | return err;
|
| 3172 |
|
| 3173 | err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
|
| 3174 |
|
| 3175 | amdgpu_pm_put_access(adev);
|
| 3176 |
|
| 3177 | if (err)
|
| 3178 | return err;
|
| 3179 |
|
| 3180 | return sysfs_emit(buf, "%i\n", rpm);
|
| 3181 | }
|
| 3182 |
|
| 3183 | static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
|
| 3184 | struct device_attribute *attr,
|
| 3185 | const char *buf, size_t count)
|
| 3186 | {
|
| 3187 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3188 | int err;
|
| 3189 | u32 value;
|
| 3190 | u32 pwm_mode;
|
| 3191 |
|
| 3192 | err = kstrtou32(buf, 10, &value);
|
| 3193 | if (err)
|
| 3194 | return err;
|
| 3195 |
|
| 3196 | err = amdgpu_pm_get_access(adev);
|
| 3197 | if (err < 0)
|
| 3198 | return err;
|
| 3199 |
|
| 3200 | err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
|
| 3201 | if (err)
|
| 3202 | goto out;
|
| 3203 |
|
| 3204 | if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
|
| 3205 | err = -ENODATA;
|
| 3206 | goto out;
|
| 3207 | }
|
| 3208 |
|
| 3209 | err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
|
| 3210 |
|
| 3211 | out:
|
| 3212 | amdgpu_pm_put_access(adev);
|
| 3213 |
|
| 3214 | if (err)
|
| 3215 | return err;
|
| 3216 |
|
| 3217 | return count;
|
| 3218 | }
|
| 3219 |
|
| 3220 | static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
|
| 3221 | struct device_attribute *attr,
|
| 3222 | char *buf)
|
| 3223 | {
|
| 3224 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3225 | u32 pwm_mode = 0;
|
| 3226 | int ret;
|
| 3227 |
|
| 3228 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 3229 | if (ret)
|
| 3230 | return ret;
|
| 3231 |
|
| 3232 | ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
|
| 3233 |
|
| 3234 | amdgpu_pm_put_access(adev);
|
| 3235 |
|
| 3236 | if (ret)
|
| 3237 | return -EINVAL;
|
| 3238 |
|
| 3239 | return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
|
| 3240 | }
|
| 3241 |
|
| 3242 | static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
|
| 3243 | struct device_attribute *attr,
|
| 3244 | const char *buf,
|
| 3245 | size_t count)
|
| 3246 | {
|
| 3247 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3248 | int err;
|
| 3249 | int value;
|
| 3250 | u32 pwm_mode;
|
| 3251 |
|
| 3252 | err = kstrtoint(buf, 10, &value);
|
| 3253 | if (err)
|
| 3254 | return err;
|
| 3255 |
|
| 3256 | if (value == 0)
|
| 3257 | pwm_mode = AMD_FAN_CTRL_AUTO;
|
| 3258 | else if (value == 1)
|
| 3259 | pwm_mode = AMD_FAN_CTRL_MANUAL;
|
| 3260 | else
|
| 3261 | return -EINVAL;
|
| 3262 |
|
| 3263 | err = amdgpu_pm_get_access(adev);
|
| 3264 | if (err < 0)
|
| 3265 | return err;
|
| 3266 |
|
| 3267 | err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
|
| 3268 |
|
| 3269 | amdgpu_pm_put_access(adev);
|
| 3270 |
|
| 3271 | if (err)
|
| 3272 | return -EINVAL;
|
| 3273 |
|
| 3274 | return count;
|
| 3275 | }
|
| 3276 |
|
| 3277 | static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
|
| 3278 | struct device_attribute *attr,
|
| 3279 | char *buf)
|
| 3280 | {
|
| 3281 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3282 | u32 vddgfx;
|
| 3283 | int r;
|
| 3284 |
|
| 3285 |
|
| 3286 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX,
|
| 3287 | (void *)&vddgfx);
|
| 3288 | if (r)
|
| 3289 | return r;
|
| 3290 |
|
| 3291 | return sysfs_emit(buf, "%d\n", vddgfx);
|
| 3292 | }
|
| 3293 |
|
| 3294 | static ssize_t amdgpu_hwmon_show_vddboard(struct device *dev,
|
| 3295 | struct device_attribute *attr,
|
| 3296 | char *buf)
|
| 3297 | {
|
| 3298 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3299 | u32 vddboard;
|
| 3300 | int r;
|
| 3301 |
|
| 3302 |
|
| 3303 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDBOARD,
|
| 3304 | (void *)&vddboard);
|
| 3305 | if (r)
|
| 3306 | return r;
|
| 3307 |
|
| 3308 | return sysfs_emit(buf, "%d\n", vddboard);
|
| 3309 | }
|
| 3310 |
|
| 3311 | static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
|
| 3312 | struct device_attribute *attr,
|
| 3313 | char *buf)
|
| 3314 | {
|
| 3315 | return sysfs_emit(buf, "vddgfx\n");
|
| 3316 | }
|
| 3317 |
|
| 3318 | static ssize_t amdgpu_hwmon_show_vddboard_label(struct device *dev,
|
| 3319 | struct device_attribute *attr,
|
| 3320 | char *buf)
|
| 3321 | {
|
| 3322 | return sysfs_emit(buf, "vddboard\n");
|
| 3323 | }
|
| 3324 | static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
|
| 3325 | struct device_attribute *attr,
|
| 3326 | char *buf)
|
| 3327 | {
|
| 3328 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3329 | u32 vddnb;
|
| 3330 | int r;
|
| 3331 |
|
| 3332 |
|
| 3333 | if (!(adev->flags & AMD_IS_APU))
|
| 3334 | return -EINVAL;
|
| 3335 |
|
| 3336 |
|
| 3337 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB,
|
| 3338 | (void *)&vddnb);
|
| 3339 | if (r)
|
| 3340 | return r;
|
| 3341 |
|
| 3342 | return sysfs_emit(buf, "%d\n", vddnb);
|
| 3343 | }
|
| 3344 |
|
| 3345 | static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
|
| 3346 | struct device_attribute *attr,
|
| 3347 | char *buf)
|
| 3348 | {
|
| 3349 | return sysfs_emit(buf, "vddnb\n");
|
| 3350 | }
|
| 3351 |
|
| 3352 | static int amdgpu_hwmon_get_power(struct device *dev,
|
| 3353 | enum amd_pp_sensors sensor)
|
| 3354 | {
|
| 3355 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3356 | u32 query = 0;
|
| 3357 | int r;
|
| 3358 |
|
| 3359 | r = amdgpu_pm_get_sensor_generic(adev, sensor, (void *)&query);
|
| 3360 | if (r)
|
| 3361 | return r;
|
| 3362 |
|
| 3363 |
|
| 3364 | return query * 1000;
|
| 3365 | }
|
| 3366 |
|
| 3367 | static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
|
| 3368 | struct device_attribute *attr,
|
| 3369 | char *buf)
|
| 3370 | {
|
| 3371 | ssize_t val;
|
| 3372 |
|
| 3373 | val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
|
| 3374 | if (val < 0)
|
| 3375 | return val;
|
| 3376 |
|
| 3377 | return sysfs_emit(buf, "%zd\n", val);
|
| 3378 | }
|
| 3379 |
|
| 3380 | static ssize_t amdgpu_hwmon_show_power_input(struct device *dev,
|
| 3381 | struct device_attribute *attr,
|
| 3382 | char *buf)
|
| 3383 | {
|
| 3384 | ssize_t val;
|
| 3385 |
|
| 3386 | val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
|
| 3387 | if (val < 0)
|
| 3388 | return val;
|
| 3389 |
|
| 3390 | return sysfs_emit(buf, "%zd\n", val);
|
| 3391 | }
|
| 3392 |
|
| 3393 | static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
|
| 3394 | struct device_attribute *attr,
|
| 3395 | char *buf,
|
| 3396 | enum pp_power_limit_level pp_limit_level)
|
| 3397 | {
|
| 3398 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3399 | enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
|
| 3400 | uint32_t limit;
|
| 3401 | ssize_t size;
|
| 3402 | int r;
|
| 3403 |
|
| 3404 | r = amdgpu_pm_get_access_if_active(adev);
|
| 3405 | if (r)
|
| 3406 | return r;
|
| 3407 |
|
| 3408 | r = amdgpu_dpm_get_power_limit(adev, &limit,
|
| 3409 | pp_limit_level, power_type);
|
| 3410 |
|
| 3411 | if (!r)
|
| 3412 | size = sysfs_emit(buf, "%u\n", limit * 1000000);
|
| 3413 | else
|
| 3414 | size = sysfs_emit(buf, "\n");
|
| 3415 |
|
| 3416 | amdgpu_pm_put_access(adev);
|
| 3417 |
|
| 3418 | return size;
|
| 3419 | }
|
| 3420 |
|
| 3421 | static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
|
| 3422 | struct device_attribute *attr,
|
| 3423 | char *buf)
|
| 3424 | {
|
| 3425 | return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN);
|
| 3426 | }
|
| 3427 |
|
| 3428 | static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
|
| 3429 | struct device_attribute *attr,
|
| 3430 | char *buf)
|
| 3431 | {
|
| 3432 | return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
|
| 3433 |
|
| 3434 | }
|
| 3435 |
|
| 3436 | static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
|
| 3437 | struct device_attribute *attr,
|
| 3438 | char *buf)
|
| 3439 | {
|
| 3440 | return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
|
| 3441 |
|
| 3442 | }
|
| 3443 |
|
| 3444 | static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
|
| 3445 | struct device_attribute *attr,
|
| 3446 | char *buf)
|
| 3447 | {
|
| 3448 | return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
|
| 3449 |
|
| 3450 | }
|
| 3451 |
|
| 3452 | static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
|
| 3453 | struct device_attribute *attr,
|
| 3454 | char *buf)
|
| 3455 | {
|
| 3456 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3457 | uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
|
| 3458 |
|
| 3459 | if (gc_ver == IP_VERSION(10, 3, 1))
|
| 3460 | return sysfs_emit(buf, "%s\n",
|
| 3461 | to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
|
| 3462 | "fastPPT" : "slowPPT");
|
| 3463 | else
|
| 3464 | return sysfs_emit(buf, "%s\n",
|
| 3465 | to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
|
| 3466 | "PPT1" : "PPT");
|
| 3467 | }
|
| 3468 |
|
| 3469 | static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
|
| 3470 | struct device_attribute *attr,
|
| 3471 | const char *buf,
|
| 3472 | size_t count)
|
| 3473 | {
|
| 3474 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3475 | int limit_type = to_sensor_dev_attr(attr)->index;
|
| 3476 | int err;
|
| 3477 | u32 value;
|
| 3478 |
|
| 3479 | err = kstrtou32(buf, 10, &value);
|
| 3480 | if (err)
|
| 3481 | return err;
|
| 3482 |
|
| 3483 | value = value / 1000000;
|
| 3484 |
|
| 3485 | err = amdgpu_pm_get_access(adev);
|
| 3486 | if (err < 0)
|
| 3487 | return err;
|
| 3488 |
|
| 3489 | err = amdgpu_dpm_set_power_limit(adev, limit_type, value);
|
| 3490 |
|
| 3491 | amdgpu_pm_put_access(adev);
|
| 3492 |
|
| 3493 | if (err)
|
| 3494 | return err;
|
| 3495 |
|
| 3496 | return count;
|
| 3497 | }
|
| 3498 |
|
| 3499 | static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
|
| 3500 | struct device_attribute *attr,
|
| 3501 | char *buf)
|
| 3502 | {
|
| 3503 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3504 | uint32_t sclk;
|
| 3505 | int r;
|
| 3506 |
|
| 3507 |
|
| 3508 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
|
| 3509 | (void *)&sclk);
|
| 3510 | if (r)
|
| 3511 | return r;
|
| 3512 |
|
| 3513 | return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
|
| 3514 | }
|
| 3515 |
|
| 3516 | static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
|
| 3517 | struct device_attribute *attr,
|
| 3518 | char *buf)
|
| 3519 | {
|
| 3520 | return sysfs_emit(buf, "sclk\n");
|
| 3521 | }
|
| 3522 |
|
| 3523 | static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
|
| 3524 | struct device_attribute *attr,
|
| 3525 | char *buf)
|
| 3526 | {
|
| 3527 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3528 | uint32_t mclk;
|
| 3529 | int r;
|
| 3530 |
|
| 3531 |
|
| 3532 | r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
|
| 3533 | (void *)&mclk);
|
| 3534 | if (r)
|
| 3535 | return r;
|
| 3536 |
|
| 3537 | return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
|
| 3538 | }
|
| 3539 |
|
| 3540 | static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
|
| 3541 | struct device_attribute *attr,
|
| 3542 | char *buf)
|
| 3543 | {
|
| 3544 | return sysfs_emit(buf, "mclk\n");
|
| 3545 | }
|
| 3546 |
|
| 3547 | |
| 3548 | * DOC: hwmon
|
| 3549 | *
|
| 3550 | * The amdgpu driver exposes the following sensor interfaces:
|
| 3551 | *
|
| 3552 | * - GPU temperature (via the on-die sensor)
|
| 3553 | *
|
| 3554 | * - GPU voltage
|
| 3555 | *
|
| 3556 | * - Northbridge voltage (APUs only)
|
| 3557 | *
|
| 3558 | * - GPU power
|
| 3559 | *
|
| 3560 | * - GPU fan
|
| 3561 | *
|
| 3562 | * - GPU gfx/compute engine clock
|
| 3563 | *
|
| 3564 | * - GPU memory clock (dGPU only)
|
| 3565 | *
|
| 3566 | * hwmon interfaces for GPU temperature:
|
| 3567 | *
|
| 3568 | * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
|
| 3569 | * - temp2_input and temp3_input are supported on SOC15 dGPUs only
|
| 3570 | *
|
| 3571 | * - temp[1-3]_label: temperature channel label
|
| 3572 | * - temp2_label and temp3_label are supported on SOC15 dGPUs only
|
| 3573 | *
|
| 3574 | * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
|
| 3575 | * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
|
| 3576 | *
|
| 3577 | * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
|
| 3578 | * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
|
| 3579 | *
|
| 3580 | * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
|
| 3581 | * - these are supported on SOC15 dGPUs only
|
| 3582 | *
|
| 3583 | * hwmon interfaces for GPU voltage:
|
| 3584 | *
|
| 3585 | * - in0_input: the voltage on the GPU in millivolts
|
| 3586 | *
|
| 3587 | * - in1_input: the voltage on the Northbridge in millivolts
|
| 3588 | *
|
| 3589 | * hwmon interfaces for GPU power:
|
| 3590 | *
|
| 3591 | * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU.
|
| 3592 | *
|
| 3593 | * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU.
|
| 3594 | *
|
| 3595 | * - power1_cap_min: minimum cap supported in microWatts
|
| 3596 | *
|
| 3597 | * - power1_cap_max: maximum cap supported in microWatts
|
| 3598 | *
|
| 3599 | * - power1_cap: selected power cap in microWatts
|
| 3600 | *
|
| 3601 | * hwmon interfaces for GPU fan:
|
| 3602 | *
|
| 3603 | * - pwm1: pulse width modulation fan level (0-255)
|
| 3604 | *
|
| 3605 | * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
|
| 3606 | *
|
| 3607 | * - pwm1_min: pulse width modulation fan control minimum level (0)
|
| 3608 | *
|
| 3609 | * - pwm1_max: pulse width modulation fan control maximum level (255)
|
| 3610 | *
|
| 3611 | * - fan1_min: a minimum value Unit: revolution/min (RPM)
|
| 3612 | *
|
| 3613 | * - fan1_max: a maximum value Unit: revolution/max (RPM)
|
| 3614 | *
|
| 3615 | * - fan1_input: fan speed in RPM
|
| 3616 | *
|
| 3617 | * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
|
| 3618 | *
|
| 3619 | * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
|
| 3620 | *
|
| 3621 | * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
|
| 3622 | * That will get the former one overridden.
|
| 3623 | *
|
| 3624 | * hwmon interfaces for GPU clocks:
|
| 3625 | *
|
| 3626 | * - freq1_input: the gfx/compute clock in hertz
|
| 3627 | *
|
| 3628 | * - freq2_input: the memory clock in hertz
|
| 3629 | *
|
| 3630 | * You can use hwmon tools like sensors to view this information on your system.
|
| 3631 | *
|
| 3632 |
|
| 3633 |
|
| 3634 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
|
| 3635 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
|
| 3636 | static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
|
| 3637 | static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
|
| 3638 | static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
|
| 3639 | static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
|
| 3640 | static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
|
| 3641 | static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
|
| 3642 | static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
|
| 3643 | static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
|
| 3644 | static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
|
| 3645 | static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
|
| 3646 | static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
|
| 3647 | static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
|
| 3648 | static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
|
| 3649 | static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
|
| 3650 | static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
|
| 3651 | static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
|
| 3652 | static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
|
| 3653 | static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
|
| 3654 | static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
|
| 3655 | static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
|
| 3656 | static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
|
| 3657 | static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
|
| 3658 | static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
|
| 3659 | static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
|
| 3660 | static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
|
| 3661 | static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
|
| 3662 | static SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, amdgpu_hwmon_show_vddboard, NULL, 0);
|
| 3663 | static SENSOR_DEVICE_ATTR(in2_label, S_IRUGO, amdgpu_hwmon_show_vddboard_label, NULL, 0);
|
| 3664 | static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
|
| 3665 | static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0);
|
| 3666 | static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
|
| 3667 | static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
|
| 3668 | static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
|
| 3669 | static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
|
| 3670 | static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
|
| 3671 | static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
|
| 3672 | static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
|
| 3673 | static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
|
| 3674 | static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
|
| 3675 | static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
|
| 3676 | static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
|
| 3677 | static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
|
| 3678 | static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
|
| 3679 | static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
|
| 3680 |
|
| 3681 | static struct attribute *hwmon_attributes[] = {
|
| 3682 | &sensor_dev_attr_temp1_input.dev_attr.attr,
|
| 3683 | &sensor_dev_attr_temp1_crit.dev_attr.attr,
|
| 3684 | &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
|
| 3685 | &sensor_dev_attr_temp2_input.dev_attr.attr,
|
| 3686 | &sensor_dev_attr_temp2_crit.dev_attr.attr,
|
| 3687 | &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
|
| 3688 | &sensor_dev_attr_temp3_input.dev_attr.attr,
|
| 3689 | &sensor_dev_attr_temp3_crit.dev_attr.attr,
|
| 3690 | &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
|
| 3691 | &sensor_dev_attr_temp1_emergency.dev_attr.attr,
|
| 3692 | &sensor_dev_attr_temp2_emergency.dev_attr.attr,
|
| 3693 | &sensor_dev_attr_temp3_emergency.dev_attr.attr,
|
| 3694 | &sensor_dev_attr_temp1_label.dev_attr.attr,
|
| 3695 | &sensor_dev_attr_temp2_label.dev_attr.attr,
|
| 3696 | &sensor_dev_attr_temp3_label.dev_attr.attr,
|
| 3697 | &sensor_dev_attr_pwm1.dev_attr.attr,
|
| 3698 | &sensor_dev_attr_pwm1_enable.dev_attr.attr,
|
| 3699 | &sensor_dev_attr_pwm1_min.dev_attr.attr,
|
| 3700 | &sensor_dev_attr_pwm1_max.dev_attr.attr,
|
| 3701 | &sensor_dev_attr_fan1_input.dev_attr.attr,
|
| 3702 | &sensor_dev_attr_fan1_min.dev_attr.attr,
|
| 3703 | &sensor_dev_attr_fan1_max.dev_attr.attr,
|
| 3704 | &sensor_dev_attr_fan1_target.dev_attr.attr,
|
| 3705 | &sensor_dev_attr_fan1_enable.dev_attr.attr,
|
| 3706 | &sensor_dev_attr_in0_input.dev_attr.attr,
|
| 3707 | &sensor_dev_attr_in0_label.dev_attr.attr,
|
| 3708 | &sensor_dev_attr_in1_input.dev_attr.attr,
|
| 3709 | &sensor_dev_attr_in1_label.dev_attr.attr,
|
| 3710 | &sensor_dev_attr_in2_input.dev_attr.attr,
|
| 3711 | &sensor_dev_attr_in2_label.dev_attr.attr,
|
| 3712 | &sensor_dev_attr_power1_average.dev_attr.attr,
|
| 3713 | &sensor_dev_attr_power1_input.dev_attr.attr,
|
| 3714 | &sensor_dev_attr_power1_cap_max.dev_attr.attr,
|
| 3715 | &sensor_dev_attr_power1_cap_min.dev_attr.attr,
|
| 3716 | &sensor_dev_attr_power1_cap.dev_attr.attr,
|
| 3717 | &sensor_dev_attr_power1_cap_default.dev_attr.attr,
|
| 3718 | &sensor_dev_attr_power1_label.dev_attr.attr,
|
| 3719 | &sensor_dev_attr_power2_cap_max.dev_attr.attr,
|
| 3720 | &sensor_dev_attr_power2_cap_min.dev_attr.attr,
|
| 3721 | &sensor_dev_attr_power2_cap.dev_attr.attr,
|
| 3722 | &sensor_dev_attr_power2_cap_default.dev_attr.attr,
|
| 3723 | &sensor_dev_attr_power2_label.dev_attr.attr,
|
| 3724 | &sensor_dev_attr_freq1_input.dev_attr.attr,
|
| 3725 | &sensor_dev_attr_freq1_label.dev_attr.attr,
|
| 3726 | &sensor_dev_attr_freq2_input.dev_attr.attr,
|
| 3727 | &sensor_dev_attr_freq2_label.dev_attr.attr,
|
| 3728 | NULL
|
| 3729 | };
|
| 3730 |
|
| 3731 | static umode_t hwmon_attributes_visible(struct kobject *kobj,
|
| 3732 | struct attribute *attr, int index)
|
| 3733 | {
|
| 3734 | struct device *dev = kobj_to_dev(kobj);
|
| 3735 | struct amdgpu_device *adev = dev_get_drvdata(dev);
|
| 3736 | umode_t effective_mode = attr->mode;
|
| 3737 | uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
|
| 3738 | uint32_t tmp;
|
| 3739 |
|
| 3740 |
|
| 3741 | if (amdgpu_sriov_is_pp_one_vf(adev))
|
| 3742 | effective_mode &= ~S_IWUSR;
|
| 3743 |
|
| 3744 |
|
| 3745 | if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
|
| 3746 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
|
| 3747 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
|
| 3748 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
|
| 3749 | attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
|
| 3750 | attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
|
| 3751 | attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
|
| 3752 | attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
|
| 3753 | attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
|
| 3754 | return 0;
|
| 3755 |
|
| 3756 |
|
| 3757 | if ((adev->flags & AMD_IS_APU) &&
|
| 3758 | (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
|
| 3759 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
|
| 3760 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
|
| 3761 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
|
| 3762 | attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
|
| 3763 | attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
|
| 3764 | attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
|
| 3765 | attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
|
| 3766 | attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
|
| 3767 | return 0;
|
| 3768 |
|
| 3769 |
|
| 3770 | if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
|
| 3771 | amdgpu_is_multi_aid(adev)) &&
|
| 3772 | (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
|
| 3773 | attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
|
| 3774 | return 0;
|
| 3775 |
|
| 3776 |
|
| 3777 | if (!adev->pm.dpm_enabled &&
|
| 3778 | (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
|
| 3779 | attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
|
| 3780 | attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
|
| 3781 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
|
| 3782 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
|
| 3783 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
|
| 3784 | attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
|
| 3785 | attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
|
| 3786 | attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
|
| 3787 | attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
|
| 3788 | attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
|
| 3789 | return 0;
|
| 3790 |
|
| 3791 |
|
| 3792 | if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
|
| 3793 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) ||
|
| 3794 | ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
|
| 3795 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr))
|
| 3796 | effective_mode &= ~S_IRUGO;
|
| 3797 |
|
| 3798 | if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
|
| 3799 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) ||
|
| 3800 | ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
|
| 3801 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr))
|
| 3802 | effective_mode &= ~S_IWUSR;
|
| 3803 |
|
| 3804 |
|
| 3805 | if (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
|
| 3806 | attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
|
| 3807 | attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
|
| 3808 | attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr) {
|
| 3809 | if (adev->family == AMDGPU_FAMILY_SI ||
|
| 3810 | ((adev->flags & AMD_IS_APU) && gc_ver != IP_VERSION(10, 3, 1) &&
|
| 3811 | (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4))) ||
|
| 3812 | (amdgpu_sriov_vf(adev) && gc_ver == IP_VERSION(11, 0, 3)))
|
| 3813 | return 0;
|
| 3814 | }
|
| 3815 |
|
| 3816 | if (attr == &sensor_dev_attr_power1_cap.dev_attr.attr &&
|
| 3817 | amdgpu_virt_cap_is_rw(&adev->virt.virt_caps, AMDGPU_VIRT_CAP_POWER_LIMIT))
|
| 3818 | effective_mode |= S_IWUSR;
|
| 3819 |
|
| 3820 |
|
| 3821 | if (((adev->family == AMDGPU_FAMILY_SI) ||
|
| 3822 | ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
|
| 3823 | (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
|
| 3824 | return 0;
|
| 3825 |
|
| 3826 |
|
| 3827 | if (attr == &sensor_dev_attr_power1_average.dev_attr.attr &&
|
| 3828 | amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER,
|
| 3829 | (void *)&tmp) == -EOPNOTSUPP)
|
| 3830 | return 0;
|
| 3831 | if (attr == &sensor_dev_attr_power1_input.dev_attr.attr &&
|
| 3832 | amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
|
| 3833 | (void *)&tmp) == -EOPNOTSUPP)
|
| 3834 | return 0;
|
| 3835 |
|
| 3836 |
|
| 3837 | if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
|
| 3838 | (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
|
| 3839 | (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
|
| 3840 | (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
|
| 3841 | (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
|
| 3842 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
|
| 3843 | return 0;
|
| 3844 |
|
| 3845 | if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
|
| 3846 | (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
|
| 3847 | (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
|
| 3848 | attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
|
| 3849 | return 0;
|
| 3850 |
|
| 3851 | if ((adev->family == AMDGPU_FAMILY_SI ||
|
| 3852 | adev->family == AMDGPU_FAMILY_KV ||
|
| 3853 | amdgpu_is_multi_aid(adev)) &&
|
| 3854 | (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
|
| 3855 | attr == &sensor_dev_attr_in0_label.dev_attr.attr))
|
| 3856 | return 0;
|
| 3857 |
|
| 3858 |
|
| 3859 | if ((!(adev->flags & AMD_IS_APU) ||
|
| 3860 | amdgpu_is_multi_aid(adev)) &&
|
| 3861 | (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
|
| 3862 | attr == &sensor_dev_attr_in1_label.dev_attr.attr))
|
| 3863 | return 0;
|
| 3864 |
|
| 3865 |
|
| 3866 | if ((attr == &sensor_dev_attr_in2_input.dev_attr.attr ||
|
| 3867 | attr == &sensor_dev_attr_in2_label.dev_attr.attr) &&
|
| 3868 | amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDBOARD,
|
| 3869 | (void *)&tmp) == -EOPNOTSUPP)
|
| 3870 | return 0;
|
| 3871 |
|
| 3872 |
|
| 3873 | if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
|
| 3874 | (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
|
| 3875 | attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
|
| 3876 | return 0;
|
| 3877 |
|
| 3878 | if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
|
| 3879 | (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4)) &&
|
| 3880 | (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
|
| 3881 | attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
|
| 3882 | attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
|
| 3883 | attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
|
| 3884 | attr == &sensor_dev_attr_temp3_label.dev_attr.attr ||
|
| 3885 | attr == &sensor_dev_attr_temp3_crit.dev_attr.attr))
|
| 3886 | return 0;
|
| 3887 |
|
| 3888 |
|
| 3889 | if (amdgpu_is_multi_aid(adev)) {
|
| 3890 | if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
|
| 3891 | attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
|
| 3892 | attr == &sensor_dev_attr_temp1_label.dev_attr.attr)
|
| 3893 | return 0;
|
| 3894 |
|
| 3895 | if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
|
| 3896 | attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)
|
| 3897 | return attr->mode;
|
| 3898 | }
|
| 3899 |
|
| 3900 |
|
| 3901 | if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
|
| 3902 | (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
|
| 3903 | attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
|
| 3904 | attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
|
| 3905 | attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
|
| 3906 | attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
|
| 3907 | return 0;
|
| 3908 |
|
| 3909 |
|
| 3910 | if ((attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
|
| 3911 | attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
|
| 3912 | attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
|
| 3913 | attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
|
| 3914 | attr == &sensor_dev_attr_power2_label.dev_attr.attr) &&
|
| 3915 | (amdgpu_dpm_get_power_limit(adev, &tmp,
|
| 3916 | PP_PWR_LIMIT_MAX,
|
| 3917 | PP_PWR_TYPE_FAST) == -EOPNOTSUPP))
|
| 3918 | return 0;
|
| 3919 |
|
| 3920 | return effective_mode;
|
| 3921 | }
|
| 3922 |
|
| 3923 | static const struct attribute_group hwmon_attrgroup = {
|
| 3924 | .attrs = hwmon_attributes,
|
| 3925 | .is_visible = hwmon_attributes_visible,
|
| 3926 | };
|
| 3927 |
|
| 3928 | static const struct attribute_group *hwmon_groups[] = {
|
| 3929 | &hwmon_attrgroup,
|
| 3930 | NULL
|
| 3931 | };
|
| 3932 |
|
| 3933 | static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev,
|
| 3934 | enum pp_clock_type od_type,
|
| 3935 | char *buf)
|
| 3936 | {
|
| 3937 | int size = 0;
|
| 3938 | int ret;
|
| 3939 |
|
| 3940 | ret = amdgpu_pm_get_access_if_active(adev);
|
| 3941 | if (ret)
|
| 3942 | return ret;
|
| 3943 |
|
| 3944 | ret = amdgpu_dpm_emit_clock_levels(adev, od_type, buf, &size);
|
| 3945 | if (ret) {
|
| 3946 | size = ret;
|
| 3947 | goto out_pm_put;
|
| 3948 | }
|
| 3949 | if (size == 0)
|
| 3950 | size = sysfs_emit(buf, "\n");
|
| 3951 |
|
| 3952 | out_pm_put:
|
| 3953 | amdgpu_pm_put_access(adev);
|
| 3954 |
|
| 3955 | return size;
|
| 3956 | }
|
| 3957 |
|
| 3958 | static int parse_input_od_command_lines(const char *buf, size_t count,
|
| 3959 | u32 *type, long *params,
|
| 3960 | uint32_t max_params,
|
| 3961 | uint32_t *num_of_params)
|
| 3962 | {
|
| 3963 | uint32_t parameter_size = 0;
|
| 3964 | char buf_cpy[128] = {0};
|
| 3965 | char *tmp_str;
|
| 3966 |
|
| 3967 | if (count > sizeof(buf_cpy) - 1)
|
| 3968 | return -EINVAL;
|
| 3969 |
|
| 3970 | memcpy(buf_cpy, buf, count);
|
| 3971 | tmp_str = buf_cpy;
|
| 3972 |
|
| 3973 |
|
| 3974 | while (isspace(*tmp_str))
|
| 3975 | tmp_str++;
|
| 3976 |
|
| 3977 | switch (*tmp_str) {
|
| 3978 | case 'c':
|
| 3979 | *type = PP_OD_COMMIT_DPM_TABLE;
|
| 3980 | return 0;
|
| 3981 | case 'r':
|
| 3982 | params[parameter_size] = *type;
|
| 3983 | *num_of_params = 1;
|
| 3984 | *type = PP_OD_RESTORE_DEFAULT_TABLE;
|
| 3985 | return 0;
|
| 3986 | default:
|
| 3987 | break;
|
| 3988 | }
|
| 3989 |
|
| 3990 | return amdgpu_pm_parse_long_params(tmp_str, params, max_params,
|
| 3991 | num_of_params);
|
| 3992 | }
|
| 3993 |
|
| 3994 | static int
|
| 3995 | amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev,
|
| 3996 | enum PP_OD_DPM_TABLE_COMMAND cmd_type,
|
| 3997 | const char *in_buf,
|
| 3998 | size_t count)
|
| 3999 | {
|
| 4000 | uint32_t parameter_size = 0;
|
| 4001 | long parameter[64];
|
| 4002 | int ret;
|
| 4003 |
|
| 4004 | ret = parse_input_od_command_lines(in_buf, count, &cmd_type, parameter,
|
| 4005 | ARRAY_SIZE(parameter),
|
| 4006 | ¶meter_size);
|
| 4007 | if (ret)
|
| 4008 | return ret;
|
| 4009 |
|
| 4010 | ret = amdgpu_pm_get_access(adev);
|
| 4011 | if (ret < 0)
|
| 4012 | return ret;
|
| 4013 |
|
| 4014 | ret = amdgpu_dpm_odn_edit_dpm_table(adev,
|
| 4015 | cmd_type,
|
| 4016 | parameter,
|
| 4017 | parameter_size);
|
| 4018 | if (ret)
|
| 4019 | goto err_out;
|
| 4020 |
|
| 4021 | if (cmd_type == PP_OD_COMMIT_DPM_TABLE) {
|
| 4022 | ret = amdgpu_dpm_dispatch_task(adev,
|
| 4023 | AMD_PP_TASK_READJUST_POWER_STATE,
|
| 4024 | NULL);
|
| 4025 | if (ret)
|
| 4026 | goto err_out;
|
| 4027 | }
|
| 4028 |
|
| 4029 | amdgpu_pm_put_access(adev);
|
| 4030 |
|
| 4031 | return count;
|
| 4032 |
|
| 4033 | err_out:
|
| 4034 | amdgpu_pm_put_access(adev);
|
| 4035 |
|
| 4036 | return ret;
|
| 4037 | }
|
| 4038 |
|
| 4039 | |
| 4040 | * DOC: fan_curve
|
| 4041 | *
|
| 4042 | * The amdgpu driver provides a sysfs API for checking and adjusting the fan
|
| 4043 | * control curve line.
|
| 4044 | *
|
| 4045 | * Reading back the file shows you the current settings(temperature in Celsius
|
| 4046 | * degree and fan speed in pwm) applied to every anchor point of the curve line
|
| 4047 | * and their permitted ranges if changable.
|
| 4048 | *
|
| 4049 | * Writing a desired string(with the format like "anchor_point_index temperature
|
| 4050 | * fan_speed_in_pwm") to the file, change the settings for the specific anchor
|
| 4051 | * point accordingly.
|
| 4052 | *
|
| 4053 | * When you have finished the editing, write "c" (commit) to the file to commit
|
| 4054 | * your changes.
|
| 4055 | *
|
| 4056 | * If you want to reset to the default value, write "r" (reset) to the file to
|
| 4057 | * reset them
|
| 4058 | *
|
| 4059 | * There are two fan control modes supported: auto and manual. With auto mode,
|
| 4060 | * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature).
|
| 4061 | * While with manual mode, users can set their own fan curve line as what
|
| 4062 | * described here. Normally the ASIC is booted up with auto mode. Any
|
| 4063 | * settings via this interface will switch the fan control to manual mode
|
| 4064 | * implicitly.
|
| 4065 |
|
| 4066 | static ssize_t fan_curve_show(struct kobject *kobj,
|
| 4067 | struct kobj_attribute *attr,
|
| 4068 | char *buf)
|
| 4069 | {
|
| 4070 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4071 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4072 |
|
| 4073 | return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf);
|
| 4074 | }
|
| 4075 |
|
| 4076 | static ssize_t fan_curve_store(struct kobject *kobj,
|
| 4077 | struct kobj_attribute *attr,
|
| 4078 | const char *buf,
|
| 4079 | size_t count)
|
| 4080 | {
|
| 4081 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4082 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4083 |
|
| 4084 | return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
|
| 4085 | PP_OD_EDIT_FAN_CURVE,
|
| 4086 | buf,
|
| 4087 | count);
|
| 4088 | }
|
| 4089 |
|
| 4090 | static umode_t fan_curve_visible(struct amdgpu_device *adev)
|
| 4091 | {
|
| 4092 | umode_t umode = 0000;
|
| 4093 |
|
| 4094 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE)
|
| 4095 | umode |= S_IRUSR | S_IRGRP | S_IROTH;
|
| 4096 |
|
| 4097 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET)
|
| 4098 | umode |= S_IWUSR;
|
| 4099 |
|
| 4100 | return umode;
|
| 4101 | }
|
| 4102 |
|
| 4103 | |
| 4104 | * DOC: acoustic_limit_rpm_threshold
|
| 4105 | *
|
| 4106 | * The amdgpu driver provides a sysfs API for checking and adjusting the
|
| 4107 | * acoustic limit in RPM for fan control.
|
| 4108 | *
|
| 4109 | * Reading back the file shows you the current setting and the permitted
|
| 4110 | * ranges if changable.
|
| 4111 | *
|
| 4112 | * Writing an integer to the file, change the setting accordingly.
|
| 4113 | *
|
| 4114 | * When you have finished the editing, write "c" (commit) to the file to commit
|
| 4115 | * your changes.
|
| 4116 | *
|
| 4117 | * If you want to reset to the default value, write "r" (reset) to the file to
|
| 4118 | * reset them
|
| 4119 | *
|
| 4120 | * This setting works under auto fan control mode only. It adjusts the PMFW's
|
| 4121 | * behavior about the maximum speed in RPM the fan can spin. Setting via this
|
| 4122 | * interface will switch the fan control to auto mode implicitly.
|
| 4123 |
|
| 4124 | static ssize_t acoustic_limit_threshold_show(struct kobject *kobj,
|
| 4125 | struct kobj_attribute *attr,
|
| 4126 | char *buf)
|
| 4127 | {
|
| 4128 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4129 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4130 |
|
| 4131 | return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf);
|
| 4132 | }
|
| 4133 |
|
| 4134 | static ssize_t acoustic_limit_threshold_store(struct kobject *kobj,
|
| 4135 | struct kobj_attribute *attr,
|
| 4136 | const char *buf,
|
| 4137 | size_t count)
|
| 4138 | {
|
| 4139 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4140 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4141 |
|
| 4142 | return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
|
| 4143 | PP_OD_EDIT_ACOUSTIC_LIMIT,
|
| 4144 | buf,
|
| 4145 | count);
|
| 4146 | }
|
| 4147 |
|
| 4148 | static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev)
|
| 4149 | {
|
| 4150 | umode_t umode = 0000;
|
| 4151 |
|
| 4152 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE)
|
| 4153 | umode |= S_IRUSR | S_IRGRP | S_IROTH;
|
| 4154 |
|
| 4155 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET)
|
| 4156 | umode |= S_IWUSR;
|
| 4157 |
|
| 4158 | return umode;
|
| 4159 | }
|
| 4160 |
|
| 4161 | |
| 4162 | * DOC: acoustic_target_rpm_threshold
|
| 4163 | *
|
| 4164 | * The amdgpu driver provides a sysfs API for checking and adjusting the
|
| 4165 | * acoustic target in RPM for fan control.
|
| 4166 | *
|
| 4167 | * Reading back the file shows you the current setting and the permitted
|
| 4168 | * ranges if changable.
|
| 4169 | *
|
| 4170 | * Writing an integer to the file, change the setting accordingly.
|
| 4171 | *
|
| 4172 | * When you have finished the editing, write "c" (commit) to the file to commit
|
| 4173 | * your changes.
|
| 4174 | *
|
| 4175 | * If you want to reset to the default value, write "r" (reset) to the file to
|
| 4176 | * reset them
|
| 4177 | *
|
| 4178 | * This setting works under auto fan control mode only. It can co-exist with
|
| 4179 | * other settings which can work also under auto mode. It adjusts the PMFW's
|
| 4180 | * behavior about the maximum speed in RPM the fan can spin when ASIC
|
| 4181 | * temperature is not greater than target temperature. Setting via this
|
| 4182 | * interface will switch the fan control to auto mode implicitly.
|
| 4183 |
|
| 4184 | static ssize_t acoustic_target_threshold_show(struct kobject *kobj,
|
| 4185 | struct kobj_attribute *attr,
|
| 4186 | char *buf)
|
| 4187 | {
|
| 4188 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4189 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4190 |
|
| 4191 | return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf);
|
| 4192 | }
|
| 4193 |
|
| 4194 | static ssize_t acoustic_target_threshold_store(struct kobject *kobj,
|
| 4195 | struct kobj_attribute *attr,
|
| 4196 | const char *buf,
|
| 4197 | size_t count)
|
| 4198 | {
|
| 4199 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4200 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4201 |
|
| 4202 | return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
|
| 4203 | PP_OD_EDIT_ACOUSTIC_TARGET,
|
| 4204 | buf,
|
| 4205 | count);
|
| 4206 | }
|
| 4207 |
|
| 4208 | static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev)
|
| 4209 | {
|
| 4210 | umode_t umode = 0000;
|
| 4211 |
|
| 4212 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE)
|
| 4213 | umode |= S_IRUSR | S_IRGRP | S_IROTH;
|
| 4214 |
|
| 4215 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET)
|
| 4216 | umode |= S_IWUSR;
|
| 4217 |
|
| 4218 | return umode;
|
| 4219 | }
|
| 4220 |
|
| 4221 | |
| 4222 | * DOC: fan_target_temperature
|
| 4223 | *
|
| 4224 | * The amdgpu driver provides a sysfs API for checking and adjusting the
|
| 4225 | * target tempeature in Celsius degree for fan control.
|
| 4226 | *
|
| 4227 | * Reading back the file shows you the current setting and the permitted
|
| 4228 | * ranges if changable.
|
| 4229 | *
|
| 4230 | * Writing an integer to the file, change the setting accordingly.
|
| 4231 | *
|
| 4232 | * When you have finished the editing, write "c" (commit) to the file to commit
|
| 4233 | * your changes.
|
| 4234 | *
|
| 4235 | * If you want to reset to the default value, write "r" (reset) to the file to
|
| 4236 | * reset them
|
| 4237 | *
|
| 4238 | * This setting works under auto fan control mode only. It can co-exist with
|
| 4239 | * other settings which can work also under auto mode. Paring with the
|
| 4240 | * acoustic_target_rpm_threshold setting, they define the maximum speed in
|
| 4241 | * RPM the fan can spin when ASIC temperature is not greater than target
|
| 4242 | * temperature. Setting via this interface will switch the fan control to
|
| 4243 | * auto mode implicitly.
|
| 4244 |
|
| 4245 | static ssize_t fan_target_temperature_show(struct kobject *kobj,
|
| 4246 | struct kobj_attribute *attr,
|
| 4247 | char *buf)
|
| 4248 | {
|
| 4249 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4250 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4251 |
|
| 4252 | return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf);
|
| 4253 | }
|
| 4254 |
|
| 4255 | static ssize_t fan_target_temperature_store(struct kobject *kobj,
|
| 4256 | struct kobj_attribute *attr,
|
| 4257 | const char *buf,
|
| 4258 | size_t count)
|
| 4259 | {
|
| 4260 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4261 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4262 |
|
| 4263 | return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
|
| 4264 | PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
|
| 4265 | buf,
|
| 4266 | count);
|
| 4267 | }
|
| 4268 |
|
| 4269 | static umode_t fan_target_temperature_visible(struct amdgpu_device *adev)
|
| 4270 | {
|
| 4271 | umode_t umode = 0000;
|
| 4272 |
|
| 4273 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE)
|
| 4274 | umode |= S_IRUSR | S_IRGRP | S_IROTH;
|
| 4275 |
|
| 4276 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET)
|
| 4277 | umode |= S_IWUSR;
|
| 4278 |
|
| 4279 | return umode;
|
| 4280 | }
|
| 4281 |
|
| 4282 | |
| 4283 | * DOC: fan_minimum_pwm
|
| 4284 | *
|
| 4285 | * The amdgpu driver provides a sysfs API for checking and adjusting the
|
| 4286 | * minimum fan speed in PWM.
|
| 4287 | *
|
| 4288 | * Reading back the file shows you the current setting and the permitted
|
| 4289 | * ranges if changable.
|
| 4290 | *
|
| 4291 | * Writing an integer to the file, change the setting accordingly.
|
| 4292 | *
|
| 4293 | * When you have finished the editing, write "c" (commit) to the file to commit
|
| 4294 | * your changes.
|
| 4295 | *
|
| 4296 | * If you want to reset to the default value, write "r" (reset) to the file to
|
| 4297 | * reset them
|
| 4298 | *
|
| 4299 | * This setting works under auto fan control mode only. It can co-exist with
|
| 4300 | * other settings which can work also under auto mode. It adjusts the PMFW's
|
| 4301 | * behavior about the minimum fan speed in PWM the fan should spin. Setting
|
| 4302 | * via this interface will switch the fan control to auto mode implicitly.
|
| 4303 |
|
| 4304 | static ssize_t fan_minimum_pwm_show(struct kobject *kobj,
|
| 4305 | struct kobj_attribute *attr,
|
| 4306 | char *buf)
|
| 4307 | {
|
| 4308 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4309 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4310 |
|
| 4311 | return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf);
|
| 4312 | }
|
| 4313 |
|
| 4314 | static ssize_t fan_minimum_pwm_store(struct kobject *kobj,
|
| 4315 | struct kobj_attribute *attr,
|
| 4316 | const char *buf,
|
| 4317 | size_t count)
|
| 4318 | {
|
| 4319 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4320 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4321 |
|
| 4322 | return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
|
| 4323 | PP_OD_EDIT_FAN_MINIMUM_PWM,
|
| 4324 | buf,
|
| 4325 | count);
|
| 4326 | }
|
| 4327 |
|
| 4328 | static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev)
|
| 4329 | {
|
| 4330 | umode_t umode = 0000;
|
| 4331 |
|
| 4332 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE)
|
| 4333 | umode |= S_IRUSR | S_IRGRP | S_IROTH;
|
| 4334 |
|
| 4335 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET)
|
| 4336 | umode |= S_IWUSR;
|
| 4337 |
|
| 4338 | return umode;
|
| 4339 | }
|
| 4340 |
|
| 4341 | |
| 4342 | * DOC: fan_zero_rpm_enable
|
| 4343 | *
|
| 4344 | * The amdgpu driver provides a sysfs API for checking and adjusting the
|
| 4345 | * zero RPM feature.
|
| 4346 | *
|
| 4347 | * Reading back the file shows you the current setting and the permitted
|
| 4348 | * ranges if changable.
|
| 4349 | *
|
| 4350 | * Writing an integer to the file, change the setting accordingly.
|
| 4351 | *
|
| 4352 | * When you have finished the editing, write "c" (commit) to the file to commit
|
| 4353 | * your changes.
|
| 4354 | *
|
| 4355 | * If you want to reset to the default value, write "r" (reset) to the file to
|
| 4356 | * reset them.
|
| 4357 |
|
| 4358 | static ssize_t fan_zero_rpm_enable_show(struct kobject *kobj,
|
| 4359 | struct kobj_attribute *attr,
|
| 4360 | char *buf)
|
| 4361 | {
|
| 4362 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4363 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4364 |
|
| 4365 | return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_ZERO_RPM_ENABLE, buf);
|
| 4366 | }
|
| 4367 |
|
| 4368 | static ssize_t fan_zero_rpm_enable_store(struct kobject *kobj,
|
| 4369 | struct kobj_attribute *attr,
|
| 4370 | const char *buf,
|
| 4371 | size_t count)
|
| 4372 | {
|
| 4373 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4374 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4375 |
|
| 4376 | return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
|
| 4377 | PP_OD_EDIT_FAN_ZERO_RPM_ENABLE,
|
| 4378 | buf,
|
| 4379 | count);
|
| 4380 | }
|
| 4381 |
|
| 4382 | static umode_t fan_zero_rpm_enable_visible(struct amdgpu_device *adev)
|
| 4383 | {
|
| 4384 | umode_t umode = 0000;
|
| 4385 |
|
| 4386 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE)
|
| 4387 | umode |= S_IRUSR | S_IRGRP | S_IROTH;
|
| 4388 |
|
| 4389 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET)
|
| 4390 | umode |= S_IWUSR;
|
| 4391 |
|
| 4392 | return umode;
|
| 4393 | }
|
| 4394 |
|
| 4395 | |
| 4396 | * DOC: fan_zero_rpm_stop_temperature
|
| 4397 | *
|
| 4398 | * The amdgpu driver provides a sysfs API for checking and adjusting the
|
| 4399 | * zero RPM stop temperature feature.
|
| 4400 | *
|
| 4401 | * Reading back the file shows you the current setting and the permitted
|
| 4402 | * ranges if changable.
|
| 4403 | *
|
| 4404 | * Writing an integer to the file, change the setting accordingly.
|
| 4405 | *
|
| 4406 | * When you have finished the editing, write "c" (commit) to the file to commit
|
| 4407 | * your changes.
|
| 4408 | *
|
| 4409 | * If you want to reset to the default value, write "r" (reset) to the file to
|
| 4410 | * reset them.
|
| 4411 | *
|
| 4412 | * This setting works only if the Zero RPM setting is enabled. It adjusts the
|
| 4413 | * temperature below which the fan can stop.
|
| 4414 |
|
| 4415 | static ssize_t fan_zero_rpm_stop_temp_show(struct kobject *kobj,
|
| 4416 | struct kobj_attribute *attr,
|
| 4417 | char *buf)
|
| 4418 | {
|
| 4419 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4420 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4421 |
|
| 4422 | return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_ZERO_RPM_STOP_TEMP, buf);
|
| 4423 | }
|
| 4424 |
|
| 4425 | static ssize_t fan_zero_rpm_stop_temp_store(struct kobject *kobj,
|
| 4426 | struct kobj_attribute *attr,
|
| 4427 | const char *buf,
|
| 4428 | size_t count)
|
| 4429 | {
|
| 4430 | struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
|
| 4431 | struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
|
| 4432 |
|
| 4433 | return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
|
| 4434 | PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP,
|
| 4435 | buf,
|
| 4436 | count);
|
| 4437 | }
|
| 4438 |
|
| 4439 | static umode_t fan_zero_rpm_stop_temp_visible(struct amdgpu_device *adev)
|
| 4440 | {
|
| 4441 | umode_t umode = 0000;
|
| 4442 |
|
| 4443 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE)
|
| 4444 | umode |= S_IRUSR | S_IRGRP | S_IROTH;
|
| 4445 |
|
| 4446 | if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET)
|
| 4447 | umode |= S_IWUSR;
|
| 4448 |
|
| 4449 | return umode;
|
| 4450 | }
|
| 4451 |
|
| 4452 | static struct od_feature_set amdgpu_od_set = {
|
| 4453 | .containers = {
|
| 4454 | [0] = {
|
| 4455 | .name = "fan_ctrl",
|
| 4456 | .sub_feature = {
|
| 4457 | [0] = {
|
| 4458 | .name = "fan_curve",
|
| 4459 | .ops = {
|
| 4460 | .is_visible = fan_curve_visible,
|
| 4461 | .show = fan_curve_show,
|
| 4462 | .store = fan_curve_store,
|
| 4463 | },
|
| 4464 | },
|
| 4465 | [1] = {
|
| 4466 | .name = "acoustic_limit_rpm_threshold",
|
| 4467 | .ops = {
|
| 4468 | .is_visible = acoustic_limit_threshold_visible,
|
| 4469 | .show = acoustic_limit_threshold_show,
|
| 4470 | .store = acoustic_limit_threshold_store,
|
| 4471 | },
|
| 4472 | },
|
| 4473 | [2] = {
|
| 4474 | .name = "acoustic_target_rpm_threshold",
|
| 4475 | .ops = {
|
| 4476 | .is_visible = acoustic_target_threshold_visible,
|
| 4477 | .show = acoustic_target_threshold_show,
|
| 4478 | .store = acoustic_target_threshold_store,
|
| 4479 | },
|
| 4480 | },
|
| 4481 | [3] = {
|
| 4482 | .name = "fan_target_temperature",
|
| 4483 | .ops = {
|
| 4484 | .is_visible = fan_target_temperature_visible,
|
| 4485 | .show = fan_target_temperature_show,
|
| 4486 | .store = fan_target_temperature_store,
|
| 4487 | },
|
| 4488 | },
|
| 4489 | [4] = {
|
| 4490 | .name = "fan_minimum_pwm",
|
| 4491 | .ops = {
|
| 4492 | .is_visible = fan_minimum_pwm_visible,
|
| 4493 | .show = fan_minimum_pwm_show,
|
| 4494 | .store = fan_minimum_pwm_store,
|
| 4495 | },
|
| 4496 | },
|
| 4497 | [5] = {
|
| 4498 | .name = "fan_zero_rpm_enable",
|
| 4499 | .ops = {
|
| 4500 | .is_visible = fan_zero_rpm_enable_visible,
|
| 4501 | .show = fan_zero_rpm_enable_show,
|
| 4502 | .store = fan_zero_rpm_enable_store,
|
| 4503 | },
|
| 4504 | },
|
| 4505 | [6] = {
|
| 4506 | .name = "fan_zero_rpm_stop_temperature",
|
| 4507 | .ops = {
|
| 4508 | .is_visible = fan_zero_rpm_stop_temp_visible,
|
| 4509 | .show = fan_zero_rpm_stop_temp_show,
|
| 4510 | .store = fan_zero_rpm_stop_temp_store,
|
| 4511 | },
|
| 4512 | },
|
| 4513 | },
|
| 4514 | },
|
| 4515 | },
|
| 4516 | };
|
| 4517 |
|
| 4518 | static void od_kobj_release(struct kobject *kobj)
|
| 4519 | {
|
| 4520 | struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj);
|
| 4521 |
|
| 4522 | kfree(od_kobj);
|
| 4523 | }
|
| 4524 |
|
| 4525 | static const struct kobj_type od_ktype = {
|
| 4526 | .release = od_kobj_release,
|
| 4527 | .sysfs_ops = &kobj_sysfs_ops,
|
| 4528 | };
|
| 4529 |
|
| 4530 | static void amdgpu_od_set_fini(struct amdgpu_device *adev)
|
| 4531 | {
|
| 4532 | struct od_kobj *container, *container_next;
|
| 4533 | struct od_attribute *attribute, *attribute_next;
|
| 4534 |
|
| 4535 | if (list_empty(&adev->pm.od_kobj_list))
|
| 4536 | return;
|
| 4537 |
|
| 4538 | list_for_each_entry_safe(container, container_next,
|
| 4539 | &adev->pm.od_kobj_list, entry) {
|
| 4540 | list_del(&container->entry);
|
| 4541 |
|
| 4542 | list_for_each_entry_safe(attribute, attribute_next,
|
| 4543 | &container->attribute, entry) {
|
| 4544 | list_del(&attribute->entry);
|
| 4545 | sysfs_remove_file(&container->kobj,
|
| 4546 | &attribute->attribute.attr);
|
| 4547 | kfree(attribute);
|
| 4548 | }
|
| 4549 |
|
| 4550 | kobject_put(&container->kobj);
|
| 4551 | }
|
| 4552 | }
|
| 4553 |
|
| 4554 | static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev,
|
| 4555 | struct od_feature_ops *feature_ops)
|
| 4556 | {
|
| 4557 | umode_t mode;
|
| 4558 |
|
| 4559 | if (!feature_ops->is_visible)
|
| 4560 | return false;
|
| 4561 |
|
| 4562 | |
| 4563 | * If the feature has no user read and write mode set,
|
| 4564 | * we can assume the feature is actually not supported.(?)
|
| 4565 | * And the revelant sysfs interface should not be exposed.
|
| 4566 |
|
| 4567 | mode = feature_ops->is_visible(adev);
|
| 4568 | if (mode & (S_IRUSR | S_IWUSR))
|
| 4569 | return true;
|
| 4570 |
|
| 4571 | return false;
|
| 4572 | }
|
| 4573 |
|
| 4574 | static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev,
|
| 4575 | struct od_feature_container *container)
|
| 4576 | {
|
| 4577 | int i;
|
| 4578 |
|
| 4579 | |
| 4580 | * If there is no valid entry within the container, the container
|
| 4581 | * is recognized as a self contained container. And the valid entry
|
| 4582 | * here means it has a valid naming and it is visible/supported by
|
| 4583 | * the ASIC.
|
| 4584 |
|
| 4585 | for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) {
|
| 4586 | if (container->sub_feature[i].name &&
|
| 4587 | amdgpu_is_od_feature_supported(adev,
|
| 4588 | &container->sub_feature[i].ops))
|
| 4589 | return false;
|
| 4590 | }
|
| 4591 |
|
| 4592 | return true;
|
| 4593 | }
|
| 4594 |
|
| 4595 | static int amdgpu_od_set_init(struct amdgpu_device *adev)
|
| 4596 | {
|
| 4597 | struct od_kobj *top_set, *sub_set;
|
| 4598 | struct od_attribute *attribute;
|
| 4599 | struct od_feature_container *container;
|
| 4600 | struct od_feature_item *feature;
|
| 4601 | int i, j;
|
| 4602 | int ret;
|
| 4603 |
|
| 4604 |
|
| 4605 | top_set = kzalloc_obj(*top_set);
|
| 4606 | if (!top_set)
|
| 4607 | return -ENOMEM;
|
| 4608 | list_add(&top_set->entry, &adev->pm.od_kobj_list);
|
| 4609 |
|
| 4610 | ret = kobject_init_and_add(&top_set->kobj,
|
| 4611 | &od_ktype,
|
| 4612 | &adev->dev->kobj,
|
| 4613 | "%s",
|
| 4614 | "gpu_od");
|
| 4615 | if (ret)
|
| 4616 | goto err_out;
|
| 4617 | INIT_LIST_HEAD(&top_set->attribute);
|
| 4618 | top_set->priv = adev;
|
| 4619 |
|
| 4620 | for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) {
|
| 4621 | container = &amdgpu_od_set.containers[i];
|
| 4622 |
|
| 4623 | if (!container->name)
|
| 4624 | continue;
|
| 4625 |
|
| 4626 | |
| 4627 | * If there is valid entries within the container, the container
|
| 4628 | * will be presented as a sub directory and all its holding entries
|
| 4629 | * will be presented as plain files under it.
|
| 4630 | * While if there is no valid entry within the container, the container
|
| 4631 | * itself will be presented as a plain file under top `gpu_od` directory.
|
| 4632 |
|
| 4633 | if (amdgpu_od_is_self_contained(adev, container)) {
|
| 4634 | if (!amdgpu_is_od_feature_supported(adev,
|
| 4635 | &container->ops))
|
| 4636 | continue;
|
| 4637 |
|
| 4638 | |
| 4639 | * The container is presented as a plain file under top `gpu_od`
|
| 4640 | * directory.
|
| 4641 |
|
| 4642 | attribute = kzalloc_obj(*attribute);
|
| 4643 | if (!attribute) {
|
| 4644 | ret = -ENOMEM;
|
| 4645 | goto err_out;
|
| 4646 | }
|
| 4647 | list_add(&attribute->entry, &top_set->attribute);
|
| 4648 |
|
| 4649 | attribute->attribute.attr.mode =
|
| 4650 | container->ops.is_visible(adev);
|
| 4651 | attribute->attribute.attr.name = container->name;
|
| 4652 | attribute->attribute.show =
|
| 4653 | container->ops.show;
|
| 4654 | attribute->attribute.store =
|
| 4655 | container->ops.store;
|
| 4656 | ret = sysfs_create_file(&top_set->kobj,
|
| 4657 | &attribute->attribute.attr);
|
| 4658 | if (ret)
|
| 4659 | goto err_out;
|
| 4660 | } else {
|
| 4661 |
|
| 4662 | sub_set = kzalloc_obj(*sub_set);
|
| 4663 | if (!sub_set) {
|
| 4664 | ret = -ENOMEM;
|
| 4665 | goto err_out;
|
| 4666 | }
|
| 4667 | list_add(&sub_set->entry, &adev->pm.od_kobj_list);
|
| 4668 |
|
| 4669 | ret = kobject_init_and_add(&sub_set->kobj,
|
| 4670 | &od_ktype,
|
| 4671 | &top_set->kobj,
|
| 4672 | "%s",
|
| 4673 | container->name);
|
| 4674 | if (ret)
|
| 4675 | goto err_out;
|
| 4676 | INIT_LIST_HEAD(&sub_set->attribute);
|
| 4677 | sub_set->priv = adev;
|
| 4678 |
|
| 4679 | for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) {
|
| 4680 | feature = &container->sub_feature[j];
|
| 4681 | if (!feature->name)
|
| 4682 | continue;
|
| 4683 |
|
| 4684 | if (!amdgpu_is_od_feature_supported(adev,
|
| 4685 | &feature->ops))
|
| 4686 | continue;
|
| 4687 |
|
| 4688 | |
| 4689 | * With the container presented as a sub directory, the entry within
|
| 4690 | * it is presented as a plain file under the sub directory.
|
| 4691 |
|
| 4692 | attribute = kzalloc_obj(*attribute);
|
| 4693 | if (!attribute) {
|
| 4694 | ret = -ENOMEM;
|
| 4695 | goto err_out;
|
| 4696 | }
|
| 4697 | list_add(&attribute->entry, &sub_set->attribute);
|
| 4698 |
|
| 4699 | attribute->attribute.attr.mode =
|
| 4700 | feature->ops.is_visible(adev);
|
| 4701 | attribute->attribute.attr.name = feature->name;
|
| 4702 | attribute->attribute.show =
|
| 4703 | feature->ops.show;
|
| 4704 | attribute->attribute.store =
|
| 4705 | feature->ops.store;
|
| 4706 | ret = sysfs_create_file(&sub_set->kobj,
|
| 4707 | &attribute->attribute.attr);
|
| 4708 | if (ret)
|
| 4709 | goto err_out;
|
| 4710 | }
|
| 4711 | }
|
| 4712 | }
|
| 4713 |
|
| 4714 | |
| 4715 | * If gpu_od is the only member in the list, that means gpu_od is an
|
| 4716 | * empty directory, so remove it.
|
| 4717 |
|
| 4718 | if (list_is_singular(&adev->pm.od_kobj_list))
|
| 4719 | goto err_out;
|
| 4720 |
|
| 4721 | return 0;
|
| 4722 |
|
| 4723 | err_out:
|
| 4724 | amdgpu_od_set_fini(adev);
|
| 4725 |
|
| 4726 | return ret;
|
| 4727 | }
|
| 4728 |
|
| 4729 | int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
|
| 4730 | {
|
| 4731 | enum amdgpu_sriov_vf_mode mode;
|
| 4732 | uint32_t mask = 0;
|
| 4733 | uint32_t tmp;
|
| 4734 | int ret;
|
| 4735 |
|
| 4736 | if (adev->pm.sysfs_initialized)
|
| 4737 | return 0;
|
| 4738 |
|
| 4739 | INIT_LIST_HEAD(&adev->pm.pm_attr_list);
|
| 4740 |
|
| 4741 | if (adev->pm.dpm_enabled == 0)
|
| 4742 | return 0;
|
| 4743 |
|
| 4744 | mode = amdgpu_virt_get_sriov_vf_mode(adev);
|
| 4745 |
|
| 4746 |
|
| 4747 | if (mode != SRIOV_VF_MODE_MULTI_VF) {
|
| 4748 | adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
|
| 4749 | DRIVER_NAME, adev,
|
| 4750 | hwmon_groups);
|
| 4751 | if (IS_ERR(adev->pm.int_hwmon_dev)) {
|
| 4752 | ret = PTR_ERR(adev->pm.int_hwmon_dev);
|
| 4753 | dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret);
|
| 4754 | return ret;
|
| 4755 | }
|
| 4756 | }
|
| 4757 |
|
| 4758 | switch (mode) {
|
| 4759 | case SRIOV_VF_MODE_ONE_VF:
|
| 4760 | mask = ATTR_FLAG_ONEVF;
|
| 4761 | break;
|
| 4762 | case SRIOV_VF_MODE_MULTI_VF:
|
| 4763 | mask = 0;
|
| 4764 | break;
|
| 4765 | case SRIOV_VF_MODE_BARE_METAL:
|
| 4766 | default:
|
| 4767 | mask = ATTR_FLAG_MASK_ALL;
|
| 4768 | break;
|
| 4769 | }
|
| 4770 |
|
| 4771 | ret = amdgpu_device_attr_create_groups(adev,
|
| 4772 | amdgpu_device_attrs,
|
| 4773 | ARRAY_SIZE(amdgpu_device_attrs),
|
| 4774 | mask,
|
| 4775 | &adev->pm.pm_attr_list);
|
| 4776 | if (ret)
|
| 4777 | goto err_out0;
|
| 4778 |
|
| 4779 | if (amdgpu_dpm_is_overdrive_supported(adev)) {
|
| 4780 | ret = amdgpu_od_set_init(adev);
|
| 4781 | if (ret)
|
| 4782 | goto err_out1;
|
| 4783 | } else if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) {
|
| 4784 | dev_info(adev->dev, "overdrive feature is not supported\n");
|
| 4785 | }
|
| 4786 |
|
| 4787 | if (amdgpu_dpm_get_pm_policy_info(adev, PP_PM_POLICY_NONE, NULL) !=
|
| 4788 | -EOPNOTSUPP) {
|
| 4789 | ret = devm_device_add_group(adev->dev,
|
| 4790 | &amdgpu_pm_policy_attr_group);
|
| 4791 | if (ret)
|
| 4792 | goto err_out1;
|
| 4793 | }
|
| 4794 |
|
| 4795 | if (amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_GPUBOARD)) {
|
| 4796 | ret = devm_device_add_group(adev->dev,
|
| 4797 | &amdgpu_board_attr_group);
|
| 4798 | if (ret)
|
| 4799 | goto err_out1;
|
| 4800 | if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT,
|
| 4801 | (void *)&tmp) != -EOPNOTSUPP) {
|
| 4802 | sysfs_add_file_to_group(&adev->dev->kobj,
|
| 4803 | &dev_attr_cur_node_power_limit.attr,
|
| 4804 | amdgpu_board_attr_group.name);
|
| 4805 | sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_node_power.attr,
|
| 4806 | amdgpu_board_attr_group.name);
|
| 4807 | sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_global_ppt_resid.attr,
|
| 4808 | amdgpu_board_attr_group.name);
|
| 4809 | sysfs_add_file_to_group(&adev->dev->kobj,
|
| 4810 | &dev_attr_max_node_power_limit.attr,
|
| 4811 | amdgpu_board_attr_group.name);
|
| 4812 | sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_npm_status.attr,
|
| 4813 | amdgpu_board_attr_group.name);
|
| 4814 | }
|
| 4815 | if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_UBB_POWER_LIMIT,
|
| 4816 | (void *)&tmp) != -EOPNOTSUPP) {
|
| 4817 | sysfs_add_file_to_group(&adev->dev->kobj,
|
| 4818 | &dev_attr_baseboard_power_limit.attr,
|
| 4819 | amdgpu_board_attr_group.name);
|
| 4820 | sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_baseboard_power.attr,
|
| 4821 | amdgpu_board_attr_group.name);
|
| 4822 | }
|
| 4823 | }
|
| 4824 |
|
| 4825 | adev->pm.sysfs_initialized = true;
|
| 4826 |
|
| 4827 | return 0;
|
| 4828 |
|
| 4829 | err_out1:
|
| 4830 | amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
|
| 4831 | err_out0:
|
| 4832 | if (adev->pm.int_hwmon_dev)
|
| 4833 | hwmon_device_unregister(adev->pm.int_hwmon_dev);
|
| 4834 |
|
| 4835 | return ret;
|
| 4836 | }
|
| 4837 |
|
| 4838 | void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
|
| 4839 | {
|
| 4840 | amdgpu_od_set_fini(adev);
|
| 4841 |
|
| 4842 | if (adev->pm.int_hwmon_dev)
|
| 4843 | hwmon_device_unregister(adev->pm.int_hwmon_dev);
|
| 4844 |
|
| 4845 | amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
|
| 4846 | }
|
| 4847 |
|
| 4848 | |
| 4849 | * Debugfs info
|
| 4850 |
|
| 4851 | #if defined(CONFIG_DEBUG_FS)
|
| 4852 |
|
| 4853 | static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
|
| 4854 | struct amdgpu_device *adev)
|
| 4855 | {
|
| 4856 | uint16_t *p_val;
|
| 4857 | uint32_t size;
|
| 4858 | int i;
|
| 4859 | uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
|
| 4860 |
|
| 4861 | if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
|
| 4862 | p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
|
| 4863 | GFP_KERNEL);
|
| 4864 |
|
| 4865 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
|
| 4866 | (void *)p_val, &size)) {
|
| 4867 | for (i = 0; i < num_cpu_cores; i++)
|
| 4868 | seq_printf(m, "\t%u MHz (CPU%d)\n",
|
| 4869 | *(p_val + i), i);
|
| 4870 | }
|
| 4871 |
|
| 4872 | kfree(p_val);
|
| 4873 | }
|
| 4874 | }
|
| 4875 |
|
| 4876 | static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
|
| 4877 | {
|
| 4878 | uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
|
| 4879 | uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
|
| 4880 | uint64_t value64 = 0;
|
| 4881 | uint32_t value;
|
| 4882 | int size;
|
| 4883 |
|
| 4884 |
|
| 4885 | size = sizeof(value);
|
| 4886 | seq_printf(m, "GFX Clocks and Power:\n");
|
| 4887 |
|
| 4888 | amdgpu_debugfs_prints_cpu_info(m, adev);
|
| 4889 |
|
| 4890 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
|
| 4891 | seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
|
| 4892 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
|
| 4893 | seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
|
| 4894 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
|
| 4895 | seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
|
| 4896 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
|
| 4897 | seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
|
| 4898 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
|
| 4899 | seq_printf(m, "\t%u mV (VDDGFX)\n", value);
|
| 4900 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
|
| 4901 | seq_printf(m, "\t%u mV (VDDNB)\n", value);
|
| 4902 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&value, &size)) {
|
| 4903 | if (adev->flags & AMD_IS_APU)
|
| 4904 | seq_printf(m, "\t%u.%02u W (average SoC including CPU)\n",
|
| 4905 | (u32)(value / MILLIWATT_PER_WATT), (u32)(value % MILLIWATT_PER_WATT) / 10);
|
| 4906 | else
|
| 4907 | seq_printf(m, "\t%u.%02u W (average SoC)\n",
|
| 4908 | (u32)(value / MILLIWATT_PER_WATT), (u32)(value % MILLIWATT_PER_WATT) / 10);
|
| 4909 | }
|
| 4910 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&value, &size)) {
|
| 4911 | if (adev->flags & AMD_IS_APU)
|
| 4912 | seq_printf(m, "\t%u.%02u W (current SoC including CPU)\n",
|
| 4913 | (u32)(value / MILLIWATT_PER_WATT), (u32)(value % MILLIWATT_PER_WATT) / 10);
|
| 4914 | else
|
| 4915 | seq_printf(m, "\t%u.%02u W (current SoC)\n",
|
| 4916 | (u32)(value / MILLIWATT_PER_WATT), (u32)(value % MILLIWATT_PER_WATT) / 10);
|
| 4917 | }
|
| 4918 | seq_printf(m, "\n");
|
| 4919 |
|
| 4920 |
|
| 4921 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
|
| 4922 | seq_printf(m, "GPU Temperature: %u C\n", value/1000);
|
| 4923 |
|
| 4924 |
|
| 4925 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
|
| 4926 | seq_printf(m, "GPU Load: %u %%\n", value);
|
| 4927 |
|
| 4928 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
|
| 4929 | seq_printf(m, "MEM Load: %u %%\n", value);
|
| 4930 |
|
| 4931 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_LOAD, (void *)&value, &size))
|
| 4932 | seq_printf(m, "VCN Load: %u %%\n", value);
|
| 4933 |
|
| 4934 | seq_printf(m, "\n");
|
| 4935 |
|
| 4936 |
|
| 4937 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
|
| 4938 | seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
|
| 4939 |
|
| 4940 |
|
| 4941 | if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
|
| 4942 |
|
| 4943 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
|
| 4944 | if (!value) {
|
| 4945 | seq_printf(m, "VCN: Powered down\n");
|
| 4946 | } else {
|
| 4947 | seq_printf(m, "VCN: Powered up\n");
|
| 4948 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
|
| 4949 | seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
|
| 4950 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
|
| 4951 | seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
|
| 4952 | }
|
| 4953 | }
|
| 4954 | seq_printf(m, "\n");
|
| 4955 | } else {
|
| 4956 |
|
| 4957 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
|
| 4958 | if (!value) {
|
| 4959 | seq_printf(m, "UVD: Powered down\n");
|
| 4960 | } else {
|
| 4961 | seq_printf(m, "UVD: Powered up\n");
|
| 4962 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
|
| 4963 | seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
|
| 4964 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
|
| 4965 | seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
|
| 4966 | }
|
| 4967 | }
|
| 4968 | seq_printf(m, "\n");
|
| 4969 |
|
| 4970 |
|
| 4971 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
|
| 4972 | if (!value) {
|
| 4973 | seq_printf(m, "VCE: Powered down\n");
|
| 4974 | } else {
|
| 4975 | seq_printf(m, "VCE: Powered up\n");
|
| 4976 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
|
| 4977 | seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
|
| 4978 | }
|
| 4979 | }
|
| 4980 | }
|
| 4981 |
|
| 4982 | return 0;
|
| 4983 | }
|
| 4984 |
|
| 4985 | static const struct cg_flag_name clocks[] = {
|
| 4986 | {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
|
| 4987 | {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
|
| 4988 | {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
|
| 4989 | {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
|
| 4990 | {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
|
| 4991 | {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
|
| 4992 | {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
|
| 4993 | {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
|
| 4994 | {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
|
| 4995 | {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
|
| 4996 | {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
|
| 4997 | {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
|
| 4998 | {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
|
| 4999 | {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
|
| 5000 | {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
|
| 5001 | {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
|
| 5002 | {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
|
| 5003 | {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
|
| 5004 | {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
|
| 5005 | {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
|
| 5006 | {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
|
| 5007 | {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
|
| 5008 | {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
|
| 5009 | {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
|
| 5010 | {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
|
| 5011 | {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
|
| 5012 | {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
|
| 5013 | {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
|
| 5014 | {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
|
| 5015 | {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
|
| 5016 | {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
|
| 5017 | {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
|
| 5018 | {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
|
| 5019 | {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
|
| 5020 | {0, NULL},
|
| 5021 | };
|
| 5022 |
|
| 5023 | static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
|
| 5024 | {
|
| 5025 | int i;
|
| 5026 |
|
| 5027 | for (i = 0; clocks[i].flag; i++)
|
| 5028 | seq_printf(m, "\t%s: %s\n", clocks[i].name,
|
| 5029 | (flags & clocks[i].flag) ? "On" : "Off");
|
| 5030 | }
|
| 5031 |
|
| 5032 | static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
|
| 5033 | {
|
| 5034 | struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
|
| 5035 | u64 flags = 0;
|
| 5036 | int r;
|
| 5037 |
|
| 5038 | r = amdgpu_pm_get_access(adev);
|
| 5039 | if (r < 0)
|
| 5040 | return r;
|
| 5041 |
|
| 5042 | if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
|
| 5043 | r = amdgpu_debugfs_pm_info_pp(m, adev);
|
| 5044 | if (r)
|
| 5045 | goto out;
|
| 5046 | }
|
| 5047 |
|
| 5048 | amdgpu_device_ip_get_clockgating_state(adev, &flags);
|
| 5049 |
|
| 5050 | seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
|
| 5051 | amdgpu_parse_cg_state(m, flags);
|
| 5052 | seq_printf(m, "\n");
|
| 5053 |
|
| 5054 | out:
|
| 5055 | amdgpu_pm_put_access(adev);
|
| 5056 |
|
| 5057 | return r;
|
| 5058 | }
|
| 5059 |
|
| 5060 | DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
|
| 5061 |
|
| 5062 | |
| 5063 | * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
|
| 5064 | *
|
| 5065 | * Reads debug memory region allocated to PMFW
|
| 5066 |
|
| 5067 | static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
|
| 5068 | size_t size, loff_t *pos)
|
| 5069 | {
|
| 5070 | struct amdgpu_device *adev = file_inode(f)->i_private;
|
| 5071 | size_t smu_prv_buf_size;
|
| 5072 | void *smu_prv_buf;
|
| 5073 | int ret = 0;
|
| 5074 |
|
| 5075 | ret = amdgpu_pm_dev_state_check(adev, true);
|
| 5076 | if (ret)
|
| 5077 | return ret;
|
| 5078 |
|
| 5079 | ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
|
| 5080 | if (ret)
|
| 5081 | return ret;
|
| 5082 |
|
| 5083 | if (!smu_prv_buf || !smu_prv_buf_size)
|
| 5084 | return -EINVAL;
|
| 5085 |
|
| 5086 | return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
|
| 5087 | smu_prv_buf_size);
|
| 5088 | }
|
| 5089 |
|
| 5090 | static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
|
| 5091 | .owner = THIS_MODULE,
|
| 5092 | .open = simple_open,
|
| 5093 | .read = amdgpu_pm_prv_buffer_read,
|
| 5094 | .llseek = default_llseek,
|
| 5095 | };
|
| 5096 |
|
| 5097 | #endif
|
| 5098 |
|
| 5099 | void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
|
| 5100 | {
|
| 5101 | #if defined(CONFIG_DEBUG_FS)
|
| 5102 | struct drm_minor *minor = adev_to_drm(adev)->primary;
|
| 5103 | struct dentry *root = minor->debugfs_root;
|
| 5104 |
|
| 5105 | if (!adev->pm.dpm_enabled)
|
| 5106 | return;
|
| 5107 |
|
| 5108 | debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
|
| 5109 | &amdgpu_debugfs_pm_info_fops);
|
| 5110 |
|
| 5111 | if (adev->pm.smu_prv_buffer_size > 0)
|
| 5112 | debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
|
| 5113 | adev,
|
| 5114 | &amdgpu_debugfs_pm_prv_buffer_fops,
|
| 5115 | adev->pm.smu_prv_buffer_size);
|
| 5116 |
|
| 5117 | amdgpu_dpm_stb_debug_fs_init(adev);
|
| 5118 | #endif
|
| 5119 | }
|