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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <[email protected]>
5 */
6
7#include "drm/drm_drv.h"
8
9#include "msm_gpu.h"
10#include "msm_gem.h"
11#include "msm_mmu.h"
12#include "msm_fence.h"
13#include "msm_gpu_trace.h"
14//#include "adreno/adreno_gpu.h"
15
16#include <linux/string_helpers.h>
17#include <linux/devcoredump.h>
18#include <linux/sched/task.h>
19#include <linux/sched/mm.h>
20#include <linux/utsname.h>
21
22/*
23 * Power Management:
24 */
25
26static int enable_pwrrail(struct msm_gpu *gpu)
27{
28 struct drm_device *dev = gpu->dev;
29 int ret = 0;
30
31 if (gpu->gpu_reg) {
32 ret = regulator_enable(gpu->gpu_reg);
33 if (ret) {
34 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
35 return ret;
36 }
37 }
38
39 if (gpu->gpu_cx) {
40 ret = regulator_enable(gpu->gpu_cx);
41 if (ret) {
42 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
43 return ret;
44 }
45 }
46
47 return 0;
48}
49
50static int disable_pwrrail(struct msm_gpu *gpu)
51{
52 if (gpu->gpu_cx)
53 regulator_disable(gpu->gpu_cx);
54 if (gpu->gpu_reg)
55 regulator_disable(gpu->gpu_reg);
56 return 0;
57}
58
59static int enable_clk(struct msm_gpu *gpu)
60{
61 if (gpu->core_clk && gpu->fast_rate)
62 dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate);
63
64 /* Set the RBBM timer rate to 19.2Mhz */
65 if (gpu->rbbmtimer_clk)
66 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
67
68 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
69}
70
71static int disable_clk(struct msm_gpu *gpu)
72{
73 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
74
75 /*
76 * Set the clock to a deliberately low rate. On older targets the clock
77 * speed had to be non zero to avoid problems. On newer targets this
78 * will be rounded down to zero anyway so it all works out.
79 */
80 if (gpu->core_clk)
81 dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000);
82
83 if (gpu->rbbmtimer_clk)
84 clk_set_rate(gpu->rbbmtimer_clk, 0);
85
86 return 0;
87}
88
89static int enable_axi(struct msm_gpu *gpu)
90{
91 return clk_prepare_enable(gpu->ebi1_clk);
92}
93
94static int disable_axi(struct msm_gpu *gpu)
95{
96 clk_disable_unprepare(gpu->ebi1_clk);
97 return 0;
98}
99
100int msm_gpu_pm_resume(struct msm_gpu *gpu)
101{
102 int ret;
103
104 DBG("%s", gpu->name);
105 trace_msm_gpu_resume(0);
106
107 ret = enable_pwrrail(gpu);
108 if (ret)
109 return ret;
110
111 ret = enable_clk(gpu);
112 if (ret)
113 return ret;
114
115 ret = enable_axi(gpu);
116 if (ret)
117 return ret;
118
119 msm_devfreq_resume(gpu);
120
121 gpu->needs_hw_init = true;
122
123 return 0;
124}
125
126int msm_gpu_pm_suspend(struct msm_gpu *gpu)
127{
128 int ret;
129
130 DBG("%s", gpu->name);
131 trace_msm_gpu_suspend(0);
132
133 msm_devfreq_suspend(gpu);
134
135 ret = disable_axi(gpu);
136 if (ret)
137 return ret;
138
139 ret = disable_clk(gpu);
140 if (ret)
141 return ret;
142
143 ret = disable_pwrrail(gpu);
144 if (ret)
145 return ret;
146
147 gpu->suspend_count++;
148
149 return 0;
150}
151
152void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_context *ctx,
153 struct drm_printer *p)
154{
155 drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns);
156 drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles);
157 drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate);
158}
159
160int msm_gpu_hw_init(struct msm_gpu *gpu)
161{
162 int ret;
163
164 WARN_ON(!mutex_is_locked(&gpu->lock));
165
166 if (!gpu->needs_hw_init)
167 return 0;
168
169 disable_irq(gpu->irq);
170 ret = gpu->funcs->hw_init(gpu);
171 if (!ret)
172 gpu->needs_hw_init = false;
173 enable_irq(gpu->irq);
174
175 return ret;
176}
177
178#ifdef CONFIG_DEV_COREDUMP
179static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
180 size_t count, void *data, size_t datalen)
181{
182 struct msm_gpu *gpu = data;
183 struct drm_print_iterator iter;
184 struct drm_printer p;
185 struct msm_gpu_state *state;
186
187 state = msm_gpu_crashstate_get(gpu);
188 if (!state)
189 return 0;
190
191 iter.data = buffer;
192 iter.offset = 0;
193 iter.start = offset;
194 iter.remain = count;
195
196 p = drm_coredump_printer(&iter);
197
198 drm_printf(&p, "---\n");
199 drm_printf(&p, "kernel: %s\n", init_utsname()->release);
200 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
201 drm_printf(&p, "time: %ptSp\n", &state->time);
202 if (state->comm)
203 drm_printf(&p, "comm: %s\n", state->comm);
204 if (state->cmd)
205 drm_printf(&p, "cmdline: %s\n", state->cmd);
206
207 gpu->funcs->show(gpu, state, &p);
208
209 msm_gpu_crashstate_put(gpu);
210
211 return count - iter.remain;
212}
213
214static void msm_gpu_devcoredump_free(void *data)
215{
216 struct msm_gpu *gpu = data;
217
218 msm_gpu_crashstate_put(gpu);
219}
220
221static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
222 struct drm_gem_object *obj, u64 iova,
223 bool full, size_t offset, size_t size)
224{
225 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
226 struct msm_gem_object *msm_obj = to_msm_bo(obj);
227
228 /* Don't record write only objects */
229 state_bo->size = size;
230 state_bo->flags = msm_obj->flags;
231 state_bo->iova = iova;
232
233 BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(msm_obj->name));
234
235 memcpy(state_bo->name, msm_obj->name, sizeof(state_bo->name));
236
237 if (full) {
238 void *ptr;
239
240 state_bo->data = kvmalloc(size, GFP_KERNEL);
241 if (!state_bo->data)
242 goto out;
243
244 ptr = msm_gem_get_vaddr_active(obj);
245 if (IS_ERR(ptr)) {
246 kvfree(state_bo->data);
247 state_bo->data = NULL;
248 goto out;
249 }
250
251 memcpy(state_bo->data, ptr + offset, size);
252 msm_gem_put_vaddr_locked(obj);
253 }
254out:
255 state->nr_bos++;
256}
257
258static void crashstate_get_bos(struct msm_gpu_state *state, struct msm_gem_submit *submit)
259{
260 extern bool rd_full;
261
262 if (msm_context_is_vmbind(submit->queue->ctx)) {
263 struct drm_exec exec;
264 struct drm_gpuva *vma;
265 unsigned cnt = 0;
266
267 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
268 drm_exec_until_all_locked(&exec) {
269 cnt = 0;
270
271 drm_exec_lock_obj(&exec, drm_gpuvm_resv_obj(submit->vm));
272 drm_exec_retry_on_contention(&exec);
273
274 drm_gpuvm_for_each_va (vma, submit->vm) {
275 if (!vma->gem.obj)
276 continue;
277
278 cnt++;
279 drm_exec_lock_obj(&exec, vma->gem.obj);
280 drm_exec_retry_on_contention(&exec);
281 }
282
283 }
284
285 drm_gpuvm_for_each_va (vma, submit->vm)
286 cnt++;
287
288 state->bos = kcalloc(cnt, sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
289
290 if (state->bos)
291 drm_gpuvm_for_each_va(vma, submit->vm) {
292 bool dump = rd_full || (vma->flags & MSM_VMA_DUMP);
293
294 /* Skip MAP_NULL/PRR VMAs: */
295 if (!vma->gem.obj)
296 continue;
297
298 msm_gpu_crashstate_get_bo(state, vma->gem.obj, vma->va.addr,
299 dump, vma->gem.offset, vma->va.range);
300 }
301
302 drm_exec_fini(&exec);
303 } else {
304 state->bos = kcalloc(submit->nr_bos,
305 sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
306
307 for (int i = 0; state->bos && i < submit->nr_bos; i++) {
308 struct drm_gem_object *obj = submit->bos[i].obj;
309 bool dump = rd_full || (submit->bos[i].flags & MSM_SUBMIT_BO_DUMP);
310
311 msm_gem_lock(obj);
312 msm_gpu_crashstate_get_bo(state, obj, submit->bos[i].iova,
313 dump, 0, obj->size);
314 msm_gem_unlock(obj);
315 }
316 }
317}
318
319static void crashstate_get_vm_logs(struct msm_gpu_state *state, struct msm_gem_vm *vm)
320{
321 uint32_t vm_log_len = (1 << vm->log_shift);
322 uint32_t vm_log_mask = vm_log_len - 1;
323 int first;
324
325 /* Bail if no log, or empty log: */
326 if (!vm->log || !vm->log[0].op)
327 return;
328
329 mutex_lock(&vm->mmu_lock);
330
331 /*
332 * log_idx is the next entry to overwrite, meaning it is the oldest, or
333 * first, entry (other than the special case handled below where the
334 * log hasn't wrapped around yet)
335 */
336 first = vm->log_idx;
337
338 if (!vm->log[first].op) {
339 /*
340 * If the next log entry has not been written yet, then only
341 * entries 0 to idx-1 are valid (ie. we haven't wrapped around
342 * yet)
343 */
344 state->nr_vm_logs = MAX(0, first - 1);
345 first = 0;
346 } else {
347 state->nr_vm_logs = vm_log_len;
348 }
349
350 state->vm_logs = kmalloc_objs(vm->log[0], state->nr_vm_logs);
351 if (!state->vm_logs) {
352 state->nr_vm_logs = 0;
353 }
354
355 for (int i = 0; i < state->nr_vm_logs; i++) {
356 int idx = (i + first) & vm_log_mask;
357
358 state->vm_logs[i] = vm->log[idx];
359 }
360
361 mutex_unlock(&vm->mmu_lock);
362}
363
364static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
365 struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info,
366 char *comm, char *cmd)
367{
368 struct msm_gpu_state *state;
369
370 /* Check if the target supports capturing crash state */
371 if (!gpu->funcs->gpu_state_get)
372 return;
373
374 /* Only save one crash state at a time */
375 if (gpu->crashstate)
376 return;
377
378 state = gpu->funcs->gpu_state_get(gpu);
379 if (IS_ERR_OR_NULL(state))
380 return;
381
382 /* Fill in the additional crash state information */
383 state->comm = kstrdup(comm, GFP_KERNEL);
384 state->cmd = kstrdup(cmd, GFP_KERNEL);
385 if (fault_info)
386 state->fault_info = *fault_info;
387
388 if (submit && state->fault_info.ttbr0) {
389 struct msm_gpu_fault_info *info = &state->fault_info;
390 struct msm_mmu *mmu = to_msm_vm(submit->vm)->mmu;
391
392 msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0,
393 &info->asid);
394 msm_iommu_pagetable_walk(mmu, info->iova, info->ptes);
395 }
396
397 if (submit) {
398 crashstate_get_vm_logs(state, to_msm_vm(submit->vm));
399 crashstate_get_bos(state, submit);
400 }
401
402 /* Set the active crash state to be dumped on failure */
403 gpu->crashstate = state;
404
405 dev_coredumpm(&gpu->pdev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
406 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
407}
408#else
409static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
410 struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info,
411 char *comm, char *cmd)
412{
413}
414#endif
415
416/*
417 * Hangcheck detection for locked gpu:
418 */
419
420static struct msm_gem_submit *
421find_submit(struct msm_ringbuffer *ring, uint32_t fence)
422{
423 struct msm_gem_submit *submit;
424 unsigned long flags;
425
426 spin_lock_irqsave(&ring->submit_lock, flags);
427 list_for_each_entry(submit, &ring->submits, node) {
428 if (submit->seqno == fence) {
429 spin_unlock_irqrestore(&ring->submit_lock, flags);
430 return submit;
431 }
432 }
433 spin_unlock_irqrestore(&ring->submit_lock, flags);
434
435 return NULL;
436}
437
438static void retire_submits(struct msm_gpu *gpu);
439
440static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd)
441{
442 struct msm_context *ctx = submit->queue->ctx;
443 struct task_struct *task;
444
445 WARN_ON(!mutex_is_locked(&submit->gpu->lock));
446
447 /* Note that kstrdup will return NULL if argument is NULL: */
448 *comm = kstrdup(ctx->comm, GFP_KERNEL);
449 *cmd = kstrdup(ctx->cmdline, GFP_KERNEL);
450
451 task = get_pid_task(submit->pid, PIDTYPE_PID);
452 if (!task)
453 return;
454
455 if (!*comm)
456 *comm = kstrdup(task->comm, GFP_KERNEL);
457
458 if (!*cmd)
459 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
460
461 put_task_struct(task);
462}
463
464static void recover_worker(struct kthread_work *work)
465{
466 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
467 struct drm_device *dev = gpu->dev;
468 struct msm_drm_private *priv = dev->dev_private;
469 struct msm_gem_submit *submit;
470 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
471 char *comm = NULL, *cmd = NULL;
472 unsigned int noreclaim_flag;
473 struct task_struct *task;
474 int i;
475
476 mutex_lock(&gpu->lock);
477
478 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
479
480 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
481
482 /*
483 * If the submit retired while we were waiting for the worker to run,
484 * or waiting to acquire the gpu lock, then nothing more to do.
485 */
486 if (!submit)
487 goto out_unlock;
488
489 /* Increment the fault counts */
490 submit->queue->faults++;
491
492 task = get_pid_task(submit->pid, PIDTYPE_PID);
493 if (!task)
494 gpu->global_faults++;
495 else {
496 struct msm_gem_vm *vm = to_msm_vm(submit->vm);
497
498 vm->faults++;
499
500 /*
501 * If userspace has opted-in to VM_BIND (and therefore userspace
502 * management of the VM), faults mark the VM as unusable. This
503 * matches vulkan expectations (vulkan is the main target for
504 * VM_BIND).
505 */
506 if (!vm->managed)
507 msm_gem_vm_unusable(submit->vm);
508
509 put_task_struct(task);
510 }
511
512 noreclaim_flag = memalloc_noreclaim_save();
513
514 get_comm_cmdline(submit, &comm, &cmd);
515
516 if (comm && cmd) {
517 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
518 gpu->name, comm, cmd);
519
520 msm_rd_dump_submit(priv->hangrd, submit,
521 "offending task: %s (%s)", comm, cmd);
522 } else {
523 DRM_DEV_ERROR(dev->dev, "%s: offending task: unknown\n", gpu->name);
524
525 msm_rd_dump_submit(priv->hangrd, submit, NULL);
526 }
527
528 /* Record the crash state */
529 pm_runtime_get_sync(&gpu->pdev->dev);
530 msm_gpu_crashstate_capture(gpu, submit, NULL, comm, cmd);
531
532 memalloc_noreclaim_restore(noreclaim_flag);
533
534 kfree(cmd);
535 kfree(comm);
536
537 /*
538 * Update all the rings with the latest and greatest fence.. this
539 * needs to happen after msm_rd_dump_submit() to ensure that the
540 * bo's referenced by the offending submit are still around.
541 */
542 for (i = 0; i < gpu->nr_rings; i++) {
543 struct msm_ringbuffer *ring = gpu->rb[i];
544
545 uint32_t fence = ring->memptrs->fence;
546
547 /*
548 * For the current (faulting?) ring/submit advance the fence by
549 * one more to clear the faulting submit
550 */
551 if (ring == cur_ring)
552 ring->memptrs->fence = ++fence;
553
554 msm_update_fence(ring->fctx, fence);
555 }
556
557 priv->disable_err_irq = false;
558
559 gpu->funcs->recover(gpu);
560
561 /* retire completed submits, plus the one that hung: */
562 retire_submits(gpu);
563
564 /*
565 * Replay all remaining submits starting with highest priority
566 * ring
567 */
568 for (i = 0; i < gpu->nr_rings; i++) {
569 struct msm_ringbuffer *ring = gpu->rb[i];
570 unsigned long flags;
571
572 spin_lock_irqsave(&ring->submit_lock, flags);
573 list_for_each_entry(submit, &ring->submits, node) {
574 /*
575 * If the submit uses an unusable vm make sure
576 * we don't actually run it
577 */
578 if (to_msm_vm(submit->vm)->unusable)
579 submit->nr_cmds = 0;
580 gpu->funcs->submit(gpu, submit);
581 }
582 spin_unlock_irqrestore(&ring->submit_lock, flags);
583 }
584
585 pm_runtime_put(&gpu->pdev->dev);
586
587out_unlock:
588 mutex_unlock(&gpu->lock);
589
590 msm_gpu_retire(gpu);
591}
592
593void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info)
594{
595 struct msm_gem_submit *submit;
596 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
597 char *comm = NULL, *cmd = NULL;
598 unsigned int noreclaim_flag;
599
600 mutex_lock(&gpu->lock);
601
602 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
603 if (submit && submit->fault_dumped)
604 goto resume_smmu;
605
606 noreclaim_flag = memalloc_noreclaim_save();
607
608 if (submit) {
609 get_comm_cmdline(submit, &comm, &cmd);
610
611 /*
612 * When we get GPU iova faults, we can get 1000s of them,
613 * but we really only want to log the first one.
614 */
615 submit->fault_dumped = true;
616 }
617
618 /* Record the crash state */
619 pm_runtime_get_sync(&gpu->pdev->dev);
620 msm_gpu_crashstate_capture(gpu, submit, fault_info, comm, cmd);
621 pm_runtime_put_sync(&gpu->pdev->dev);
622
623 memalloc_noreclaim_restore(noreclaim_flag);
624
625 kfree(cmd);
626 kfree(comm);
627
628resume_smmu:
629 mutex_unlock(&gpu->lock);
630}
631
632static void hangcheck_timer_reset(struct msm_gpu *gpu)
633{
634 struct msm_drm_private *priv = gpu->dev->dev_private;
635 mod_timer(&gpu->hangcheck_timer,
636 round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period)));
637}
638
639static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
640{
641 if (ring->hangcheck_progress_retries >= DRM_MSM_HANGCHECK_PROGRESS_RETRIES)
642 return false;
643
644 if (!gpu->funcs->progress)
645 return false;
646
647 if (!gpu->funcs->progress(gpu, ring))
648 return false;
649
650 ring->hangcheck_progress_retries++;
651 return true;
652}
653
654static void hangcheck_handler(struct timer_list *t)
655{
656 struct msm_gpu *gpu = timer_container_of(gpu, t, hangcheck_timer);
657 struct drm_device *dev = gpu->dev;
658 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
659 uint32_t fence = ring->memptrs->fence;
660
661 if (fence != ring->hangcheck_fence) {
662 /* some progress has been made.. ya! */
663 ring->hangcheck_fence = fence;
664 ring->hangcheck_progress_retries = 0;
665 } else if (fence_before(fence, ring->fctx->last_fence) &&
666 !made_progress(gpu, ring)) {
667 /* no progress and not done.. hung! */
668 ring->hangcheck_fence = fence;
669 ring->hangcheck_progress_retries = 0;
670 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
671 gpu->name, ring->id);
672 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n",
673 gpu->name, fence);
674 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n",
675 gpu->name, ring->fctx->last_fence);
676
677 kthread_queue_work(gpu->worker, &gpu->recover_work);
678 }
679
680 /* if still more pending work, reset the hangcheck timer: */
681 if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence))
682 hangcheck_timer_reset(gpu);
683
684 /* workaround for missing irq: */
685 msm_gpu_retire(gpu);
686}
687
688/*
689 * Cmdstream submission/retirement:
690 */
691
692static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
693 struct msm_gem_submit *submit)
694{
695 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
696 volatile struct msm_gpu_submit_stats *stats;
697 u64 elapsed, clock = 0, cycles;
698 unsigned long flags;
699
700 stats = &ring->memptrs->stats[index];
701 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
702 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
703 do_div(elapsed, 192);
704
705 cycles = stats->cpcycles_end - stats->cpcycles_start;
706
707 /* Calculate the clock frequency from the number of CP cycles */
708 if (elapsed) {
709 clock = cycles * 1000;
710 do_div(clock, elapsed);
711 }
712
713 submit->queue->ctx->elapsed_ns += elapsed;
714 submit->queue->ctx->cycles += cycles;
715
716 trace_msm_gpu_submit_retired(submit, elapsed, clock,
717 stats->alwayson_start, stats->alwayson_end);
718
719 msm_submit_retire(submit);
720
721 pm_runtime_mark_last_busy(&gpu->pdev->dev);
722
723 spin_lock_irqsave(&ring->submit_lock, flags);
724 list_del(&submit->node);
725 spin_unlock_irqrestore(&ring->submit_lock, flags);
726
727 /* Update devfreq on transition from active->idle: */
728 mutex_lock(&gpu->active_lock);
729 gpu->active_submits--;
730 WARN_ON(gpu->active_submits < 0);
731 if (!gpu->active_submits) {
732 msm_devfreq_idle(gpu);
733 pm_runtime_put_autosuspend(&gpu->pdev->dev);
734 }
735
736 mutex_unlock(&gpu->active_lock);
737
738 msm_gem_submit_put(submit);
739}
740
741static void retire_submits(struct msm_gpu *gpu)
742{
743 int i;
744
745 /* Retire the commits starting with highest priority */
746 for (i = 0; i < gpu->nr_rings; i++) {
747 struct msm_ringbuffer *ring = gpu->rb[i];
748
749 while (true) {
750 struct msm_gem_submit *submit = NULL;
751 unsigned long flags;
752
753 spin_lock_irqsave(&ring->submit_lock, flags);
754 submit = list_first_entry_or_null(&ring->submits,
755 struct msm_gem_submit, node);
756 spin_unlock_irqrestore(&ring->submit_lock, flags);
757
758 /*
759 * If no submit, we are done. If submit->fence hasn't
760 * been signalled, then later submits are not signalled
761 * either, so we are also done.
762 */
763 if (submit && dma_fence_is_signaled(submit->hw_fence)) {
764 retire_submit(gpu, ring, submit);
765 } else {
766 break;
767 }
768 }
769 }
770
771 wake_up_all(&gpu->retire_event);
772}
773
774static void retire_worker(struct kthread_work *work)
775{
776 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
777
778 retire_submits(gpu);
779}
780
781/* call from irq handler to schedule work to retire bo's */
782void msm_gpu_retire(struct msm_gpu *gpu)
783{
784 int i;
785
786 for (i = 0; i < gpu->nr_rings; i++)
787 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence);
788
789 kthread_queue_work(gpu->worker, &gpu->retire_work);
790}
791
792/* add bo's to gpu's ring, and kick gpu: */
793void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
794{
795 struct msm_ringbuffer *ring = submit->ring;
796 unsigned long flags;
797
798 WARN_ON(!mutex_is_locked(&gpu->lock));
799
800 pm_runtime_get_sync(&gpu->pdev->dev);
801
802 msm_gpu_hw_init(gpu);
803
804 submit->seqno = submit->hw_fence->seqno;
805
806 /*
807 * ring->submits holds a ref to the submit, to deal with the case
808 * that a submit completes before msm_ioctl_gem_submit() returns.
809 */
810 msm_gem_submit_get(submit);
811
812 spin_lock_irqsave(&ring->submit_lock, flags);
813 list_add_tail(&submit->node, &ring->submits);
814 spin_unlock_irqrestore(&ring->submit_lock, flags);
815
816 /* Update devfreq on transition from idle->active: */
817 mutex_lock(&gpu->active_lock);
818 if (!gpu->active_submits) {
819 pm_runtime_get(&gpu->pdev->dev);
820 msm_devfreq_active(gpu);
821 }
822 gpu->active_submits++;
823 mutex_unlock(&gpu->active_lock);
824
825 gpu->funcs->submit(gpu, submit);
826 submit->ring->cur_ctx_seqno = submit->queue->ctx->seqno;
827
828 pm_runtime_put(&gpu->pdev->dev);
829 hangcheck_timer_reset(gpu);
830}
831
832/*
833 * Init/Cleanup:
834 */
835
836static irqreturn_t irq_handler(int irq, void *data)
837{
838 struct msm_gpu *gpu = data;
839 return gpu->funcs->irq(gpu);
840}
841
842static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
843{
844 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
845
846 if (ret < 1) {
847 gpu->nr_clocks = 0;
848 return ret;
849 }
850
851 gpu->nr_clocks = ret;
852
853 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
854 gpu->nr_clocks, "core");
855
856 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
857 gpu->nr_clocks, "rbbmtimer");
858
859 return 0;
860}
861
862/* Return a new address space for a msm_drm_private instance */
863struct drm_gpuvm *
864msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task,
865 bool kernel_managed)
866{
867 struct drm_gpuvm *vm = NULL;
868
869 if (!gpu)
870 return NULL;
871
872 /*
873 * If the target doesn't support private address spaces then return
874 * the global one
875 */
876 if (gpu->funcs->create_private_vm) {
877 vm = gpu->funcs->create_private_vm(gpu, kernel_managed);
878 if (!IS_ERR(vm))
879 to_msm_vm(vm)->pid = get_pid(task_pid(task));
880 }
881
882 if (IS_ERR_OR_NULL(vm) && kernel_managed)
883 vm = drm_gpuvm_get(gpu->vm);
884
885 return vm;
886}
887
888int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
889 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
890 const char *name, struct msm_gpu_config *config)
891{
892 struct msm_drm_private *priv = drm->dev_private;
893 int i, ret, nr_rings = config->nr_rings;
894 void *memptrs;
895 uint64_t memptrs_iova;
896
897 gpu->dev = drm;
898 gpu->funcs = funcs;
899 gpu->name = name;
900
901 gpu->worker = kthread_run_worker(0, "gpu-worker");
902 if (IS_ERR(gpu->worker)) {
903 ret = PTR_ERR(gpu->worker);
904 gpu->worker = NULL;
905 goto fail;
906 }
907
908 sched_set_fifo_low(gpu->worker->task);
909
910 mutex_init(&gpu->active_lock);
911 mutex_init(&gpu->lock);
912 init_waitqueue_head(&gpu->retire_event);
913 kthread_init_work(&gpu->retire_work, retire_worker);
914 kthread_init_work(&gpu->recover_work, recover_worker);
915
916 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
917
918 /*
919 * If progress detection is supported, halve the hangcheck timer
920 * duration, as it takes two iterations of the hangcheck handler
921 * to detect a hang.
922 */
923 if (funcs->progress)
924 priv->hangcheck_period /= 2;
925
926 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
927
928 /* Map registers: */
929 gpu->mmio = msm_ioremap(pdev, config->ioname);
930 if (IS_ERR(gpu->mmio)) {
931 ret = PTR_ERR(gpu->mmio);
932 goto fail;
933 }
934
935 /* Get Interrupt: */
936 gpu->irq = platform_get_irq(pdev, 0);
937 if (gpu->irq < 0) {
938 ret = gpu->irq;
939 goto fail;
940 }
941
942 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
943 IRQF_TRIGGER_HIGH, "gpu-irq", gpu);
944 if (ret) {
945 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
946 goto fail;
947 }
948
949 ret = get_clocks(pdev, gpu);
950 if (ret)
951 goto fail;
952
953 gpu->ebi1_clk = msm_clk_get(pdev, "bus");
954 DBG("ebi1_clk: %p", gpu->ebi1_clk);
955 if (IS_ERR(gpu->ebi1_clk))
956 gpu->ebi1_clk = NULL;
957
958 /* Acquire regulators: */
959 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
960 DBG("gpu_reg: %p", gpu->gpu_reg);
961 if (IS_ERR(gpu->gpu_reg))
962 gpu->gpu_reg = NULL;
963
964 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
965 DBG("gpu_cx: %p", gpu->gpu_cx);
966 if (IS_ERR(gpu->gpu_cx))
967 gpu->gpu_cx = NULL;
968
969 platform_set_drvdata(pdev, &gpu->adreno_smmu);
970
971 msm_devfreq_init(gpu);
972
973 gpu->vm = gpu->funcs->create_vm(gpu, pdev);
974 if (IS_ERR(gpu->vm)) {
975 ret = PTR_ERR(gpu->vm);
976 goto fail;
977 }
978
979 memptrs = msm_gem_kernel_new(drm,
980 sizeof(struct msm_rbmemptrs) * nr_rings,
981 check_apriv(gpu, MSM_BO_WC), gpu->vm, &gpu->memptrs_bo,
982 &memptrs_iova);
983
984 if (IS_ERR(memptrs)) {
985 ret = PTR_ERR(memptrs);
986 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
987 goto fail;
988 }
989
990 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
991
992 if (nr_rings > ARRAY_SIZE(gpu->rb)) {
993 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
994 ARRAY_SIZE(gpu->rb));
995 nr_rings = ARRAY_SIZE(gpu->rb);
996 }
997
998 /* Create ringbuffer(s): */
999 for (i = 0; i < nr_rings; i++) {
1000 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
1001
1002 if (IS_ERR(gpu->rb[i])) {
1003 ret = PTR_ERR(gpu->rb[i]);
1004 DRM_DEV_ERROR(drm->dev,
1005 "could not create ringbuffer %d: %d\n", i, ret);
1006 goto fail;
1007 }
1008
1009 memptrs += sizeof(struct msm_rbmemptrs);
1010 memptrs_iova += sizeof(struct msm_rbmemptrs);
1011 }
1012
1013 gpu->nr_rings = nr_rings;
1014
1015 refcount_set(&gpu->sysprof_active, 1);
1016
1017 mutex_init(&gpu->perfcntr_lock);
1018
1019 if (gpu->num_perfcntr_groups > 0) {
1020 gpu->perfcntrs = msm_perfcntr_init(gpu);
1021 if (IS_ERR(gpu->perfcntrs)) {
1022 ret = PTR_ERR(gpu->perfcntrs);
1023 gpu->perfcntrs = NULL;
1024 goto fail;
1025 }
1026 }
1027
1028 return 0;
1029
1030fail:
1031 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1032 msm_ringbuffer_destroy(gpu->rb[i]);
1033 gpu->rb[i] = NULL;
1034 }
1035
1036 msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm);
1037
1038 platform_set_drvdata(pdev, NULL);
1039 return ret;
1040}
1041
1042void msm_gpu_cleanup(struct msm_gpu *gpu)
1043{
1044 int i;
1045
1046 DBG("%s", gpu->name);
1047
1048 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1049 msm_ringbuffer_destroy(gpu->rb[i]);
1050 gpu->rb[i] = NULL;
1051 }
1052
1053 msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm);
1054
1055 if (!IS_ERR_OR_NULL(gpu->vm)) {
1056 struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu;
1057 mmu->funcs->detach(mmu);
1058 drm_gpuvm_put(gpu->vm);
1059 }
1060
1061 if (gpu->worker) {
1062 kthread_destroy_worker(gpu->worker);
1063 }
1064
1065 msm_devfreq_cleanup(gpu);
1066 msm_perfcntr_cleanup(gpu);
1067
1068 platform_set_drvdata(gpu->pdev, NULL);
1069}