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1776 lines · 44.4 KiB

1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/debugfs.h>
8#include <linux/delay.h>
9#include <linux/host1x.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/regulator/consumer.h>
16#include <linux/reset.h>
17#include <linux/tegra-mipi-cal.h>
18
19#include <video/mipi_display.h>
20
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_debugfs.h>
23#include <drm/drm_file.h>
24#include <drm/drm_mipi_dsi.h>
25#include <drm/drm_panel.h>
26#include <drm/drm_print.h>
27#include <drm/drm_simple_kms_helper.h>
28
29#include "dc.h"
30#include "drm.h"
31#include "dsi.h"
32#include "mipi-phy.h"
33#include "trace.h"
34
35struct tegra_dsi_state {
36 struct drm_connector_state base;
37
38 struct mipi_dphy_timing timing;
39 unsigned long period;
40
41 unsigned int vrefresh;
42 unsigned int lanes;
43 unsigned long pclk;
44 unsigned long bclk;
45
46 enum tegra_dsi_format format;
47 unsigned int mul;
48 unsigned int div;
49};
50
51static inline struct tegra_dsi_state *
52to_dsi_state(struct drm_connector_state *state)
53{
54 return container_of(state, struct tegra_dsi_state, base);
55}
56
57struct tegra_dsi_config {
58 bool has_multiple_pad_controls;
59 bool has_mux_parent_clk;
60};
61
62struct tegra_dsi {
63 struct host1x_client client;
64 struct tegra_output output;
65 struct device *dev;
66
67 void __iomem *regs;
68
69 struct reset_control *rst;
70 struct clk *clk_parent;
71 struct clk *clk_lp;
72 struct clk *clk;
73
74 struct drm_info_list *debugfs_files;
75
76 unsigned long flags;
77 enum mipi_dsi_pixel_format format;
78 unsigned int lanes;
79
80 struct tegra_mipi_device *mipi;
81 struct mipi_dsi_host host;
82
83 struct regulator *vdd;
84
85 unsigned int video_fifo_depth;
86 unsigned int host_fifo_depth;
87
88 /* for ganged-mode support */
89 struct tegra_dsi *master;
90 struct tegra_dsi *slave;
91
92 const struct tegra_dsi_config *config;
93};
94
95static inline struct tegra_dsi *
96host1x_client_to_dsi(struct host1x_client *client)
97{
98 return container_of(client, struct tegra_dsi, client);
99}
100
101static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
102{
103 return container_of(host, struct tegra_dsi, host);
104}
105
106static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
107{
108 return container_of(output, struct tegra_dsi, output);
109}
110
111static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
112{
113 return to_dsi_state(dsi->output.connector.state);
114}
115
116static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
117{
118 u32 value = readl(dsi->regs + (offset << 2));
119
120 trace_dsi_readl(dsi->dev, offset, value);
121
122 return value;
123}
124
125static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
126 unsigned int offset)
127{
128 trace_dsi_writel(dsi->dev, offset, value);
129 writel(value, dsi->regs + (offset << 2));
130}
131
132#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
133
134static const struct debugfs_reg32 tegra_dsi_regs[] = {
135 DEBUGFS_REG32(DSI_INCR_SYNCPT),
136 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
137 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
138 DEBUGFS_REG32(DSI_CTXSW),
139 DEBUGFS_REG32(DSI_RD_DATA),
140 DEBUGFS_REG32(DSI_WR_DATA),
141 DEBUGFS_REG32(DSI_POWER_CONTROL),
142 DEBUGFS_REG32(DSI_INT_ENABLE),
143 DEBUGFS_REG32(DSI_INT_STATUS),
144 DEBUGFS_REG32(DSI_INT_MASK),
145 DEBUGFS_REG32(DSI_HOST_CONTROL),
146 DEBUGFS_REG32(DSI_CONTROL),
147 DEBUGFS_REG32(DSI_SOL_DELAY),
148 DEBUGFS_REG32(DSI_MAX_THRESHOLD),
149 DEBUGFS_REG32(DSI_TRIGGER),
150 DEBUGFS_REG32(DSI_TX_CRC),
151 DEBUGFS_REG32(DSI_STATUS),
152 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
153 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
154 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
155 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
156 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
157 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
158 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
159 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
160 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
161 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
162 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
163 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
164 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
165 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
166 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
167 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
168 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
169 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
170 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
171 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
172 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
173 DEBUGFS_REG32(DSI_DCS_CMDS),
174 DEBUGFS_REG32(DSI_PKT_LEN_0_1),
175 DEBUGFS_REG32(DSI_PKT_LEN_2_3),
176 DEBUGFS_REG32(DSI_PKT_LEN_4_5),
177 DEBUGFS_REG32(DSI_PKT_LEN_6_7),
178 DEBUGFS_REG32(DSI_PHY_TIMING_0),
179 DEBUGFS_REG32(DSI_PHY_TIMING_1),
180 DEBUGFS_REG32(DSI_PHY_TIMING_2),
181 DEBUGFS_REG32(DSI_BTA_TIMING),
182 DEBUGFS_REG32(DSI_TIMEOUT_0),
183 DEBUGFS_REG32(DSI_TIMEOUT_1),
184 DEBUGFS_REG32(DSI_TO_TALLY),
185 DEBUGFS_REG32(DSI_PAD_CONTROL_0),
186 DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
187 DEBUGFS_REG32(DSI_PAD_CD_STATUS),
188 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
189 DEBUGFS_REG32(DSI_PAD_CONTROL_1),
190 DEBUGFS_REG32(DSI_PAD_CONTROL_2),
191 DEBUGFS_REG32(DSI_PAD_CONTROL_3),
192 DEBUGFS_REG32(DSI_PAD_CONTROL_4),
193 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
194 DEBUGFS_REG32(DSI_GANGED_MODE_START),
195 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
196 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
197 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
198 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
199 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
200 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
201 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
202 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
203 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
204 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
205 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
206};
207
208static int tegra_dsi_show_regs(struct seq_file *s, void *data)
209{
210 struct drm_info_node *node = s->private;
211 struct tegra_dsi *dsi = node->info_ent->data;
212 struct drm_crtc *crtc = dsi->output.encoder.crtc;
213 struct drm_device *drm = node->minor->dev;
214 unsigned int i;
215 int err = 0;
216
217 drm_modeset_lock_all(drm);
218
219 if (!crtc || !crtc->state->active) {
220 err = -EBUSY;
221 goto unlock;
222 }
223
224 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
225 unsigned int offset = tegra_dsi_regs[i].offset;
226
227 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
228 offset, tegra_dsi_readl(dsi, offset));
229 }
230
231unlock:
232 drm_modeset_unlock_all(drm);
233 return err;
234}
235
236static struct drm_info_list debugfs_files[] = {
237 { "regs", tegra_dsi_show_regs, 0, NULL },
238};
239
240static int tegra_dsi_late_register(struct drm_connector *connector)
241{
242 struct tegra_output *output = connector_to_output(connector);
243 unsigned int i, count = ARRAY_SIZE(debugfs_files);
244 struct drm_minor *minor = connector->dev->primary;
245 struct dentry *root = connector->debugfs_entry;
246 struct tegra_dsi *dsi = to_dsi(output);
247
248 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
249 GFP_KERNEL);
250 if (!dsi->debugfs_files)
251 return -ENOMEM;
252
253 for (i = 0; i < count; i++)
254 dsi->debugfs_files[i].data = dsi;
255
256 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
257
258 return 0;
259}
260
261static void tegra_dsi_early_unregister(struct drm_connector *connector)
262{
263 struct tegra_output *output = connector_to_output(connector);
264 unsigned int count = ARRAY_SIZE(debugfs_files);
265 struct tegra_dsi *dsi = to_dsi(output);
266
267 drm_debugfs_remove_files(dsi->debugfs_files, count,
268 connector->debugfs_entry,
269 connector->dev->primary);
270 kfree(dsi->debugfs_files);
271 dsi->debugfs_files = NULL;
272}
273
274#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
275#define PKT_LEN0(len) (((len) & 0x07) << 0)
276#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
277#define PKT_LEN1(len) (((len) & 0x07) << 10)
278#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
279#define PKT_LEN2(len) (((len) & 0x07) << 20)
280
281#define PKT_LP (1 << 30)
282#define NUM_PKT_SEQ 12
283
284/*
285 * non-burst mode with sync pulses
286 */
287static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
288 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
289 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
290 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
291 PKT_LP,
292 [ 1] = 0,
293 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
294 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
295 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
296 PKT_LP,
297 [ 3] = 0,
298 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
299 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
300 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
301 PKT_LP,
302 [ 5] = 0,
303 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
304 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
305 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
306 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
307 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
308 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
309 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
310 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
311 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
312 PKT_LP,
313 [ 9] = 0,
314 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
315 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
316 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
317 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
318 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
319 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
320};
321
322/*
323 * non-burst mode with sync events
324 */
325static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
326 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
327 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
328 PKT_LP,
329 [ 1] = 0,
330 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
331 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
332 PKT_LP,
333 [ 3] = 0,
334 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
335 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
336 PKT_LP,
337 [ 5] = 0,
338 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
339 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
340 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
341 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
342 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
343 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
344 PKT_LP,
345 [ 9] = 0,
346 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
347 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
348 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
349 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
350};
351
352static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
353 [ 0] = 0,
354 [ 1] = 0,
355 [ 2] = 0,
356 [ 3] = 0,
357 [ 4] = 0,
358 [ 5] = 0,
359 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
360 [ 7] = 0,
361 [ 8] = 0,
362 [ 9] = 0,
363 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
364 [11] = 0,
365};
366
367static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
368 unsigned long period,
369 const struct mipi_dphy_timing *timing)
370{
371 u32 value;
372
373 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
374 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
375 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
376 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
377 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
378
379 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
380 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
381 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
382 DSI_TIMING_FIELD(timing->lpx, period, 1);
383 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
384
385 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
386 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
387 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
388 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
389
390 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
391 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
392 DSI_TIMING_FIELD(timing->tago, period, 1);
393 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
394
395 if (dsi->slave)
396 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
397}
398
399static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
400 unsigned int *mulp, unsigned int *divp)
401{
402 switch (format) {
403 case MIPI_DSI_FMT_RGB666_PACKED:
404 case MIPI_DSI_FMT_RGB888:
405 *mulp = 3;
406 *divp = 1;
407 break;
408
409 case MIPI_DSI_FMT_RGB565:
410 *mulp = 2;
411 *divp = 1;
412 break;
413
414 case MIPI_DSI_FMT_RGB666:
415 *mulp = 9;
416 *divp = 4;
417 break;
418
419 default:
420 return -EINVAL;
421 }
422
423 return 0;
424}
425
426static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
427 enum tegra_dsi_format *fmt)
428{
429 switch (format) {
430 case MIPI_DSI_FMT_RGB888:
431 *fmt = TEGRA_DSI_FORMAT_24P;
432 break;
433
434 case MIPI_DSI_FMT_RGB666:
435 *fmt = TEGRA_DSI_FORMAT_18NP;
436 break;
437
438 case MIPI_DSI_FMT_RGB666_PACKED:
439 *fmt = TEGRA_DSI_FORMAT_18P;
440 break;
441
442 case MIPI_DSI_FMT_RGB565:
443 *fmt = TEGRA_DSI_FORMAT_16P;
444 break;
445
446 default:
447 return -EINVAL;
448 }
449
450 return 0;
451}
452
453static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
454 unsigned int size)
455{
456 u32 value;
457
458 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
459 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
460
461 value = DSI_GANGED_MODE_CONTROL_ENABLE;
462 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
463}
464
465static void tegra_dsi_enable(struct tegra_dsi *dsi)
466{
467 u32 value;
468
469 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
470 value |= DSI_POWER_CONTROL_ENABLE;
471 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
472
473 if (dsi->slave)
474 tegra_dsi_enable(dsi->slave);
475}
476
477static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
478{
479 if (dsi->master)
480 return dsi->master->lanes + dsi->lanes;
481
482 if (dsi->slave)
483 return dsi->lanes + dsi->slave->lanes;
484
485 return dsi->lanes;
486}
487
488static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
489 const struct drm_display_mode *mode)
490{
491 unsigned int hact, hsw, hbp, hfp, i, mul, div;
492 struct tegra_dsi_state *state;
493 const u32 *pkt_seq;
494 u32 value;
495
496 /* XXX: pass in state into this function? */
497 if (dsi->master)
498 state = tegra_dsi_get_state(dsi->master);
499 else
500 state = tegra_dsi_get_state(dsi);
501
502 mul = state->mul;
503 div = state->div;
504
505 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
506 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
507 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
508 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
509 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
510 pkt_seq = pkt_seq_video_non_burst_sync_events;
511 } else {
512 DRM_DEBUG_KMS("Command mode\n");
513 pkt_seq = pkt_seq_command_mode;
514 }
515
516 value = DSI_CONTROL_CHANNEL(0) |
517 DSI_CONTROL_FORMAT(state->format) |
518 DSI_CONTROL_LANES(dsi->lanes - 1) |
519 DSI_CONTROL_SOURCE(pipe);
520 tegra_dsi_writel(dsi, value, DSI_CONTROL);
521
522 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
523
524 value = DSI_HOST_CONTROL_HS;
525 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
526
527 value = tegra_dsi_readl(dsi, DSI_CONTROL);
528
529 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
530 value |= DSI_CONTROL_HS_CLK_CTRL;
531
532 value &= ~DSI_CONTROL_TX_TRIG(3);
533
534 /* enable DCS commands for command mode */
535 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
536 value &= ~DSI_CONTROL_DCS_ENABLE;
537 else
538 value |= DSI_CONTROL_DCS_ENABLE;
539
540 value |= DSI_CONTROL_VIDEO_ENABLE;
541 value &= ~DSI_CONTROL_HOST_ENABLE;
542 tegra_dsi_writel(dsi, value, DSI_CONTROL);
543
544 for (i = 0; i < NUM_PKT_SEQ; i++)
545 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
546
547 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
548 /* horizontal active pixels */
549 hact = mode->hdisplay * mul / div;
550
551 /* horizontal sync width */
552 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
553
554 /* horizontal back porch */
555 hbp = (mode->htotal - mode->hsync_end) * mul / div;
556
557 /* horizontal front porch */
558 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
559
560 if (dsi->master || dsi->slave) {
561 hact /= 2;
562 hsw /= 2;
563 hbp /= 2;
564 hfp /= 2;
565 }
566
567 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
568 hbp += hsw;
569
570 /* subtract packet overhead */
571 hsw -= 10;
572 hbp -= 14;
573 hfp -= 8;
574
575 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
576 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
577 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
578 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
579 } else {
580 u16 bytes;
581
582 if (dsi->master || dsi->slave) {
583 /*
584 * For ganged mode, assume symmetric left-right mode.
585 */
586 bytes = 1 + (mode->hdisplay / 2) * mul / div;
587 } else {
588 /* 1 byte (DCS command) + pixel data */
589 bytes = 1 + mode->hdisplay * mul / div;
590 }
591
592 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
593 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
594 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
595 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
596
597 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
598 MIPI_DCS_WRITE_MEMORY_CONTINUE;
599 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
600 }
601
602 /* set SOL delay */
603 if (dsi->master || dsi->slave) {
604 unsigned long delay, bclk, bclk_ganged;
605 unsigned int lanes = state->lanes;
606
607 /* SOL to valid, valid to FIFO and FIFO write delay */
608 delay = 4 + 4 + 2;
609 delay = DIV_ROUND_UP(delay * mul, div * lanes);
610 /* FIFO read delay */
611 delay = delay + 6;
612
613 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
614 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
615 value = bclk - bclk_ganged + delay + 20;
616 } else {
617 value = 8 * mul / div;
618 }
619
620 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
621
622 if (dsi->slave) {
623 tegra_dsi_configure(dsi->slave, pipe, mode);
624
625 /*
626 * TODO: Support modes other than symmetrical left-right
627 * split.
628 */
629 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
630 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
631 mode->hdisplay / 2);
632 }
633}
634
635static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
636{
637 u32 value;
638
639 timeout = jiffies + msecs_to_jiffies(timeout);
640
641 while (time_before(jiffies, timeout)) {
642 value = tegra_dsi_readl(dsi, DSI_STATUS);
643 if (value & DSI_STATUS_IDLE)
644 return 0;
645
646 usleep_range(1000, 2000);
647 }
648
649 return -ETIMEDOUT;
650}
651
652static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
653{
654 u32 value;
655
656 value = tegra_dsi_readl(dsi, DSI_CONTROL);
657 value &= ~DSI_CONTROL_VIDEO_ENABLE;
658 tegra_dsi_writel(dsi, value, DSI_CONTROL);
659
660 if (dsi->slave)
661 tegra_dsi_video_disable(dsi->slave);
662}
663
664static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
665{
666 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
667 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
668 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
669}
670
671static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
672{
673 u32 value;
674
675 if (dsi->config->has_multiple_pad_controls) {
676 /*
677 * XXX Is this still needed? The module reset is deasserted right
678 * before this function is called.
679 */
680 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
681 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
684 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
685
686 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
687 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
688
689 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
690 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
691 DSI_PAD_OUT_CLK(0x0);
692 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
693
694 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
695 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
696 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
697 } else {
698 value = DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) |
699 DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) |
700 DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) |
701 DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0);
702 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
703 }
704
705 return 0;
706}
707
708static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
709{
710 int err;
711
712 /* start calibration */
713 tegra_dsi_pad_enable(dsi);
714
715 err = tegra_mipi_start_calibration(dsi->mipi);
716 if (err < 0)
717 return err;
718
719 return tegra_mipi_finish_calibration(dsi->mipi);
720}
721
722static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
723 unsigned int vrefresh)
724{
725 unsigned int timeout;
726 u32 value;
727
728 /* one frame high-speed transmission timeout */
729 timeout = (bclk / vrefresh) / 512;
730 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
731 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
732
733 /* 2 ms peripheral timeout for panel */
734 timeout = 2 * bclk / 512 * 1000;
735 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
736 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
737
738 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
739 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
740
741 if (dsi->slave)
742 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
743}
744
745static void tegra_dsi_disable(struct tegra_dsi *dsi)
746{
747 u32 value;
748
749 if (dsi->slave) {
750 tegra_dsi_ganged_disable(dsi->slave);
751 tegra_dsi_ganged_disable(dsi);
752 }
753
754 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
755 value &= ~DSI_POWER_CONTROL_ENABLE;
756 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
757
758 if (dsi->slave)
759 tegra_dsi_disable(dsi->slave);
760
761 usleep_range(5000, 10000);
762}
763
764static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
765{
766 u32 value;
767
768 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
769 value &= ~DSI_POWER_CONTROL_ENABLE;
770 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
771
772 usleep_range(300, 1000);
773
774 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
775 value |= DSI_POWER_CONTROL_ENABLE;
776 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
777
778 usleep_range(300, 1000);
779
780 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
781 if (value)
782 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
783
784 if (dsi->slave)
785 tegra_dsi_soft_reset(dsi->slave);
786}
787
788static void tegra_dsi_connector_reset(struct drm_connector *connector)
789{
790 struct tegra_dsi_state *state = kzalloc_obj(*state);
791
792 if (!state)
793 return;
794
795 if (connector->state) {
796 __drm_atomic_helper_connector_destroy_state(connector->state);
797 kfree(connector->state);
798 }
799
800 __drm_atomic_helper_connector_reset(connector, &state->base);
801}
802
803static struct drm_connector_state *
804tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
805{
806 struct tegra_dsi_state *state = to_dsi_state(connector->state);
807 struct tegra_dsi_state *copy;
808
809 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
810 if (!copy)
811 return NULL;
812
813 __drm_atomic_helper_connector_duplicate_state(connector,
814 &copy->base);
815
816 return &copy->base;
817}
818
819static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
820 .reset = tegra_dsi_connector_reset,
821 .detect = tegra_output_connector_detect,
822 .fill_modes = drm_helper_probe_single_connector_modes,
823 .destroy = tegra_output_connector_destroy,
824 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
825 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
826 .late_register = tegra_dsi_late_register,
827 .early_unregister = tegra_dsi_early_unregister,
828};
829
830static enum drm_mode_status
831tegra_dsi_connector_mode_valid(struct drm_connector *connector,
832 const struct drm_display_mode *mode)
833{
834 return MODE_OK;
835}
836
837static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
838 .get_modes = tegra_output_connector_get_modes,
839 .mode_valid = tegra_dsi_connector_mode_valid,
840};
841
842static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
843{
844 int err;
845
846 if (dsi->slave)
847 tegra_dsi_unprepare(dsi->slave);
848
849 err = tegra_mipi_disable(dsi->mipi);
850 if (err < 0)
851 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
852 err);
853
854 err = host1x_client_suspend(&dsi->client);
855 if (err < 0)
856 dev_err(dsi->dev, "failed to suspend: %d\n", err);
857}
858
859static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
860{
861 struct tegra_output *output = encoder_to_output(encoder);
862 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
863 struct tegra_dsi *dsi = to_dsi(output);
864 u32 value;
865 int err;
866
867 if (output->panel)
868 drm_panel_disable(output->panel);
869
870 tegra_dsi_video_disable(dsi);
871
872 /*
873 * The following accesses registers of the display controller, so make
874 * sure it's only executed when the output is attached to one.
875 */
876 if (dc) {
877 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
878 value &= ~DSI_ENABLE;
879 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
880
881 tegra_dc_commit(dc);
882 }
883
884 err = tegra_dsi_wait_idle(dsi, 100);
885 if (err < 0)
886 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
887
888 tegra_dsi_soft_reset(dsi);
889
890 if (output->panel)
891 drm_panel_unprepare(output->panel);
892
893 tegra_dsi_disable(dsi);
894
895 tegra_dsi_unprepare(dsi);
896}
897
898static int tegra_dsi_prepare(struct tegra_dsi *dsi)
899{
900 int err;
901
902 err = host1x_client_resume(&dsi->client);
903 if (err < 0) {
904 dev_err(dsi->dev, "failed to resume: %d\n", err);
905 return err;
906 }
907
908 err = tegra_mipi_enable(dsi->mipi);
909 if (err < 0)
910 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
911 err);
912
913 err = tegra_dsi_pad_calibrate(dsi);
914 if (err < 0)
915 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
916
917 if (dsi->slave)
918 tegra_dsi_prepare(dsi->slave);
919
920 return 0;
921}
922
923static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
924{
925 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
926 struct tegra_output *output = encoder_to_output(encoder);
927 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
928 struct tegra_dsi *dsi = to_dsi(output);
929 struct tegra_dsi_state *state;
930 u32 value;
931 int err;
932
933 err = tegra_dsi_prepare(dsi);
934 if (err < 0) {
935 dev_err(dsi->dev, "failed to prepare: %d\n", err);
936 return;
937 }
938
939 /* If the bootloader enabled DSI it needs to be disabled
940 * in order for the panel initialization commands to be
941 * properly sent.
942 */
943 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
944
945 if (value & DSI_POWER_CONTROL_ENABLE)
946 tegra_dsi_disable(dsi);
947
948 state = tegra_dsi_get_state(dsi);
949
950 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
951
952 /*
953 * The D-PHY timing fields are expressed in byte-clock cycles, so
954 * multiply the period by 8.
955 */
956 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
957
958 if (output->panel)
959 drm_panel_prepare(output->panel);
960
961 tegra_dsi_configure(dsi, dc->pipe, mode);
962
963 /* enable display controller */
964 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
965 value |= DSI_ENABLE;
966 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
967
968 tegra_dc_commit(dc);
969
970 /* enable DSI controller */
971 tegra_dsi_enable(dsi);
972
973 if (output->panel)
974 drm_panel_enable(output->panel);
975}
976
977static int
978tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
979 struct drm_crtc_state *crtc_state,
980 struct drm_connector_state *conn_state)
981{
982 struct tegra_output *output = encoder_to_output(encoder);
983 struct tegra_dsi_state *state = to_dsi_state(conn_state);
984 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
985 struct tegra_dsi *dsi = to_dsi(output);
986 unsigned int scdiv;
987 unsigned long plld;
988 int err;
989
990 state->pclk = crtc_state->mode.clock * 1000;
991
992 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
993 if (err < 0)
994 return err;
995
996 state->lanes = tegra_dsi_get_lanes(dsi);
997
998 err = tegra_dsi_get_format(dsi->format, &state->format);
999 if (err < 0)
1000 return err;
1001
1002 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
1003
1004 /* compute byte clock */
1005 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
1006
1007 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
1008 state->lanes);
1009 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
1010 state->vrefresh);
1011 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
1012
1013 /*
1014 * Compute bit clock and round up to the next MHz.
1015 */
1016 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
1017 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
1018
1019 err = mipi_dphy_timing_get_default(&state->timing, state->period);
1020 if (err < 0)
1021 return err;
1022
1023 err = mipi_dphy_timing_validate(&state->timing, state->period);
1024 if (err < 0) {
1025 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
1026 return err;
1027 }
1028
1029 /*
1030 * We divide the frequency by two here, but we make up for that by
1031 * setting the shift clock divider (further below) to half of the
1032 * correct value.
1033 */
1034 plld /= 2;
1035
1036 /*
1037 * Derive pixel clock from bit clock using the shift clock divider.
1038 * Note that this is only half of what we would expect, but we need
1039 * that to make up for the fact that we divided the bit clock by a
1040 * factor of two above.
1041 *
1042 * It's not clear exactly why this is necessary, but the display is
1043 * not working properly otherwise. Perhaps the PLLs cannot generate
1044 * frequencies sufficiently high.
1045 */
1046 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1047
1048 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
1049 plld, scdiv);
1050 if (err < 0) {
1051 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1052 return err;
1053 }
1054
1055 return err;
1056}
1057
1058static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1059 .disable = tegra_dsi_encoder_disable,
1060 .enable = tegra_dsi_encoder_enable,
1061 .atomic_check = tegra_dsi_encoder_atomic_check,
1062};
1063
1064static int tegra_dsi_init(struct host1x_client *client)
1065{
1066 struct drm_device *drm = dev_get_drvdata(client->host);
1067 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1068 int err;
1069
1070 /* Gangsters must not register their own outputs. */
1071 if (!dsi->master) {
1072 dsi->output.dev = client->dev;
1073
1074 drm_connector_init(drm, &dsi->output.connector,
1075 &tegra_dsi_connector_funcs,
1076 DRM_MODE_CONNECTOR_DSI);
1077 drm_connector_helper_add(&dsi->output.connector,
1078 &tegra_dsi_connector_helper_funcs);
1079 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1080
1081 drm_simple_encoder_init(drm, &dsi->output.encoder,
1082 DRM_MODE_ENCODER_DSI);
1083 drm_encoder_helper_add(&dsi->output.encoder,
1084 &tegra_dsi_encoder_helper_funcs);
1085
1086 drm_connector_attach_encoder(&dsi->output.connector,
1087 &dsi->output.encoder);
1088 drm_connector_register(&dsi->output.connector);
1089
1090 err = tegra_output_init(drm, &dsi->output);
1091 if (err < 0)
1092 dev_err(dsi->dev, "failed to initialize output: %d\n",
1093 err);
1094
1095 dsi->output.encoder.possible_crtcs = 0x3;
1096 }
1097
1098 return 0;
1099}
1100
1101static int tegra_dsi_exit(struct host1x_client *client)
1102{
1103 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1104
1105 tegra_output_exit(&dsi->output);
1106
1107 return 0;
1108}
1109
1110static int tegra_dsi_runtime_suspend(struct host1x_client *client)
1111{
1112 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1113 struct device *dev = client->dev;
1114 int err;
1115
1116 if (dsi->rst) {
1117 err = reset_control_assert(dsi->rst);
1118 if (err < 0) {
1119 dev_err(dev, "failed to assert reset: %d\n", err);
1120 return err;
1121 }
1122 }
1123
1124 usleep_range(1000, 2000);
1125
1126 clk_disable_unprepare(dsi->clk_lp);
1127 clk_disable_unprepare(dsi->clk);
1128
1129 regulator_disable(dsi->vdd);
1130 pm_runtime_put_sync(dev);
1131
1132 return 0;
1133}
1134
1135static int tegra_dsi_runtime_resume(struct host1x_client *client)
1136{
1137 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1138 struct device *dev = client->dev;
1139 int err;
1140
1141 err = pm_runtime_resume_and_get(dev);
1142 if (err < 0) {
1143 dev_err(dev, "failed to get runtime PM: %d\n", err);
1144 return err;
1145 }
1146
1147 err = regulator_enable(dsi->vdd);
1148 if (err < 0) {
1149 dev_err(dev, "failed to enable VDD supply: %d\n", err);
1150 goto put_rpm;
1151 }
1152
1153 err = clk_prepare_enable(dsi->clk);
1154 if (err < 0) {
1155 dev_err(dev, "cannot enable DSI clock: %d\n", err);
1156 goto disable_vdd;
1157 }
1158
1159 err = clk_prepare_enable(dsi->clk_lp);
1160 if (err < 0) {
1161 dev_err(dev, "cannot enable low-power clock: %d\n", err);
1162 goto disable_clk;
1163 }
1164
1165 usleep_range(1000, 2000);
1166
1167 if (dsi->rst) {
1168 err = reset_control_deassert(dsi->rst);
1169 if (err < 0) {
1170 dev_err(dev, "cannot assert reset: %d\n", err);
1171 goto disable_clk_lp;
1172 }
1173 }
1174
1175 return 0;
1176
1177disable_clk_lp:
1178 clk_disable_unprepare(dsi->clk_lp);
1179disable_clk:
1180 clk_disable_unprepare(dsi->clk);
1181disable_vdd:
1182 regulator_disable(dsi->vdd);
1183put_rpm:
1184 pm_runtime_put_sync(dev);
1185 return err;
1186}
1187
1188static const struct host1x_client_ops dsi_client_ops = {
1189 .init = tegra_dsi_init,
1190 .exit = tegra_dsi_exit,
1191 .suspend = tegra_dsi_runtime_suspend,
1192 .resume = tegra_dsi_runtime_resume,
1193};
1194
1195static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1196{
1197 struct clk *parent;
1198 int err;
1199
1200 /*
1201 * Tegra124+ uses a clock gate, not a mux, so this step
1202 * should be redundant for configuration; yet, DSI refuses
1203 * to work without it.
1204 */
1205
1206 parent = clk_get_parent(dsi->clk);
1207 if (!parent)
1208 return -EINVAL;
1209
1210 err = clk_set_parent(parent, dsi->clk_parent);
1211 if (err < 0)
1212 return err;
1213
1214 return 0;
1215}
1216
1217static const char * const error_report[16] = {
1218 "SoT Error",
1219 "SoT Sync Error",
1220 "EoT Sync Error",
1221 "Escape Mode Entry Command Error",
1222 "Low-Power Transmit Sync Error",
1223 "Peripheral Timeout Error",
1224 "False Control Error",
1225 "Contention Detected",
1226 "ECC Error, single-bit",
1227 "ECC Error, multi-bit",
1228 "Checksum Error",
1229 "DSI Data Type Not Recognized",
1230 "DSI VC ID Invalid",
1231 "Invalid Transmission Length",
1232 "Reserved",
1233 "DSI Protocol Violation",
1234};
1235
1236static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1237 const struct mipi_dsi_msg *msg,
1238 size_t count)
1239{
1240 u8 *rx = msg->rx_buf;
1241 unsigned int i, j, k;
1242 size_t size = 0;
1243 u16 errors;
1244 u32 value;
1245
1246 /* read and parse packet header */
1247 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1248
1249 switch (value & 0x3f) {
1250 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1251 errors = (value >> 8) & 0xffff;
1252 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1253 errors);
1254 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1255 if (errors & BIT(i))
1256 dev_dbg(dsi->dev, " %2u: %s\n", i,
1257 error_report[i]);
1258 break;
1259
1260 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1261 rx[0] = (value >> 8) & 0xff;
1262 size = 1;
1263 break;
1264
1265 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1266 rx[0] = (value >> 8) & 0xff;
1267 rx[1] = (value >> 16) & 0xff;
1268 size = 2;
1269 break;
1270
1271 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1272 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1273 break;
1274
1275 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1276 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1277 break;
1278
1279 default:
1280 dev_err(dsi->dev, "unhandled response type: %02x\n",
1281 value & 0x3f);
1282 return -EPROTO;
1283 }
1284
1285 size = min(size, msg->rx_len);
1286
1287 if (msg->rx_buf && size > 0) {
1288 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1289 u8 *rx = msg->rx_buf + j;
1290
1291 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1292
1293 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1294 rx[j + k] = (value >> (k << 3)) & 0xff;
1295 }
1296 }
1297
1298 return size;
1299}
1300
1301static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1302{
1303 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1304
1305 timeout = jiffies + msecs_to_jiffies(timeout);
1306
1307 while (time_before(jiffies, timeout)) {
1308 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1309 if ((value & DSI_TRIGGER_HOST) == 0)
1310 return 0;
1311
1312 usleep_range(1000, 2000);
1313 }
1314
1315 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1316 return -ETIMEDOUT;
1317}
1318
1319static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1320 unsigned long timeout)
1321{
1322 timeout = jiffies + msecs_to_jiffies(250);
1323
1324 while (time_before(jiffies, timeout)) {
1325 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1326 u8 count = value & 0x1f;
1327
1328 if (count > 0)
1329 return count;
1330
1331 usleep_range(1000, 2000);
1332 }
1333
1334 DRM_DEBUG_KMS("peripheral returned no data\n");
1335 return -ETIMEDOUT;
1336}
1337
1338static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1339 const void *buffer, size_t size)
1340{
1341 const u8 *buf = buffer;
1342 size_t i, j;
1343 u32 value;
1344
1345 for (j = 0; j < size; j += 4) {
1346 value = 0;
1347
1348 for (i = 0; i < 4 && j + i < size; i++)
1349 value |= buf[j + i] << (i << 3);
1350
1351 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1352 }
1353}
1354
1355static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1356 const struct mipi_dsi_msg *msg)
1357{
1358 struct tegra_dsi *dsi = host_to_tegra(host);
1359 struct mipi_dsi_packet packet;
1360 const u8 *header;
1361 size_t count;
1362 ssize_t err;
1363 u32 value;
1364
1365 err = mipi_dsi_create_packet(&packet, msg);
1366 if (err < 0)
1367 return err;
1368
1369 header = packet.header;
1370
1371 /* maximum FIFO depth is 1920 words */
1372 if (packet.size > dsi->video_fifo_depth * 4)
1373 return -ENOSPC;
1374
1375 /* reset underflow/overflow flags */
1376 value = tegra_dsi_readl(dsi, DSI_STATUS);
1377 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1378 value = DSI_HOST_CONTROL_FIFO_RESET;
1379 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1380 usleep_range(10, 20);
1381 }
1382
1383 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1384 value |= DSI_POWER_CONTROL_ENABLE;
1385 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1386
1387 usleep_range(5000, 10000);
1388
1389 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1390 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1391
1392 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1393 value |= DSI_HOST_CONTROL_HS;
1394
1395 /*
1396 * The host FIFO has a maximum of 64 words, so larger transmissions
1397 * need to use the video FIFO.
1398 */
1399 if (packet.size > dsi->host_fifo_depth * 4)
1400 value |= DSI_HOST_CONTROL_FIFO_SEL;
1401
1402 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1403
1404 /*
1405 * For reads and messages with explicitly requested ACK, generate a
1406 * BTA sequence after the transmission of the packet.
1407 */
1408 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1409 (msg->rx_buf && msg->rx_len > 0)) {
1410 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1411 value |= DSI_HOST_CONTROL_PKT_BTA;
1412 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1413 }
1414
1415 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1416 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1417
1418 /* write packet header, ECC is generated by hardware */
1419 value = header[2] << 16 | header[1] << 8 | header[0];
1420 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1421
1422 /* write payload (if any) */
1423 if (packet.payload_length > 0)
1424 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1425 packet.payload_length);
1426
1427 err = tegra_dsi_transmit(dsi, 250);
1428 if (err < 0)
1429 return err;
1430
1431 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1432 (msg->rx_buf && msg->rx_len > 0)) {
1433 err = tegra_dsi_wait_for_response(dsi, 250);
1434 if (err < 0)
1435 return err;
1436
1437 count = err;
1438
1439 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1440 switch (value) {
1441 case 0x84:
1442 /*
1443 dev_dbg(dsi->dev, "ACK\n");
1444 */
1445 break;
1446
1447 case 0x87:
1448 /*
1449 dev_dbg(dsi->dev, "ESCAPE\n");
1450 */
1451 break;
1452
1453 default:
1454 dev_err(dsi->dev, "unknown status: %08x\n", value);
1455 break;
1456 }
1457
1458 if (count > 1) {
1459 err = tegra_dsi_read_response(dsi, msg, count);
1460 if (err < 0)
1461 dev_err(dsi->dev,
1462 "failed to parse response: %zd\n",
1463 err);
1464 else {
1465 /*
1466 * For read commands, return the number of
1467 * bytes returned by the peripheral.
1468 */
1469 count = err;
1470 }
1471 }
1472 } else {
1473 /*
1474 * For write commands, we have transmitted the 4-byte header
1475 * plus the variable-length payload.
1476 */
1477 count = 4 + packet.payload_length;
1478 }
1479
1480 return count;
1481}
1482
1483static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1484{
1485 struct clk *parent;
1486 int err;
1487
1488 /* make sure both DSI controllers share the same PLL */
1489 parent = clk_get_parent(dsi->slave->clk);
1490 if (!parent)
1491 return -EINVAL;
1492
1493 err = clk_set_parent(parent, dsi->clk_parent);
1494 if (err < 0)
1495 return err;
1496
1497 return 0;
1498}
1499
1500static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1501 struct mipi_dsi_device *device)
1502{
1503 struct tegra_dsi *dsi = host_to_tegra(host);
1504
1505 dsi->flags = device->mode_flags;
1506 dsi->format = device->format;
1507 dsi->lanes = device->lanes;
1508
1509 if (dsi->slave) {
1510 int err;
1511
1512 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1513 dev_name(&device->dev));
1514
1515 err = tegra_dsi_ganged_setup(dsi);
1516 if (err < 0) {
1517 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1518 err);
1519 return err;
1520 }
1521 }
1522
1523 /*
1524 * Slaves don't have a panel associated with them, so they provide
1525 * merely the second channel.
1526 */
1527 if (!dsi->master) {
1528 struct tegra_output *output = &dsi->output;
1529
1530 /*
1531 * tegra_output_probe() never populates a panel for DSI
1532 * outputs, so output->panel is always NULL here.
1533 */
1534 output->panel = of_drm_find_panel(device->dev.of_node);
1535 if (IS_ERR(output->panel))
1536 output->panel = NULL;
1537
1538 if (output->panel && output->connector.dev)
1539 drm_helper_hpd_irq_event(output->connector.dev);
1540 }
1541
1542 return 0;
1543}
1544
1545static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1546 struct mipi_dsi_device *device)
1547{
1548 struct tegra_dsi *dsi = host_to_tegra(host);
1549 struct tegra_output *output = &dsi->output;
1550
1551 if (output->panel && &device->dev == output->panel->dev) {
1552 drm_panel_put(output->panel);
1553 output->panel = NULL;
1554
1555 if (output->connector.dev)
1556 drm_helper_hpd_irq_event(output->connector.dev);
1557 }
1558
1559 return 0;
1560}
1561
1562static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1563 .attach = tegra_dsi_host_attach,
1564 .detach = tegra_dsi_host_detach,
1565 .transfer = tegra_dsi_host_transfer,
1566};
1567
1568static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1569{
1570 struct device_node *np;
1571
1572 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1573 if (np) {
1574 struct platform_device *gangster = of_find_device_by_node(np);
1575 of_node_put(np);
1576 if (!gangster)
1577 return -EPROBE_DEFER;
1578
1579 dsi->slave = platform_get_drvdata(gangster);
1580 put_device(&gangster->dev);
1581 if (!dsi->slave)
1582 return -EPROBE_DEFER;
1583
1584 dsi->slave->master = dsi;
1585 }
1586
1587 return 0;
1588}
1589
1590static int tegra_dsi_probe(struct platform_device *pdev)
1591{
1592 struct tegra_dsi *dsi;
1593 int err;
1594
1595 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1596 if (!dsi)
1597 return -ENOMEM;
1598
1599 dsi->config = device_get_match_data(&pdev->dev);
1600 if (!dsi->config)
1601 return -ENODEV;
1602
1603 dsi->output.dev = dsi->dev = &pdev->dev;
1604 dsi->video_fifo_depth = 1920;
1605 dsi->host_fifo_depth = 64;
1606
1607 err = tegra_dsi_ganged_probe(dsi);
1608 if (err < 0)
1609 return err;
1610
1611 err = tegra_output_probe(&dsi->output);
1612 if (err < 0)
1613 return err;
1614
1615 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1616
1617 /*
1618 * Assume these values by default. When a DSI peripheral driver
1619 * attaches to the DSI host, the parameters will be taken from
1620 * the attached device.
1621 */
1622 dsi->flags = MIPI_DSI_MODE_VIDEO;
1623 dsi->format = MIPI_DSI_FMT_RGB888;
1624 dsi->lanes = 4;
1625
1626 if (!pdev->dev.pm_domain) {
1627 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1628 if (IS_ERR(dsi->rst)) {
1629 err = PTR_ERR(dsi->rst);
1630 goto remove;
1631 }
1632 }
1633
1634 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1635 if (IS_ERR(dsi->clk)) {
1636 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk),
1637 "cannot get DSI clock\n");
1638 goto remove;
1639 }
1640
1641 dsi->clk_lp = devm_clk_get_optional(&pdev->dev, "lp");
1642 if (IS_ERR(dsi->clk_lp)) {
1643 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp),
1644 "cannot get low-power clock\n");
1645 goto remove;
1646 }
1647
1648 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1649 if (IS_ERR(dsi->clk_parent)) {
1650 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_parent),
1651 "cannot get parent clock\n");
1652 goto remove;
1653 }
1654
1655 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1656 if (IS_ERR(dsi->vdd)) {
1657 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->vdd),
1658 "cannot get VDD supply\n");
1659 goto remove;
1660 }
1661
1662 if (dsi->config->has_mux_parent_clk) {
1663 err = tegra_dsi_setup_clocks(dsi);
1664 if (err < 0) {
1665 dev_err(&pdev->dev, "cannot setup clocks\n");
1666 goto remove;
1667 }
1668 }
1669
1670 dsi->regs = devm_platform_ioremap_resource(pdev, 0);
1671 if (IS_ERR(dsi->regs)) {
1672 err = PTR_ERR(dsi->regs);
1673 goto remove;
1674 }
1675
1676 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node);
1677 if (IS_ERR(dsi->mipi)) {
1678 err = PTR_ERR(dsi->mipi);
1679 goto remove;
1680 }
1681
1682 dsi->host.ops = &tegra_dsi_host_ops;
1683 dsi->host.dev = &pdev->dev;
1684
1685 err = mipi_dsi_host_register(&dsi->host);
1686 if (err < 0) {
1687 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1688 goto mipi_free;
1689 }
1690
1691 platform_set_drvdata(pdev, dsi);
1692 pm_runtime_enable(&pdev->dev);
1693
1694 INIT_LIST_HEAD(&dsi->client.list);
1695 dsi->client.ops = &dsi_client_ops;
1696 dsi->client.dev = &pdev->dev;
1697
1698 err = host1x_client_register(&dsi->client);
1699 if (err < 0) {
1700 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1701 err);
1702 goto unregister;
1703 }
1704
1705 return 0;
1706
1707unregister:
1708 pm_runtime_disable(&pdev->dev);
1709 mipi_dsi_host_unregister(&dsi->host);
1710mipi_free:
1711 tegra_mipi_free(dsi->mipi);
1712remove:
1713 tegra_output_remove(&dsi->output);
1714 return err;
1715}
1716
1717static void tegra_dsi_remove(struct platform_device *pdev)
1718{
1719 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1720
1721 pm_runtime_disable(&pdev->dev);
1722
1723 host1x_client_unregister(&dsi->client);
1724
1725 tegra_output_remove(&dsi->output);
1726
1727 mipi_dsi_host_unregister(&dsi->host);
1728 tegra_mipi_free(dsi->mipi);
1729}
1730
1731static const struct tegra_dsi_config tegra20_dsi_config = {
1732 .has_multiple_pad_controls = false,
1733 .has_mux_parent_clk = false,
1734};
1735
1736/*
1737 * Tegra30 allows DSIA/DSIB to be muxed to either PLL_D or PLL_D2; this is
1738 * simply not modeled in the clock driver yet. If this functionality is
1739 * required, the has_mux_parent_clk flag can be set to true once the clock
1740 * driver is patched.
1741 */
1742static const struct tegra_dsi_config tegra30_dsi_config = {
1743 .has_multiple_pad_controls = false,
1744 .has_mux_parent_clk = false,
1745};
1746
1747static const struct tegra_dsi_config tegra114_dsi_config = {
1748 .has_multiple_pad_controls = true,
1749 .has_mux_parent_clk = true,
1750};
1751
1752/* TODO: figure out why has_mux_parent_clk = true is necessary on Tegra124+ */
1753static const struct tegra_dsi_config tegra124_dsi_config = {
1754 .has_multiple_pad_controls = true,
1755 .has_mux_parent_clk = true,
1756};
1757
1758static const struct of_device_id tegra_dsi_of_match[] = {
1759 { .compatible = "nvidia,tegra210-dsi", .data = &tegra124_dsi_config },
1760 { .compatible = "nvidia,tegra132-dsi", .data = &tegra124_dsi_config },
1761 { .compatible = "nvidia,tegra124-dsi", .data = &tegra124_dsi_config },
1762 { .compatible = "nvidia,tegra114-dsi", .data = &tegra114_dsi_config },
1763 { .compatible = "nvidia,tegra30-dsi", .data = &tegra30_dsi_config },
1764 { .compatible = "nvidia,tegra20-dsi", .data = &tegra20_dsi_config },
1765 { },
1766};
1767MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1768
1769struct platform_driver tegra_dsi_driver = {
1770 .driver = {
1771 .name = "tegra-dsi",
1772 .of_match_table = tegra_dsi_of_match,
1773 },
1774 .probe = tegra_dsi_probe,
1775 .remove = tegra_dsi_remove,
1776};