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| 2 | |
| 3 | * Copyright (C) 2013 NVIDIA Corporation
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| 4 |
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| 5 |
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| 6 | #ifndef TEGRA_GR2D_H
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| 7 | #define TEGRA_GR2D_H
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| 8 |
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| 9 | #define GR2D_UA_BASE_ADDR 0x1a
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| 10 | #define GR2D_VA_BASE_ADDR 0x1b
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| 11 | #define GR2D_PAT_BASE_ADDR 0x26
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| 12 | #define GR2D_DSTA_BASE_ADDR 0x2b
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| 13 | #define GR2D_DSTB_BASE_ADDR 0x2c
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| 14 | #define GR2D_DSTC_BASE_ADDR 0x2d
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| 15 | #define GR2D_SRCA_BASE_ADDR 0x31
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| 16 | #define GR2D_SRCB_BASE_ADDR 0x32
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| 17 | #define GR2D_PATBASE_ADDR 0x47
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| 18 | #define GR2D_SRC_BASE_ADDR_SB 0x48
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| 19 | #define GR2D_DSTA_BASE_ADDR_SB 0x49
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| 20 | #define GR2D_DSTB_BASE_ADDR_SB 0x4a
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| 21 | #define GR2D_UA_BASE_ADDR_SB 0x4b
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| 22 | #define GR2D_VA_BASE_ADDR_SB 0x4c
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| 23 |
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| 24 | #define GR2D_NUM_REGS 0x4d
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| 25 |
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| 26 | #endif
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