projects/linux·blob master · refs

615 lines · 14.2 KiB

1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Avionic Design GmbH
4 * Copyright (C) 2013 NVIDIA Corporation
5 */
6
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/host1x.h>
10#include <linux/iommu.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/platform_device.h>
14#include <linux/pm_domain.h>
15#include <linux/pm_opp.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18
19#include <soc/tegra/common.h>
20#include <soc/tegra/pmc.h>
21
22#include "drm.h"
23#include "gem.h"
24#include "gr3d.h"
25
26enum {
27 RST_MC,
28 RST_GR3D,
29 RST_MC2,
30 RST_GR3D2,
31 RST_GR3D_MAX,
32};
33
34struct gr3d_soc {
35 unsigned int version;
36 unsigned int num_clocks;
37 unsigned int num_resets;
38};
39
40struct gr3d {
41 struct tegra_drm_client client;
42 struct host1x_channel *channel;
43
44 const struct gr3d_soc *soc;
45 struct clk_bulk_data *clocks;
46 unsigned int nclocks;
47 struct reset_control_bulk_data resets[RST_GR3D_MAX];
48 unsigned int nresets;
49 struct tegra_pmc *pmc;
50 struct dev_pm_domain_list *pd_list;
51
52 DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
53};
54
55static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
56{
57 return container_of(client, struct gr3d, client);
58}
59
60static int gr3d_init(struct host1x_client *client)
61{
62 struct tegra_drm_client *drm = host1x_to_drm_client(client);
63 struct drm_device *dev = dev_get_drvdata(client->host);
64 unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
65 struct gr3d *gr3d = to_gr3d(drm);
66 int err;
67
68 gr3d->channel = host1x_channel_request(client);
69 if (!gr3d->channel)
70 return -ENOMEM;
71
72 client->syncpts[0] = host1x_syncpt_request(client, flags);
73 if (!client->syncpts[0]) {
74 err = -ENOMEM;
75 dev_err(client->dev, "failed to request syncpoint: %d\n", err);
76 goto put;
77 }
78
79 err = host1x_client_iommu_attach(client);
80 if (err < 0) {
81 dev_err(client->dev, "failed to attach to domain: %d\n", err);
82 goto free;
83 }
84
85 err = tegra_drm_register_client(dev->dev_private, drm);
86 if (err < 0) {
87 dev_err(client->dev, "failed to register client: %d\n", err);
88 goto detach_iommu;
89 }
90
91 return 0;
92
93detach_iommu:
94 host1x_client_iommu_detach(client);
95free:
96 host1x_syncpt_put(client->syncpts[0]);
97put:
98 host1x_channel_put(gr3d->channel);
99 return err;
100}
101
102static int gr3d_exit(struct host1x_client *client)
103{
104 struct tegra_drm_client *drm = host1x_to_drm_client(client);
105 struct drm_device *dev = dev_get_drvdata(client->host);
106 struct gr3d *gr3d = to_gr3d(drm);
107 int err;
108
109 err = tegra_drm_unregister_client(dev->dev_private, drm);
110 if (err < 0)
111 return err;
112
113 host1x_client_iommu_detach(client);
114 host1x_syncpt_put(client->syncpts[0]);
115 host1x_channel_put(gr3d->channel);
116
117 gr3d->channel = NULL;
118
119 return 0;
120}
121
122static const struct host1x_client_ops gr3d_client_ops = {
123 .init = gr3d_init,
124 .exit = gr3d_exit,
125};
126
127static int gr3d_open_channel(struct tegra_drm_client *client,
128 struct tegra_drm_context *context)
129{
130 struct gr3d *gr3d = to_gr3d(client);
131
132 context->channel = host1x_channel_get(gr3d->channel);
133 if (!context->channel)
134 return -ENOMEM;
135
136 return 0;
137}
138
139static void gr3d_close_channel(struct tegra_drm_context *context)
140{
141 host1x_channel_put(context->channel);
142}
143
144static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
145{
146 struct gr3d *gr3d = dev_get_drvdata(dev);
147
148 switch (class) {
149 case HOST1X_CLASS_HOST1X:
150 if (offset == 0x2b)
151 return 1;
152
153 break;
154
155 case HOST1X_CLASS_GR3D:
156 if (offset >= GR3D_NUM_REGS)
157 break;
158
159 if (test_bit(offset, gr3d->addr_regs))
160 return 1;
161
162 break;
163 }
164
165 return 0;
166}
167
168static const struct tegra_drm_client_ops gr3d_ops = {
169 .open_channel = gr3d_open_channel,
170 .close_channel = gr3d_close_channel,
171 .is_addr_reg = gr3d_is_addr_reg,
172 .submit = tegra_drm_submit,
173};
174
175static const struct gr3d_soc tegra20_gr3d_soc = {
176 .version = 0x20,
177 .num_clocks = 1,
178 .num_resets = 2,
179};
180
181static const struct gr3d_soc tegra30_gr3d_soc = {
182 .version = 0x30,
183 .num_clocks = 2,
184 .num_resets = 4,
185};
186
187static const struct gr3d_soc tegra114_gr3d_soc = {
188 .version = 0x35,
189 .num_clocks = 1,
190 .num_resets = 2,
191};
192
193static const struct of_device_id tegra_gr3d_match[] = {
194 { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc },
195 { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc },
196 { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc },
197 { }
198};
199MODULE_DEVICE_TABLE(of, tegra_gr3d_match);
200
201static const u32 gr3d_addr_regs[] = {
202 GR3D_IDX_ATTRIBUTE( 0),
203 GR3D_IDX_ATTRIBUTE( 1),
204 GR3D_IDX_ATTRIBUTE( 2),
205 GR3D_IDX_ATTRIBUTE( 3),
206 GR3D_IDX_ATTRIBUTE( 4),
207 GR3D_IDX_ATTRIBUTE( 5),
208 GR3D_IDX_ATTRIBUTE( 6),
209 GR3D_IDX_ATTRIBUTE( 7),
210 GR3D_IDX_ATTRIBUTE( 8),
211 GR3D_IDX_ATTRIBUTE( 9),
212 GR3D_IDX_ATTRIBUTE(10),
213 GR3D_IDX_ATTRIBUTE(11),
214 GR3D_IDX_ATTRIBUTE(12),
215 GR3D_IDX_ATTRIBUTE(13),
216 GR3D_IDX_ATTRIBUTE(14),
217 GR3D_IDX_ATTRIBUTE(15),
218 GR3D_IDX_INDEX_BASE,
219 GR3D_QR_ZTAG_ADDR,
220 GR3D_QR_CTAG_ADDR,
221 GR3D_QR_CZ_ADDR,
222 GR3D_TEX_TEX_ADDR( 0),
223 GR3D_TEX_TEX_ADDR( 1),
224 GR3D_TEX_TEX_ADDR( 2),
225 GR3D_TEX_TEX_ADDR( 3),
226 GR3D_TEX_TEX_ADDR( 4),
227 GR3D_TEX_TEX_ADDR( 5),
228 GR3D_TEX_TEX_ADDR( 6),
229 GR3D_TEX_TEX_ADDR( 7),
230 GR3D_TEX_TEX_ADDR( 8),
231 GR3D_TEX_TEX_ADDR( 9),
232 GR3D_TEX_TEX_ADDR(10),
233 GR3D_TEX_TEX_ADDR(11),
234 GR3D_TEX_TEX_ADDR(12),
235 GR3D_TEX_TEX_ADDR(13),
236 GR3D_TEX_TEX_ADDR(14),
237 GR3D_TEX_TEX_ADDR(15),
238 GR3D_DW_MEMORY_OUTPUT_ADDRESS,
239 GR3D_GLOBAL_SURFADDR( 0),
240 GR3D_GLOBAL_SURFADDR( 1),
241 GR3D_GLOBAL_SURFADDR( 2),
242 GR3D_GLOBAL_SURFADDR( 3),
243 GR3D_GLOBAL_SURFADDR( 4),
244 GR3D_GLOBAL_SURFADDR( 5),
245 GR3D_GLOBAL_SURFADDR( 6),
246 GR3D_GLOBAL_SURFADDR( 7),
247 GR3D_GLOBAL_SURFADDR( 8),
248 GR3D_GLOBAL_SURFADDR( 9),
249 GR3D_GLOBAL_SURFADDR(10),
250 GR3D_GLOBAL_SURFADDR(11),
251 GR3D_GLOBAL_SURFADDR(12),
252 GR3D_GLOBAL_SURFADDR(13),
253 GR3D_GLOBAL_SURFADDR(14),
254 GR3D_GLOBAL_SURFADDR(15),
255 GR3D_GLOBAL_SPILLSURFADDR,
256 GR3D_GLOBAL_SURFOVERADDR( 0),
257 GR3D_GLOBAL_SURFOVERADDR( 1),
258 GR3D_GLOBAL_SURFOVERADDR( 2),
259 GR3D_GLOBAL_SURFOVERADDR( 3),
260 GR3D_GLOBAL_SURFOVERADDR( 4),
261 GR3D_GLOBAL_SURFOVERADDR( 5),
262 GR3D_GLOBAL_SURFOVERADDR( 6),
263 GR3D_GLOBAL_SURFOVERADDR( 7),
264 GR3D_GLOBAL_SURFOVERADDR( 8),
265 GR3D_GLOBAL_SURFOVERADDR( 9),
266 GR3D_GLOBAL_SURFOVERADDR(10),
267 GR3D_GLOBAL_SURFOVERADDR(11),
268 GR3D_GLOBAL_SURFOVERADDR(12),
269 GR3D_GLOBAL_SURFOVERADDR(13),
270 GR3D_GLOBAL_SURFOVERADDR(14),
271 GR3D_GLOBAL_SURFOVERADDR(15),
272 GR3D_GLOBAL_SAMP01SURFADDR( 0),
273 GR3D_GLOBAL_SAMP01SURFADDR( 1),
274 GR3D_GLOBAL_SAMP01SURFADDR( 2),
275 GR3D_GLOBAL_SAMP01SURFADDR( 3),
276 GR3D_GLOBAL_SAMP01SURFADDR( 4),
277 GR3D_GLOBAL_SAMP01SURFADDR( 5),
278 GR3D_GLOBAL_SAMP01SURFADDR( 6),
279 GR3D_GLOBAL_SAMP01SURFADDR( 7),
280 GR3D_GLOBAL_SAMP01SURFADDR( 8),
281 GR3D_GLOBAL_SAMP01SURFADDR( 9),
282 GR3D_GLOBAL_SAMP01SURFADDR(10),
283 GR3D_GLOBAL_SAMP01SURFADDR(11),
284 GR3D_GLOBAL_SAMP01SURFADDR(12),
285 GR3D_GLOBAL_SAMP01SURFADDR(13),
286 GR3D_GLOBAL_SAMP01SURFADDR(14),
287 GR3D_GLOBAL_SAMP01SURFADDR(15),
288 GR3D_GLOBAL_SAMP23SURFADDR( 0),
289 GR3D_GLOBAL_SAMP23SURFADDR( 1),
290 GR3D_GLOBAL_SAMP23SURFADDR( 2),
291 GR3D_GLOBAL_SAMP23SURFADDR( 3),
292 GR3D_GLOBAL_SAMP23SURFADDR( 4),
293 GR3D_GLOBAL_SAMP23SURFADDR( 5),
294 GR3D_GLOBAL_SAMP23SURFADDR( 6),
295 GR3D_GLOBAL_SAMP23SURFADDR( 7),
296 GR3D_GLOBAL_SAMP23SURFADDR( 8),
297 GR3D_GLOBAL_SAMP23SURFADDR( 9),
298 GR3D_GLOBAL_SAMP23SURFADDR(10),
299 GR3D_GLOBAL_SAMP23SURFADDR(11),
300 GR3D_GLOBAL_SAMP23SURFADDR(12),
301 GR3D_GLOBAL_SAMP23SURFADDR(13),
302 GR3D_GLOBAL_SAMP23SURFADDR(14),
303 GR3D_GLOBAL_SAMP23SURFADDR(15),
304};
305
306static int gr3d_power_up_legacy_domain(struct device *dev, const char *name,
307 unsigned int id)
308{
309 struct gr3d *gr3d = dev_get_drvdata(dev);
310 struct reset_control *reset;
311 struct clk *clk;
312 unsigned int i;
313 int err;
314
315 /*
316 * Tegra20 device-tree doesn't specify 3d clock name and there is only
317 * one clock for Tegra20. Tegra30+ device-trees always specified names
318 * for the clocks.
319 */
320 if (gr3d->nclocks == 1) {
321 if (id == TEGRA_POWERGATE_3D1)
322 return 0;
323
324 clk = gr3d->clocks[0].clk;
325 } else {
326 for (i = 0; i < gr3d->nclocks; i++) {
327 if (WARN_ON(!gr3d->clocks[i].id))
328 continue;
329
330 if (!strcmp(gr3d->clocks[i].id, name)) {
331 clk = gr3d->clocks[i].clk;
332 break;
333 }
334 }
335
336 if (WARN_ON(i == gr3d->nclocks))
337 return -EINVAL;
338 }
339
340 /*
341 * We use array of resets, which includes MC resets, and MC
342 * reset shouldn't be asserted while hardware is gated because
343 * MC flushing will fail for gated hardware. Hence for legacy
344 * PD we request the individual reset separately.
345 */
346 reset = reset_control_get_exclusive_released(dev, name);
347 if (IS_ERR(reset))
348 return PTR_ERR(reset);
349
350 err = reset_control_acquire(reset);
351 if (err) {
352 dev_err(dev, "failed to acquire %s reset: %d\n", name, err);
353 } else {
354 err = tegra_pmc_powergate_sequence_power_up(gr3d->pmc, id,
355 clk, reset);
356 reset_control_release(reset);
357 }
358
359 reset_control_put(reset);
360 if (err)
361 return err;
362
363 /*
364 * tegra_powergate_sequence_power_up() leaves clocks enabled,
365 * while GENPD not. Hence keep clock-enable balanced.
366 */
367 clk_disable_unprepare(clk);
368
369 return 0;
370}
371
372static int gr3d_init_power(struct device *dev, struct gr3d *gr3d)
373{
374 struct dev_pm_domain_attach_data pd_data = {
375 .pd_names = (const char *[]) { "3d0", "3d1" },
376 .num_pd_names = 2,
377 .pd_flags = PD_FLAG_REQUIRED_OPP,
378 };
379 int err;
380
381 err = of_count_phandle_with_args(dev->of_node, "power-domains",
382 "#power-domain-cells");
383 if (err < 0) {
384 if (err != -ENOENT)
385 return err;
386
387 gr3d->pmc = devm_tegra_pmc_get(dev);
388 if (IS_ERR(gr3d->pmc))
389 return dev_err_probe(dev, PTR_ERR(gr3d->pmc),
390 "failed to get PMC\n");
391
392 /*
393 * Older device-trees don't use GENPD. In this case we should
394 * toggle power domain manually.
395 */
396 err = gr3d_power_up_legacy_domain(dev, "3d",
397 TEGRA_POWERGATE_3D);
398 if (err)
399 return err;
400
401 err = gr3d_power_up_legacy_domain(dev, "3d2",
402 TEGRA_POWERGATE_3D1);
403 if (err)
404 return err;
405
406 return 0;
407 }
408
409 /*
410 * The PM domain core automatically attaches a single power domain,
411 * otherwise it skips attaching completely. We have a single domain
412 * on Tegra20 and two domains on Tegra30+.
413 */
414 if (dev->pm_domain)
415 return 0;
416
417 err = devm_pm_domain_attach_list(dev, &pd_data, &gr3d->pd_list);
418 if (err < 0)
419 return err;
420
421 return 0;
422}
423
424static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d)
425{
426 int err;
427
428 err = devm_clk_bulk_get_all(dev, &gr3d->clocks);
429 if (err < 0) {
430 dev_err(dev, "failed to get clock: %d\n", err);
431 return err;
432 }
433 gr3d->nclocks = err;
434
435 if (gr3d->nclocks != gr3d->soc->num_clocks) {
436 dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks);
437 return -ENOENT;
438 }
439
440 return 0;
441}
442
443static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d)
444{
445 int err;
446
447 gr3d->resets[RST_MC].id = "mc";
448 gr3d->resets[RST_MC2].id = "mc2";
449 gr3d->resets[RST_GR3D].id = "3d";
450 gr3d->resets[RST_GR3D2].id = "3d2";
451 gr3d->nresets = gr3d->soc->num_resets;
452
453 err = devm_reset_control_bulk_get_optional_exclusive_released(
454 dev, gr3d->nresets, gr3d->resets);
455 if (err) {
456 dev_err(dev, "failed to get reset: %d\n", err);
457 return err;
458 }
459
460 if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) ||
461 WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4))
462 return -ENOENT;
463
464 return 0;
465}
466
467static int gr3d_probe(struct platform_device *pdev)
468{
469 struct host1x_syncpt **syncpts;
470 struct gr3d *gr3d;
471 unsigned int i;
472 int err;
473
474 gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
475 if (!gr3d)
476 return -ENOMEM;
477
478 platform_set_drvdata(pdev, gr3d);
479
480 gr3d->soc = of_device_get_match_data(&pdev->dev);
481
482 syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL);
483 if (!syncpts)
484 return -ENOMEM;
485
486 err = gr3d_get_clocks(&pdev->dev, gr3d);
487 if (err)
488 return err;
489
490 err = gr3d_get_resets(&pdev->dev, gr3d);
491 if (err)
492 return err;
493
494 err = gr3d_init_power(&pdev->dev, gr3d);
495 if (err)
496 return err;
497
498 INIT_LIST_HEAD(&gr3d->client.base.list);
499 gr3d->client.base.ops = &gr3d_client_ops;
500 gr3d->client.base.dev = &pdev->dev;
501 gr3d->client.base.class = HOST1X_CLASS_GR3D;
502 gr3d->client.base.syncpts = syncpts;
503 gr3d->client.base.num_syncpts = 1;
504
505 INIT_LIST_HEAD(&gr3d->client.list);
506 gr3d->client.version = gr3d->soc->version;
507 gr3d->client.ops = &gr3d_ops;
508
509 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
510 if (err)
511 return err;
512
513 /* initialize address register map */
514 for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++)
515 set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
516
517 pm_runtime_enable(&pdev->dev);
518
519 err = host1x_client_register(&gr3d->client.base);
520 if (err < 0) {
521 pm_runtime_disable(&pdev->dev);
522 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
523 err);
524 return err;
525 }
526
527 pm_runtime_use_autosuspend(&pdev->dev);
528 pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
529
530 return 0;
531}
532
533static void gr3d_remove(struct platform_device *pdev)
534{
535 struct gr3d *gr3d = platform_get_drvdata(pdev);
536
537 pm_runtime_disable(&pdev->dev);
538 host1x_client_unregister(&gr3d->client.base);
539}
540
541static int __maybe_unused gr3d_runtime_suspend(struct device *dev)
542{
543 struct gr3d *gr3d = dev_get_drvdata(dev);
544 int err;
545
546 host1x_channel_stop(gr3d->channel);
547
548 err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets);
549 if (err) {
550 dev_err(dev, "failed to assert reset: %d\n", err);
551 return err;
552 }
553
554 usleep_range(10, 20);
555
556 /*
557 * Older device-trees don't specify MC resets and power-gating can't
558 * be done safely in that case. Hence we will keep the power ungated
559 * for older DTBs. For newer DTBs, GENPD will perform the power-gating.
560 */
561
562 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
563 reset_control_bulk_release(gr3d->nresets, gr3d->resets);
564
565 return 0;
566}
567
568static int __maybe_unused gr3d_runtime_resume(struct device *dev)
569{
570 struct gr3d *gr3d = dev_get_drvdata(dev);
571 int err;
572
573 err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets);
574 if (err) {
575 dev_err(dev, "failed to acquire reset: %d\n", err);
576 return err;
577 }
578
579 err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks);
580 if (err) {
581 dev_err(dev, "failed to enable clock: %d\n", err);
582 goto release_reset;
583 }
584
585 err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets);
586 if (err) {
587 dev_err(dev, "failed to deassert reset: %d\n", err);
588 goto disable_clk;
589 }
590
591 return 0;
592
593disable_clk:
594 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
595release_reset:
596 reset_control_bulk_release(gr3d->nresets, gr3d->resets);
597
598 return err;
599}
600
601static const struct dev_pm_ops tegra_gr3d_pm = {
602 SET_RUNTIME_PM_OPS(gr3d_runtime_suspend, gr3d_runtime_resume, NULL)
603 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
604 pm_runtime_force_resume)
605};
606
607struct platform_driver tegra_gr3d_driver = {
608 .driver = {
609 .name = "tegra-gr3d",
610 .of_match_table = tegra_gr3d_match,
611 .pm = &tegra_gr3d_pm,
612 },
613 .probe = gr3d_probe,
614 .remove = gr3d_remove,
615};