| 1 | |
| 2 | |
| 3 | * Copyright (c) 2021, NVIDIA Corporation.
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| 4 |
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| 5 |
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| 6 | #include <linux/device.h>
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| 7 | #include <linux/host1x_context_bus.h>
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| 8 | #include <linux/kref.h>
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| 9 | #include <linux/of.h>
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| 10 | #include <linux/of_device.h>
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| 11 | #include <linux/pid.h>
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| 12 | #include <linux/slab.h>
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| 13 |
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| 14 | #include "context.h"
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| 15 | #include "dev.h"
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| 16 |
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| 17 | static void host1x_memory_context_release(struct device *dev)
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| 18 | {
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| 19 |
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| 20 | }
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| 21 |
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| 22 | int host1x_memory_context_list_init(struct host1x *host1x)
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| 23 | {
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| 24 | struct host1x_memory_context_list *cdl = &host1x->context_list;
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| 25 | struct device_node *node = host1x->dev->of_node;
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| 26 | struct host1x_memory_context *ctx;
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| 27 | unsigned int devs, i;
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| 28 | int err;
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| 29 |
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| 30 | cdl->devs = NULL;
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| 31 | cdl->len = 0;
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| 32 | mutex_init(&cdl->lock);
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| 33 |
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| 34 | err = of_property_count_u32_elems(node, "iommu-map");
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| 35 | if (err < 0)
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| 36 | return 0;
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| 37 |
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| 38 | devs = 0;
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| 39 |
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| 40 | for (i = 0; i < err / 4; i++) {
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| 41 | u32 length;
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| 42 |
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| 43 | of_property_read_u32_index(node, "iommu-map", i * 4 + 3, &length);
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| 44 | devs += length;
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| 45 | }
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| 46 |
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| 47 | cdl->len = devs;
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| 48 | cdl->devs = kzalloc_objs(*cdl->devs, cdl->len);
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| 49 | if (!cdl->devs)
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| 50 | return -ENOMEM;
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| 51 |
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| 52 | for (i = 0; i < cdl->len; i++) {
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| 53 | ctx = &cdl->devs[i];
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| 54 |
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| 55 | ctx->host = host1x;
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| 56 |
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| 57 | device_initialize(&ctx->dev);
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| 58 |
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| 59 | |
| 60 | * Due to an issue with T194 NVENC, only 38 bits can be used.
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| 61 | * Anyway, 256GiB of IOVA ought to be enough for anyone.
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| 62 |
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| 63 | ctx->dma_mask = DMA_BIT_MASK(38);
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| 64 | ctx->dev.dma_mask = &ctx->dma_mask;
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| 65 | ctx->dev.coherent_dma_mask = ctx->dma_mask;
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| 66 | dev_set_name(&ctx->dev, "host1x-ctx.%d", i);
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| 67 | ctx->dev.bus = &host1x_context_device_bus_type;
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| 68 | ctx->dev.parent = host1x->dev;
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| 69 | ctx->dev.release = host1x_memory_context_release;
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| 70 |
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| 71 | ctx->dev.dma_parms = &ctx->dma_parms;
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| 72 | dma_set_max_seg_size(&ctx->dev, UINT_MAX);
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| 73 |
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| 74 | err = device_add(&ctx->dev);
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| 75 | if (err) {
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| 76 | dev_err(host1x->dev, "could not add context device %d: %d\n", i, err);
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| 77 | put_device(&ctx->dev);
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| 78 | goto unreg_devices;
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| 79 | }
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| 80 |
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| 81 | err = of_dma_configure_id(&ctx->dev, node, true, &i);
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| 82 | if (err) {
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| 83 | dev_err(host1x->dev, "IOMMU configuration failed for context device %d: %d\n",
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| 84 | i, err);
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| 85 | device_unregister(&ctx->dev);
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| 86 | goto unreg_devices;
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| 87 | }
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| 88 |
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| 89 | if (!tegra_dev_iommu_get_stream_id(&ctx->dev, &ctx->stream_id) ||
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| 90 | !device_iommu_mapped(&ctx->dev)) {
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| 91 | dev_err(host1x->dev, "Context device %d has no IOMMU!\n", i);
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| 92 | device_unregister(&ctx->dev);
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| 93 |
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| 94 | |
| 95 | * This means that if IOMMU is disabled but context devices
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| 96 | * are defined in the device tree, Host1x will fail to probe.
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| 97 | * That's probably OK in this time and age.
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| 98 |
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| 99 | err = -EINVAL;
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| 100 |
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| 101 | goto unreg_devices;
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| 102 | }
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| 103 | }
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| 104 |
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| 105 | return 0;
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| 106 |
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| 107 | unreg_devices:
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| 108 | while (i--)
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| 109 | device_unregister(&cdl->devs[i].dev);
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| 110 |
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| 111 | kfree(cdl->devs);
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| 112 | cdl->devs = NULL;
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| 113 | cdl->len = 0;
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| 114 |
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| 115 | return err;
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| 116 | }
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| 117 |
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| 118 | void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)
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| 119 | {
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| 120 | unsigned int i;
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| 121 |
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| 122 | for (i = 0; i < cdl->len; i++)
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| 123 | device_unregister(&cdl->devs[i].dev);
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| 124 |
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| 125 | kfree(cdl->devs);
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| 126 | cdl->len = 0;
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| 127 | }
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| 128 |
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| 129 | struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
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| 130 | struct device *dev,
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| 131 | struct pid *pid)
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| 132 | {
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| 133 | struct host1x_memory_context_list *cdl = &host1x->context_list;
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| 134 | struct host1x_memory_context *free = NULL;
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| 135 | int i;
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| 136 |
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| 137 | if (!cdl->len)
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| 138 | return ERR_PTR(-EOPNOTSUPP);
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| 139 |
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| 140 | mutex_lock(&cdl->lock);
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| 141 |
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| 142 | for (i = 0; i < cdl->len; i++) {
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| 143 | struct host1x_memory_context *cd = &cdl->devs[i];
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| 144 |
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| 145 | if (cd->dev.iommu->iommu_dev != dev->iommu->iommu_dev)
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| 146 | continue;
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| 147 |
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| 148 | if (cd->owner == pid) {
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| 149 | refcount_inc(&cd->ref);
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| 150 | mutex_unlock(&cdl->lock);
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| 151 | return cd;
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| 152 | } else if (!cd->owner && !free) {
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| 153 | free = cd;
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| 154 | }
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| 155 | }
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| 156 |
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| 157 | if (!free) {
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| 158 | mutex_unlock(&cdl->lock);
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| 159 | return ERR_PTR(-EBUSY);
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| 160 | }
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| 161 |
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| 162 | refcount_set(&free->ref, 1);
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| 163 | free->owner = get_pid(pid);
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| 164 |
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| 165 | mutex_unlock(&cdl->lock);
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| 166 |
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| 167 | return free;
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| 168 | }
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| 169 | EXPORT_SYMBOL_GPL(host1x_memory_context_alloc);
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| 170 |
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| 171 | void host1x_memory_context_get(struct host1x_memory_context *cd)
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| 172 | {
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| 173 | refcount_inc(&cd->ref);
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| 174 | }
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| 175 | EXPORT_SYMBOL_GPL(host1x_memory_context_get);
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| 176 |
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| 177 | void host1x_memory_context_put(struct host1x_memory_context *cd)
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| 178 | {
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| 179 | struct host1x_memory_context_list *cdl = &cd->host->context_list;
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| 180 |
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| 181 | if (refcount_dec_and_mutex_lock(&cd->ref, &cdl->lock)) {
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| 182 | put_pid(cd->owner);
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| 183 | cd->owner = NULL;
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| 184 | mutex_unlock(&cdl->lock);
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| 185 | }
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| 186 | }
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| 187 | EXPORT_SYMBOL_GPL(host1x_memory_context_put);
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