| 1 | |
| 2 | |
| 3 | * Tegra host1x Interrupt Management
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| 4 | *
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| 5 | * Copyright (c) 2010-2021, NVIDIA Corporation.
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| 6 |
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| 7 |
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| 8 | #include <linux/clk.h>
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| 9 | #include <linux/interrupt.h>
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| 10 | #include <linux/overflow.h>
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| 11 | #include "dev.h"
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| 12 | #include "fence.h"
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| 13 | #include "intr.h"
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| 14 |
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| 15 | static void host1x_intr_add_fence_to_list(struct host1x_fence_list *list,
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| 16 | struct host1x_syncpt_fence *fence)
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| 17 | {
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| 18 | struct host1x_syncpt_fence *fence_in_list;
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| 19 |
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| 20 | list_for_each_entry_reverse(fence_in_list, &list->list, list) {
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| 21 | if ((s32)wrapping_sub(u32, fence_in_list->threshold, fence->threshold) <= 0) {
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| 22 |
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| 23 | list_add(&fence->list, &fence_in_list->list);
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| 24 | return;
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| 25 | }
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| 26 | }
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| 27 |
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| 28 |
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| 29 | list_add(&fence->list, &list->list);
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| 30 | }
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| 31 |
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| 32 | static void host1x_intr_update_hw_state(struct host1x *host, struct host1x_syncpt *sp)
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| 33 | {
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| 34 | struct host1x_syncpt_fence *fence;
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| 35 |
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| 36 | if (!list_empty(&sp->fences.list)) {
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| 37 | fence = list_first_entry(&sp->fences.list, struct host1x_syncpt_fence, list);
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| 38 |
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| 39 | host1x_hw_intr_set_syncpt_threshold(host, sp->id, fence->threshold);
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| 40 | host1x_hw_intr_enable_syncpt_intr(host, sp->id);
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| 41 | } else {
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| 42 | host1x_hw_intr_disable_syncpt_intr(host, sp->id);
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| 43 | }
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| 44 | }
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| 45 |
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| 46 | void host1x_intr_add_fence_locked(struct host1x *host, struct host1x_syncpt_fence *fence)
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| 47 | {
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| 48 | struct host1x_fence_list *fence_list = &fence->sp->fences;
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| 49 |
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| 50 | INIT_LIST_HEAD(&fence->list);
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| 51 |
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| 52 | host1x_intr_add_fence_to_list(fence_list, fence);
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| 53 | host1x_intr_update_hw_state(host, fence->sp);
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| 54 | }
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| 55 |
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| 56 | bool host1x_intr_remove_fence(struct host1x *host, struct host1x_syncpt_fence *fence)
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| 57 | {
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| 58 | struct host1x_fence_list *fence_list = &fence->sp->fences;
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| 59 | unsigned long irqflags;
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| 60 |
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| 61 | spin_lock_irqsave(&fence_list->lock, irqflags);
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| 62 |
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| 63 | if (list_empty(&fence->list)) {
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| 64 | spin_unlock_irqrestore(&fence_list->lock, irqflags);
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| 65 | return false;
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| 66 | }
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| 67 |
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| 68 | list_del_init(&fence->list);
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| 69 | host1x_intr_update_hw_state(host, fence->sp);
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| 70 |
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| 71 | spin_unlock_irqrestore(&fence_list->lock, irqflags);
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| 72 |
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| 73 | return true;
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| 74 | }
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| 75 |
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| 76 | void host1x_intr_handle_interrupt(struct host1x *host, unsigned int id)
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| 77 | {
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| 78 | struct host1x_syncpt *sp = &host->syncpt[id];
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| 79 | struct host1x_syncpt_fence *fence, *tmp;
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| 80 | unsigned int value;
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| 81 |
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| 82 | value = host1x_syncpt_load(sp);
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| 83 |
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| 84 | spin_lock(&sp->fences.lock);
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| 85 |
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| 86 | list_for_each_entry_safe(fence, tmp, &sp->fences.list, list) {
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| 87 | if ((wrapping_sub(u32, value, fence->threshold) & 0x80000000U) != 0U) {
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| 88 |
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| 89 | break;
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| 90 | }
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| 91 |
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| 92 | list_del_init(&fence->list);
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| 93 | host1x_fence_signal(fence);
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| 94 | }
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| 95 |
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| 96 | |
| 97 | * Re-enable interrupt if necessary. The ISR already disabled the interrupt,
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| 98 | * so if no fences remain, no update is needed.
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| 99 |
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| 100 | if (!list_empty(&sp->fences.list))
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| 101 | host1x_intr_update_hw_state(host, sp);
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| 102 |
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| 103 | spin_unlock(&sp->fences.lock);
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| 104 | }
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| 105 |
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| 106 | int host1x_intr_init(struct host1x *host)
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| 107 | {
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| 108 | struct host1x_intr_irq_data *irq_data;
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| 109 | unsigned int id;
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| 110 | int i, err;
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| 111 |
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| 112 | for (id = 0; id < host1x_syncpt_nb_pts(host); ++id) {
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| 113 | struct host1x_syncpt *syncpt = &host->syncpt[id];
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| 114 |
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| 115 | spin_lock_init(&syncpt->fences.lock);
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| 116 | INIT_LIST_HEAD(&syncpt->fences.list);
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| 117 | }
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| 118 |
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| 119 | irq_data = devm_kcalloc(host->dev, host->num_syncpt_irqs, sizeof(irq_data[0]), GFP_KERNEL);
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| 120 | if (!irq_data)
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| 121 | return -ENOMEM;
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| 122 |
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| 123 | host1x_hw_intr_disable_all_syncpt_intrs(host);
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| 124 |
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| 125 | for (i = 0; i < host->num_syncpt_irqs; i++) {
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| 126 | irq_data[i].host = host;
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| 127 | irq_data[i].offset = i;
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| 128 |
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| 129 | err = devm_request_irq(host->dev, host->syncpt_irqs[i],
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| 130 | host->intr_op->isr, IRQF_SHARED,
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| 131 | "host1x_syncpt", &irq_data[i]);
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| 132 | if (err < 0)
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| 133 | return err;
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| 134 | }
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| 135 |
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| 136 | return 0;
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| 137 | }
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| 138 |
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| 139 | void host1x_intr_deinit(struct host1x *host)
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| 140 | {
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| 141 | }
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| 142 |
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| 143 | void host1x_intr_start(struct host1x *host)
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| 144 | {
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| 145 | u32 hz = clk_get_rate(host->clk);
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| 146 | int err;
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| 147 |
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| 148 | mutex_lock(&host->intr_mutex);
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| 149 | err = host1x_hw_intr_init_host_sync(host, DIV_ROUND_UP(hz, 1000000));
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| 150 | if (err) {
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| 151 | mutex_unlock(&host->intr_mutex);
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| 152 | return;
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| 153 | }
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| 154 | mutex_unlock(&host->intr_mutex);
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| 155 | }
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| 156 |
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| 157 | void host1x_intr_stop(struct host1x *host)
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| 158 | {
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| 159 | host1x_hw_intr_disable_all_syncpt_intrs(host);
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| 160 | }
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