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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * coretemp.c - Linux kernel module for hardware monitoring
4 *
5 * Copyright (C) 2007 Rudolf Marek <[email protected]>
6 *
7 * Inspired from many hwmon drivers
8 */
9
10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/jiffies.h>
16#include <linux/hwmon.h>
17#include <linux/sysfs.h>
18#include <linux/hwmon-sysfs.h>
19#include <linux/err.h>
20#include <linux/mutex.h>
21#include <linux/list.h>
22#include <linux/platform_device.h>
23#include <linux/cpu.h>
24#include <linux/smp.h>
25#include <linux/moduleparam.h>
26#include <linux/pci.h>
27#include <asm/msr.h>
28#include <linux/processor.h>
29#include <asm/cpu_device_id.h>
30#include <linux/sched/isolation.h>
31
32#define DRVNAME "coretemp"
33
34/*
35 * force_tjmax only matters when TjMax can't be read from the CPU itself.
36 * When set, it replaces the driver's suboptimal heuristic.
37 */
38static int force_tjmax;
39module_param_named(tjmax, force_tjmax, int, 0444);
40MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius");
41
42#define CORETEMP_NAME_LENGTH 28 /* String Length of attrs */
43
44enum coretemp_attr_index {
45 ATTR_LABEL,
46 ATTR_CRIT_ALARM,
47 ATTR_TEMP,
48 ATTR_TJMAX,
49 ATTR_TTARGET,
50 MAX_CORE_ATTRS = ATTR_TJMAX + 1, /* Maximum no of basic attrs */
51 TOTAL_ATTRS = ATTR_TTARGET + 1 /* Maximum no of possible attrs */
52};
53
54#ifdef CONFIG_SMP
55#define for_each_sibling(i, cpu) \
56 for_each_cpu(i, topology_sibling_cpumask(cpu))
57#else
58#define for_each_sibling(i, cpu) for (i = 0; false; )
59#endif
60
61/*
62 * Per-Core Temperature Data
63 * @tjmax: The static tjmax value when tjmax cannot be retrieved from
64 * IA32_TEMPERATURE_TARGET MSR.
65 * @last_updated: The time when the current temperature value was updated
66 * earlier (in jiffies).
67 * @cpu_core_id: The CPU Core from which temperature values should be read
68 * This value is passed as "id" field to rdmsr/wrmsr functions.
69 * @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS,
70 * from where the temperature values should be read.
71 * @attr_size: Number of sysfs attributes in this temperature data group.
72 */
73struct temp_data {
74 int temp;
75 int tjmax;
76 unsigned long last_updated;
77 unsigned int cpu;
78 int index;
79 u32 cpu_core_id;
80 u32 status_reg;
81 int attr_size;
82 struct device_attribute sd_attrs[TOTAL_ATTRS];
83 char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH];
84 struct attribute *attrs[TOTAL_ATTRS + 1];
85 struct attribute_group attr_group;
86 struct mutex update_lock;
87};
88
89/* Platform Data per Physical CPU */
90struct platform_data {
91 struct device *hwmon_dev;
92 u16 pkg_id;
93 int nr_cores;
94 struct ida ida;
95 struct cpumask cpumask;
96 struct temp_data *pkg_data;
97 struct temp_data **core_data;
98 struct device_attribute name_attr;
99};
100
101struct tjmax_pci {
102 unsigned int device;
103 int tjmax;
104};
105
106static const struct tjmax_pci tjmax_pci_table[] = {
107 { 0x0708, 110000 }, /* CE41x0 (Sodaville ) */
108 { 0x0c72, 102000 }, /* Atom S1240 (Centerton) */
109 { 0x0c73, 95000 }, /* Atom S1220 (Centerton) */
110 { 0x0c75, 95000 }, /* Atom S1260 (Centerton) */
111};
112
113struct tjmax {
114 char const *id;
115 int tjmax;
116};
117
118static const struct tjmax tjmax_table[] = {
119 { "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */
120 { "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */
121};
122
123struct tjmax_model {
124 u32 vfm;
125 u8 stepping_mask;
126 int tjmax;
127};
128
129#define ANY 0xff
130
131static const struct tjmax_model tjmax_model_table[] = {
132 { INTEL_ATOM_BONNELL, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */
133 { INTEL_ATOM_BONNELL, ANY, 90000 }, /* Z5xx, N2xx, possibly others
134 * Note: Also matches 230 and 330,
135 * which are covered by tjmax_table
136 */
137 { INTEL_ATOM_BONNELL_MID, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx)
138 * Note: TjMax for E6xxT is 110C, but CPU
139 * type is undetectable by software
140 */
141 { INTEL_ATOM_SALTWELL_MID, ANY, 90000 }, /* Atom Medfield (Z2460) */
142 { INTEL_ATOM_SALTWELL_TABLET, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */
143 { INTEL_ATOM_SALTWELL, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx)
144 * Also matches S12x0 (stepping 9), covered
145 * by PCI table
146 */
147 { INTEL_ATOM_SILVERMONT, 9, 110000 }, /* Atom Bay Trail E38xx (embedded) */
148 { INTEL_ATOM_SILVERMONT, ANY, 90000 }, /* Atom Bay Trail Z37xx (tablet) */
149 { INTEL_ATOM_SILVERMONT_MID, ANY, 90000 }, /* Atom Merrifield (Z34xx) */
150 { INTEL_ATOM_SILVERMONT_MID2, ANY, 90000 }, /* Atom Moorefield (Z35xx) */
151 { INTEL_ATOM_AIRMONT, ANY, 90000 }, /* Atom Cherry Trail (Z8xxx) */
152 { INTEL_ATOM_GOLDMONT, ANY, 105000 }, /* Atom Apollo Lake (J3xxx, N3xxx, E39xx) */
153 { INTEL_ATOM_GOLDMONT_PLUS, ANY, 105000 }, /* Atom Gemini Lake (J4xxx, N4xxx, N5xxx) */
154 { INTEL_ATOM_TREMONT, ANY, 105000 }, /* Atom Elkhart Lake */
155 { INTEL_ATOM_TREMONT_L, ANY, 105000 }, /* Atom Jasper Lake */
156};
157
158static bool is_pkg_temp_data(struct temp_data *tdata)
159{
160 return tdata->index < 0;
161}
162
163static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
164{
165 /* The 100C is default for both mobile and non mobile CPUs */
166
167 int tjmax = 100000;
168 int tjmax_ee = 85000;
169 int usemsr_ee = 1;
170 int err;
171 u64 val;
172 int i;
173 u16 devfn = PCI_DEVFN(0, 0);
174 struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn);
175
176 /*
177 * Explicit tjmax table entries override heuristics.
178 * First try PCI host bridge IDs, followed by model ID strings
179 * and model/stepping information.
180 */
181 if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) {
182 for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) {
183 if (host_bridge->device == tjmax_pci_table[i].device) {
184 pci_dev_put(host_bridge);
185 return tjmax_pci_table[i].tjmax;
186 }
187 }
188 }
189 pci_dev_put(host_bridge);
190
191 /*
192 * This is literally looking for "CPU XXX" in the model string.
193 * Not checking it against the model as well. Just purely a
194 * string search.
195 */
196 for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) {
197 if (strstr(c->x86_model_id, tjmax_table[i].id))
198 return tjmax_table[i].tjmax;
199 }
200
201 for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
202 const struct tjmax_model *tm = &tjmax_model_table[i];
203
204 if (c->x86_vfm == tm->vfm &&
205 (tm->stepping_mask == ANY ||
206 tm->stepping_mask == c->x86_stepping))
207 return tm->tjmax;
208 }
209
210 /* Early chips have no MSR for TjMax */
211
212 if (c->x86_vfm == INTEL_CORE2_MEROM && c->x86_stepping < 4)
213 usemsr_ee = 0;
214
215 if (c->x86_vfm > INTEL_CORE_YONAH && usemsr_ee) {
216 u8 platform_id;
217
218 /*
219 * Now we can detect the mobile CPU using Intel provided table
220 * http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
221 * For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
222 */
223 err = rdmsrq_safe_on_cpu(id, 0x17, &val);
224 if (err) {
225 dev_warn(dev,
226 "Unable to access MSR 0x17, assuming desktop CPU\n");
227 usemsr_ee = 0;
228 } else if (c->x86_vfm < INTEL_CORE2_PENRYN &&
229 !(val & 0x10000000)) {
230 /*
231 * Trust bit 28 up to Penryn, I could not find any
232 * documentation on that; if you happen to know
233 * someone at Intel please ask
234 */
235 usemsr_ee = 0;
236 } else {
237 /* Platform ID bits 52:50 */
238 platform_id = (val >> 50) & 0x7;
239
240 /*
241 * Mobile Penryn CPU seems to be platform ID 7 or 5
242 * (guesswork)
243 */
244 if (c->x86_vfm == INTEL_CORE2_PENRYN &&
245 (platform_id == 5 || platform_id == 7)) {
246 /*
247 * If MSR EE bit is set, set it to 90 degrees C,
248 * otherwise 105 degrees C
249 */
250 tjmax_ee = 90000;
251 tjmax = 105000;
252 }
253 }
254 }
255
256 if (usemsr_ee) {
257 err = rdmsrq_safe_on_cpu(id, 0xee, &val);
258 if (err) {
259 dev_warn(dev,
260 "Unable to access MSR 0xEE, for Tjmax, left at default\n");
261 } else if (val & 0x40000000) {
262 tjmax = tjmax_ee;
263 }
264 } else if (tjmax == 100000) {
265 /*
266 * If we don't use msr EE it means we are desktop CPU
267 * (with exeception of Atom)
268 */
269 dev_warn(dev, "Using relative temperature scale!\n");
270 }
271
272 return tjmax;
273}
274
275static int get_tjmax(struct temp_data *tdata, struct device *dev)
276{
277 struct cpuinfo_x86 *c = &cpu_data(tdata->cpu);
278 int err;
279 u64 msrval;
280 u32 val;
281
282 /* use static tjmax once it is set */
283 if (tdata->tjmax)
284 return tdata->tjmax;
285
286 /*
287 * A new feature of current Intel(R) processors, the
288 * IA32_TEMPERATURE_TARGET contains the TjMax value
289 */
290 err = rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &msrval);
291 if (err) {
292 dev_warn_once(dev, "Unable to read TjMax from CPU %u\n", tdata->cpu);
293 } else {
294 val = (msrval >> 16) & 0xff;
295 if (val)
296 return val * 1000;
297 }
298
299 if (force_tjmax) {
300 dev_notice(dev, "TjMax forced to %d degrees C by user\n",
301 force_tjmax);
302 tdata->tjmax = force_tjmax * 1000;
303 } else {
304 /*
305 * An assumption is made for early CPUs and unreadable MSR.
306 * NOTE: the calculated value may not be correct.
307 */
308 tdata->tjmax = adjust_tjmax(c, tdata->cpu, dev);
309 }
310 return tdata->tjmax;
311}
312
313static int get_ttarget(struct temp_data *tdata, struct device *dev)
314{
315 u64 val;
316 int tjmax, ttarget_offset, ret;
317
318 /*
319 * ttarget is valid only if tjmax can be retrieved from
320 * MSR_IA32_TEMPERATURE_TARGET
321 */
322 if (tdata->tjmax)
323 return -ENODEV;
324
325 ret = rdmsrq_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &val);
326 if (ret)
327 return ret;
328
329 tjmax = (val >> 16) & 0xff;
330
331 /* Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. */
332 ttarget_offset = (val >> 8) & 0xff;
333
334 return (tjmax - ttarget_offset) * 1000;
335}
336
337/* Keep track of how many zone pointers we allocated in init() */
338static int max_zones __read_mostly;
339/* Array of zone pointers. Serialized by cpu hotplug lock */
340static struct platform_device **zone_devices;
341
342static ssize_t show_label(struct device *dev,
343 struct device_attribute *devattr, char *buf)
344{
345 struct platform_data *pdata = dev_get_drvdata(dev);
346 struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_LABEL]);
347
348 if (is_pkg_temp_data(tdata))
349 return sprintf(buf, "Package id %u\n", pdata->pkg_id);
350
351 return sprintf(buf, "Core %u\n", tdata->cpu_core_id);
352}
353
354static ssize_t show_crit_alarm(struct device *dev,
355 struct device_attribute *devattr, char *buf)
356{
357 struct msr val;
358 struct temp_data *tdata = container_of(devattr, struct temp_data,
359 sd_attrs[ATTR_CRIT_ALARM]);
360
361 mutex_lock(&tdata->update_lock);
362 rdmsrq_on_cpu(tdata->cpu, tdata->status_reg, &val.q);
363 mutex_unlock(&tdata->update_lock);
364
365 return sprintf(buf, "%d\n", (val.l >> 5) & 1);
366}
367
368static ssize_t show_tjmax(struct device *dev,
369 struct device_attribute *devattr, char *buf)
370{
371 struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TJMAX]);
372 int tjmax;
373
374 mutex_lock(&tdata->update_lock);
375 tjmax = get_tjmax(tdata, dev);
376 mutex_unlock(&tdata->update_lock);
377
378 return sprintf(buf, "%d\n", tjmax);
379}
380
381static ssize_t show_ttarget(struct device *dev,
382 struct device_attribute *devattr, char *buf)
383{
384 struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TTARGET]);
385 int ttarget;
386
387 mutex_lock(&tdata->update_lock);
388 ttarget = get_ttarget(tdata, dev);
389 mutex_unlock(&tdata->update_lock);
390
391 if (ttarget < 0)
392 return ttarget;
393 return sprintf(buf, "%d\n", ttarget);
394}
395
396static ssize_t show_temp(struct device *dev,
397 struct device_attribute *devattr, char *buf)
398{
399 struct msr val;
400 struct temp_data *tdata = container_of(devattr, struct temp_data, sd_attrs[ATTR_TEMP]);
401 int tjmax;
402
403 mutex_lock(&tdata->update_lock);
404
405 tjmax = get_tjmax(tdata, dev);
406 /* Check whether the time interval has elapsed */
407 if (time_after(jiffies, tdata->last_updated + HZ)) {
408 rdmsrq_on_cpu(tdata->cpu, tdata->status_reg, &val.q);
409 /*
410 * Ignore the valid bit. In all observed cases the register
411 * value is either low or zero if the valid bit is 0.
412 * Return it instead of reporting an error which doesn't
413 * really help at all.
414 */
415 tdata->temp = tjmax - ((val.l >> 16) & 0xff) * 1000;
416 tdata->last_updated = jiffies;
417 }
418
419 mutex_unlock(&tdata->update_lock);
420 return sprintf(buf, "%d\n", tdata->temp);
421}
422
423static int create_core_attrs(struct temp_data *tdata, struct device *dev)
424{
425 static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev,
426 struct device_attribute *devattr, char *buf) = {
427 show_label, show_crit_alarm, show_temp, show_tjmax,
428 show_ttarget };
429 static const char *const suffixes[TOTAL_ATTRS] = {
430 "label", "crit_alarm", "input", "crit", "max"
431 };
432 int i;
433
434 for (i = 0; i < tdata->attr_size; i++) {
435 /*
436 * We map the attr number to core id of the CPU
437 * The attr number is always core id + 2
438 * The Pkgtemp will always show up as temp1_*, if available
439 */
440 int attr_no = is_pkg_temp_data(tdata) ? 1 : tdata->cpu_core_id + 2;
441
442 snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH,
443 "temp%d_%s", attr_no, suffixes[i]);
444 sysfs_attr_init(&tdata->sd_attrs[i].attr);
445 tdata->sd_attrs[i].attr.name = tdata->attr_name[i];
446 tdata->sd_attrs[i].attr.mode = 0444;
447 tdata->sd_attrs[i].show = rd_ptr[i];
448 tdata->attrs[i] = &tdata->sd_attrs[i].attr;
449 }
450 tdata->attr_group.attrs = tdata->attrs;
451 return sysfs_create_group(&dev->kobj, &tdata->attr_group);
452}
453
454static int chk_ucode_version(unsigned int cpu)
455{
456 struct cpuinfo_x86 *c = &cpu_data(cpu);
457
458 /*
459 * Check if we have problem with errata AE18 of Core processors:
460 * Readings might stop update when processor visited too deep sleep,
461 * fixed for stepping D0 (6EC).
462 */
463 if (c->x86_vfm == INTEL_CORE_YONAH && c->x86_stepping < 0xc && c->microcode < 0x39) {
464 pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n");
465 return -ENODEV;
466 }
467 return 0;
468}
469
470static struct platform_device *coretemp_get_pdev(unsigned int cpu)
471{
472 int id = topology_logical_die_id(cpu);
473
474 if (id >= 0 && id < max_zones)
475 return zone_devices[id];
476 return NULL;
477}
478
479static struct temp_data *
480init_temp_data(struct platform_data *pdata, unsigned int cpu, int pkg_flag)
481{
482 struct temp_data *tdata;
483
484 if (!pdata->core_data) {
485 pdata->nr_cores = topology_num_cores_per_package();
486 pdata->core_data = kzalloc_objs(struct temp_data *,
487 pdata->nr_cores);
488 if (!pdata->core_data)
489 return NULL;
490 }
491
492 tdata = kzalloc_obj(struct temp_data);
493 if (!tdata)
494 return NULL;
495
496 if (pkg_flag) {
497 pdata->pkg_data = tdata;
498 /* Use tdata->index as indicator of package temp data */
499 tdata->index = -1;
500 } else {
501 tdata->index = ida_alloc_max(&pdata->ida, pdata->nr_cores - 1, GFP_KERNEL);
502 if (tdata->index < 0) {
503 kfree(tdata);
504 return NULL;
505 }
506 pdata->core_data[tdata->index] = tdata;
507 }
508
509 tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS :
510 MSR_IA32_THERM_STATUS;
511 tdata->cpu = cpu;
512 tdata->cpu_core_id = topology_core_id(cpu);
513 tdata->attr_size = MAX_CORE_ATTRS;
514 mutex_init(&tdata->update_lock);
515 return tdata;
516}
517
518static void destroy_temp_data(struct platform_data *pdata, struct temp_data *tdata)
519{
520 if (is_pkg_temp_data(tdata)) {
521 pdata->pkg_data = NULL;
522 kfree(pdata->core_data);
523 pdata->core_data = NULL;
524 pdata->nr_cores = 0;
525 } else {
526 pdata->core_data[tdata->index] = NULL;
527 ida_free(&pdata->ida, tdata->index);
528 }
529 kfree(tdata);
530}
531
532static struct temp_data *get_temp_data(struct platform_data *pdata, int cpu)
533{
534 int i;
535
536 /* cpu < 0 means get pkg temp_data */
537 if (cpu < 0)
538 return pdata->pkg_data;
539
540 for (i = 0; i < pdata->nr_cores; i++) {
541 if (pdata->core_data[i] &&
542 pdata->core_data[i]->cpu_core_id == topology_core_id(cpu))
543 return pdata->core_data[i];
544 }
545 return NULL;
546}
547
548static int create_core_data(struct platform_device *pdev, unsigned int cpu,
549 int pkg_flag)
550{
551 struct temp_data *tdata;
552 struct platform_data *pdata = platform_get_drvdata(pdev);
553 struct cpuinfo_x86 *c = &cpu_data(cpu);
554 u64 val;
555 int err;
556
557 if (!housekeeping_cpu(cpu, HK_TYPE_MISC))
558 return 0;
559
560 tdata = init_temp_data(pdata, cpu, pkg_flag);
561 if (!tdata)
562 return -ENOMEM;
563
564 /* Test if we can access the status register */
565 err = rdmsrq_safe_on_cpu(cpu, tdata->status_reg, &val);
566 if (err)
567 goto err;
568
569 /* Make sure tdata->tjmax is a valid indicator for dynamic/static tjmax */
570 get_tjmax(tdata, &pdev->dev);
571
572 /*
573 * The target temperature is available on older CPUs but not in the
574 * MSR_IA32_TEMPERATURE_TARGET register. Atoms don't have the register
575 * at all.
576 */
577 if (c->x86_vfm > INTEL_CORE_YONAH && c->x86_vfm != INTEL_ATOM_BONNELL)
578 if (get_ttarget(tdata, &pdev->dev) >= 0)
579 tdata->attr_size++;
580
581 /* Create sysfs interfaces */
582 err = create_core_attrs(tdata, pdata->hwmon_dev);
583 if (err)
584 goto err;
585
586 return 0;
587
588err:
589 destroy_temp_data(pdata, tdata);
590 return err;
591}
592
593static void
594coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag)
595{
596 if (create_core_data(pdev, cpu, pkg_flag))
597 dev_err(&pdev->dev, "Adding Core %u failed\n", cpu);
598}
599
600static void coretemp_remove_core(struct platform_data *pdata, struct temp_data *tdata)
601{
602 /* if we errored on add then this is already gone */
603 if (!tdata)
604 return;
605
606 /* Remove the sysfs attributes */
607 sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group);
608
609 destroy_temp_data(pdata, tdata);
610}
611
612static int coretemp_device_add(int zoneid)
613{
614 struct platform_device *pdev;
615 struct platform_data *pdata;
616 int err;
617
618 /* Initialize the per-zone data structures */
619 pdata = kzalloc_obj(*pdata);
620 if (!pdata)
621 return -ENOMEM;
622
623 pdata->pkg_id = zoneid;
624 ida_init(&pdata->ida);
625
626 pdev = platform_device_alloc(DRVNAME, zoneid);
627 if (!pdev) {
628 err = -ENOMEM;
629 goto err_free_pdata;
630 }
631
632 err = platform_device_add(pdev);
633 if (err)
634 goto err_put_dev;
635
636 platform_set_drvdata(pdev, pdata);
637 zone_devices[zoneid] = pdev;
638 return 0;
639
640err_put_dev:
641 platform_device_put(pdev);
642err_free_pdata:
643 kfree(pdata);
644 return err;
645}
646
647static void coretemp_device_remove(int zoneid)
648{
649 struct platform_device *pdev = zone_devices[zoneid];
650 struct platform_data *pdata = platform_get_drvdata(pdev);
651
652 ida_destroy(&pdata->ida);
653 kfree(pdata->core_data);
654 kfree(pdata);
655 platform_device_unregister(pdev);
656}
657
658static int coretemp_cpu_online(unsigned int cpu)
659{
660 struct platform_device *pdev = coretemp_get_pdev(cpu);
661 struct cpuinfo_x86 *c = &cpu_data(cpu);
662 struct platform_data *pdata;
663
664 /*
665 * Don't execute this on resume as the offline callback did
666 * not get executed on suspend.
667 */
668 if (cpuhp_tasks_frozen)
669 return 0;
670
671 /*
672 * CPUID.06H.EAX[0] indicates whether the CPU has thermal
673 * sensors. We check this bit only, all the early CPUs
674 * without thermal sensors will be filtered out.
675 */
676 if (!cpu_has(c, X86_FEATURE_DTHERM))
677 return -ENODEV;
678
679 pdata = platform_get_drvdata(pdev);
680 if (!pdata->hwmon_dev) {
681 struct device *hwmon;
682
683 /* Check the microcode version of the CPU */
684 if (chk_ucode_version(cpu))
685 return -EINVAL;
686
687 /*
688 * Alright, we have DTS support.
689 * We are bringing the _first_ core in this pkg
690 * online. So, initialize per-pkg data structures and
691 * then bring this core online.
692 */
693 hwmon = hwmon_device_register_with_groups(&pdev->dev, DRVNAME,
694 pdata, NULL);
695 if (IS_ERR(hwmon))
696 return PTR_ERR(hwmon);
697 pdata->hwmon_dev = hwmon;
698
699 /*
700 * Check whether pkgtemp support is available.
701 * If so, add interfaces for pkgtemp.
702 */
703 if (cpu_has(c, X86_FEATURE_PTS))
704 coretemp_add_core(pdev, cpu, 1);
705 }
706
707 /*
708 * Check whether a thread sibling is already online. If not add the
709 * interface for this CPU core.
710 */
711 if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu)))
712 coretemp_add_core(pdev, cpu, 0);
713
714 cpumask_set_cpu(cpu, &pdata->cpumask);
715 return 0;
716}
717
718static int coretemp_cpu_offline(unsigned int cpu)
719{
720 struct platform_device *pdev = coretemp_get_pdev(cpu);
721 struct platform_data *pd;
722 struct temp_data *tdata;
723 int target;
724
725 /* No need to tear down any interfaces for suspend */
726 if (cpuhp_tasks_frozen)
727 return 0;
728
729 /* If the physical CPU device does not exist, just return */
730 pd = platform_get_drvdata(pdev);
731 if (!pd->hwmon_dev)
732 return 0;
733
734 tdata = get_temp_data(pd, cpu);
735
736 cpumask_clear_cpu(cpu, &pd->cpumask);
737
738 /*
739 * If this is the last thread sibling, remove the CPU core
740 * interface, If there is still a sibling online, transfer the
741 * target cpu of that core interface to it.
742 */
743 target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu));
744 if (target >= nr_cpu_ids) {
745 coretemp_remove_core(pd, tdata);
746 } else if (tdata && tdata->cpu == cpu) {
747 mutex_lock(&tdata->update_lock);
748 tdata->cpu = target;
749 mutex_unlock(&tdata->update_lock);
750 }
751
752 /*
753 * If all cores in this pkg are offline, remove the interface.
754 */
755 tdata = get_temp_data(pd, -1);
756 if (cpumask_empty(&pd->cpumask)) {
757 if (tdata)
758 coretemp_remove_core(pd, tdata);
759 hwmon_device_unregister(pd->hwmon_dev);
760 pd->hwmon_dev = NULL;
761 return 0;
762 }
763
764 /*
765 * Check whether this core is the target for the package
766 * interface. We need to assign it to some other cpu.
767 */
768 if (tdata && tdata->cpu == cpu) {
769 target = cpumask_first(&pd->cpumask);
770 mutex_lock(&tdata->update_lock);
771 tdata->cpu = target;
772 mutex_unlock(&tdata->update_lock);
773 }
774 return 0;
775}
776
777static const struct x86_cpu_id coretemp_ids[] __initconst = {
778 X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_DTHERM, NULL),
779 {}
780};
781MODULE_DEVICE_TABLE(x86cpu, coretemp_ids);
782
783static enum cpuhp_state coretemp_hp_online;
784
785static int __init coretemp_init(void)
786{
787 int i, err;
788
789 /*
790 * CPUID.06H.EAX[0] indicates whether the CPU has thermal
791 * sensors. We check this bit only, all the early CPUs
792 * without thermal sensors will be filtered out. This
793 * includes all the Family 5 and Family 15 (Pentium 4)
794 * models, since they never set the CPUID bit.
795 */
796 if (!x86_match_cpu(coretemp_ids))
797 return -ENODEV;
798
799 max_zones = topology_max_packages() * topology_max_dies_per_package();
800 zone_devices = kzalloc_objs(struct platform_device *, max_zones);
801 if (!zone_devices)
802 return -ENOMEM;
803
804 for (i = 0; i < max_zones; i++) {
805 err = coretemp_device_add(i);
806 if (err)
807 goto outzone;
808 }
809
810 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online",
811 coretemp_cpu_online, coretemp_cpu_offline);
812 if (err < 0)
813 goto outzone;
814 coretemp_hp_online = err;
815 return 0;
816
817outzone:
818 while (i--)
819 coretemp_device_remove(i);
820 kfree(zone_devices);
821 return err;
822}
823module_init(coretemp_init)
824
825static void __exit coretemp_exit(void)
826{
827 int i;
828
829 cpuhp_remove_state(coretemp_hp_online);
830 for (i = 0; i < max_zones; i++)
831 coretemp_device_remove(i);
832 kfree(zone_devices);
833}
834module_exit(coretemp_exit)
835
836MODULE_AUTHOR("Rudolf Marek <[email protected]>");
837MODULE_DESCRIPTION("Intel Core temperature monitor");
838MODULE_LICENSE("GPL");