projects/linux·blob master · refs

965 lines · 27.0 KiB

1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * HWMON driver for Microchip EMC1812/13/14/15/33 Multichannel high-accuracy
4 * 2-wire low-voltage remote diode temperature monitor family.
5 *
6 * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries
7 *
8 * Author: Marius Cristea <[email protected]>
9 *
10 * Datasheet can be found here:
11 * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/EMC1812-3-4-5-33-Data-Sheet-DS20005751.pdf
12 */
13
14#include <linux/bitfield.h>
15#include <linux/bitops.h>
16#include <linux/bits.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/hwmon.h>
20#include <linux/i2c.h>
21#include <linux/kernel.h>
22#include <linux/math64.h>
23#include <linux/property.h>
24#include <linux/regmap.h>
25#include <linux/string.h>
26#include <linux/units.h>
27#include <linux/util_macros.h>
28
29/* EMC1812 Registers Addresses */
30#define EMC1812_STATUS_ADDR 0x02
31#define EMC1812_CONFIG_LO_ADDR 0x03
32
33#define EMC1812_CFG_ADDR 0x09
34#define EMC1812_CONV_ADDR 0x0A
35#define EMC1812_INT_DIODE_HIGH_LIMIT_ADDR 0x0B
36#define EMC1812_INT_DIODE_LOW_LIMIT_ADDR 0x0C
37#define EMC1812_EXT1_HIGH_LIMIT_HIGH_BYTE_ADDR 0x0D
38#define EMC1812_EXT1_LOW_LIMIT_HIGH_BYTE_ADDR 0x0E
39#define EMC1812_ONE_SHOT_ADDR 0x0F
40
41#define EMC1812_EXT1_HIGH_LIMIT_LOW_BYTE_ADDR 0x13
42#define EMC1812_EXT1_LOW_LIMIT_LOW_BYTE_ADDR 0x14
43#define EMC1812_EXT2_HIGH_LIMIT_HIGH_BYTE_ADDR 0x15
44#define EMC1812_EXT2_LOW_LIMIT_HIGH_BYTE_ADDR 0x16
45#define EMC1812_EXT2_HIGH_LIMIT_LOW_BYTE_ADDR 0x17
46#define EMC1812_EXT2_LOW_LIMIT_LOW_BYTE_ADDR 0x18
47#define EMC1812_EXT1_THERM_LIMIT_ADDR 0x19
48#define EMC1812_EXT2_THERM_LIMIT_ADDR 0x1A
49#define EMC1812_EXT_DIODE_FAULT_STATUS_ADDR 0x1B
50
51#define EMC1812_DIODE_FAULT_MASK_ADDR 0x1F
52#define EMC1812_INT_DIODE_THERM_LIMIT_ADDR 0x20
53#define EMC1812_THRM_HYS_ADDR 0x21
54#define EMC1812_CONSEC_ALERT_ADDR 0x22
55
56#define EMC1812_EXT1_BETA_CONFIG_ADDR 0x25
57#define EMC1812_EXT2_BETA_CONFIG_ADDR 0x26
58#define EMC1812_EXT1_IDEALITY_FACTOR_ADDR 0x27
59#define EMC1812_EXT2_IDEALITY_FACTOR_ADDR 0x28
60
61#define EMC1812_EXT3_HIGH_LIMIT_HIGH_BYTE_ADDR 0x2C
62#define EMC1812_EXT3_LOW_LIMIT_HIGH_BYTE_ADDR 0x2D
63#define EMC1812_EXT3_HIGH_LIMIT_LOW_BYTE_ADDR 0x2E
64#define EMC1812_EXT3_LOW_LIMIT_LOW_BYTE_ADDR 0x2F
65#define EMC1812_EXT3_THERM_LIMIT_ADDR 0x30
66#define EMC1812_EXT3_IDEALITY_FACTOR_ADDR 0x31
67
68#define EMC1812_EXT4_HIGH_LIMIT_HIGH_BYTE_ADDR 0x34
69#define EMC1812_EXT4_LOW_LIMIT_HIGH_BYTE_ADDR 0x35
70#define EMC1812_EXT4_HIGH_LIMIT_LOW_BYTE_ADDR 0x36
71#define EMC1812_EXT4_LOW_LIMIT_LOW_BYTE_ADDR 0x37
72#define EMC1812_EXT4_THERM_LIMIT_ADDR 0x38
73#define EMC1812_EXT4_IDEALITY_FACTOR_ADDR 0x39
74#define EMC1812_HIGH_LIMIT_STATUS_ADDR 0x3A
75#define EMC1812_LOW_LIMIT_STATUS_ADDR 0x3B
76#define EMC1812_THERM_LIMIT_STATUS_ADDR 0x3C
77#define EMC1812_ROC_GAIN_ADDR 0x3D
78#define EMC1812_ROC_CONFIG_ADDR 0x3E
79#define EMC1812_ROC_STATUS_ADDR 0x3F
80#define EMC1812_R1_RESH_ADDR 0x40
81#define EMC1812_R1_LIMH_ADDR 0x41
82#define EMC1812_R1_LIML_ADDR 0x42
83#define EMC1812_R1_SMPL_ADDR 0x43
84#define EMC1812_R2_RESH_ADDR 0x44
85#define EMC1812_R2_3_RESL_ADDR 0x45
86#define EMC1812_R2_LIMH_ADDR 0x46
87#define EMC1812_R2_LIML_ADDR 0x47
88#define EMC1812_R2_SMPL_ADDR 0x48
89#define EMC1812_PER_MAXTH_1_ADDR 0x49
90#define EMC1812_PER_MAXT1L_ADDR 0x4A
91#define EMC1812_PER_MAXTH_2_ADDR 0x4B
92#define EMC1812_PER_MAXT2_3L_ADDR 0x4C
93#define EMC1812_GBL_MAXT1H_ADDR 0x4D
94#define EMC1812_GBL_MAXT1L_ADDR 0x4E
95#define EMC1812_GBL_MAXT2H_ADDR 0x4F
96#define EMC1812_GBL_MAXT2L_ADDR 0x50
97#define EMC1812_FILTER_SEL_ADDR 0x51
98
99#define EMC1812_INT_HIGH_BYTE_ADDR 0x60
100#define EMC1812_INT_LOW_BYTE_ADDR 0x61
101#define EMC1812_EXT1_HIGH_BYTE_ADDR 0x62
102#define EMC1812_EXT1_LOW_BYTE_ADDR 0x63
103#define EMC1812_EXT2_HIGH_BYTE_ADDR 0x64
104#define EMC1812_EXT2_LOW_BYTE_ADDR 0x65
105#define EMC1812_EXT3_HIGH_BYTE_ADDR 0x66
106#define EMC1812_EXT3_LOW_BYTE_ADDR 0x67
107#define EMC1812_EXT4_HIGH_BYTE_ADDR 0x68
108#define EMC1812_EXT4_LOW_BYTE_ADDR 0x69
109#define EMC1812_HOTTEST_DIODE_HIGH_BYTE_ADDR 0x6A
110#define EMC1812_HOTTEST_DIODE_LOW_BYTE_ADDR 0x6B
111#define EMC1812_HOTTEST_STATUS_ADDR 0x6C
112#define EMC1812_HOTTEST_CFG_ADDR 0x6D
113
114#define EMC1812_PRODUCT_ID_ADDR 0xFD
115#define EMC1812_MANUFACTURER_ID_ADDR 0xFE
116#define EMC1812_REVISION_ADDR 0xFF
117
118/* EMC1812 Config Bits */
119#define EMC1812_CFG_MSKAL BIT(7)
120#define EMC1812_CFG_RS BIT(6)
121#define EMC1812_CFG_ATTHM BIT(5)
122#define EMC1812_CFG_RECD12 BIT(4)
123#define EMC1812_CFG_RECD34 BIT(3)
124#define EMC1812_CFG_RANGE BIT(2)
125#define EMC1812_CFG_DA_ENA BIT(1)
126#define EMC1812_CFG_APDD BIT(0)
127
128/* EMC1812 Status Bits */
129#define EMC1812_STATUS_ROCF BIT(7)
130#define EMC1812_STATUS_HOTCHG BIT(6)
131#define EMC1812_STATUS_BUSY BIT(5)
132#define EMC1812_STATUS_HIGH BIT(4)
133#define EMC1812_STATUS_LOW BIT(3)
134#define EMC1812_STATUS_FAULT BIT(2)
135#define EMC1812_STATUS_ETHRM BIT(1)
136#define EMC1812_STATUS_ITHRM BIT(0)
137
138#define EMC1812_BETA_LOCK_VAL 0x0F
139
140#define EMC1812_TEMP_CH_ADDR(index) (EMC1812_INT_HIGH_BYTE_ADDR + 2 * (index))
141
142#define EMC1812_FILTER_MASK_LEN 2
143
144#define EMC1812_PID 0x81
145#define EMC1813_PID 0x87
146#define EMC1814_PID 0x84
147#define EMC1815_PID 0x85
148#define EMC1833_PID 0x83
149
150/* The maximum number of channels a member of the family can have */
151#define EMC1812_MAX_NUM_CHANNELS 5
152#define EMC1812_TEMP_OFFSET 64
153
154#define EMC1812_DEFAULT_IDEALITY_FACTOR 0x12
155
156/* Constants and default values */
157#define EMC1812_HIGH_LIMIT_DEFAULT (85 + EMC1812_TEMP_OFFSET)
158
159#define EMC1812_TEMP_MASK (HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | \
160 HWMON_T_CRIT | HWMON_T_MAX_HYST | HWMON_T_CRIT_HYST | \
161 HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | \
162 HWMON_T_CRIT_ALARM | HWMON_T_LABEL)
163
164static const struct hwmon_channel_info * const emc1812_info[] = {
165 HWMON_CHANNEL_INFO(chip, HWMON_C_UPDATE_INTERVAL),
166 HWMON_CHANNEL_INFO(temp,
167 EMC1812_TEMP_MASK,
168 EMC1812_TEMP_MASK | HWMON_T_FAULT,
169 EMC1812_TEMP_MASK | HWMON_T_FAULT,
170 EMC1812_TEMP_MASK | HWMON_T_FAULT,
171 EMC1812_TEMP_MASK | HWMON_T_FAULT),
172 NULL
173};
174
175/**
176 * struct emc1812_features - features of a emc1812 instance
177 * @name: chip's name
178 * @phys_channels: number of physical channels supported by the chip
179 * @has_ext2_beta_reg: the EXT2_BETA register is available on the chip
180 */
181struct emc1812_features {
182 const char *name;
183 u8 phys_channels;
184 bool has_ext2_beta_reg;
185};
186
187static const struct emc1812_features emc1833_chip_config = {
188 .name = "emc1833",
189 .phys_channels = 3,
190 .has_ext2_beta_reg = true,
191};
192
193static const struct emc1812_features emc1812_chip_config = {
194 .name = "emc1812",
195 .phys_channels = 2,
196 .has_ext2_beta_reg = false,
197};
198
199static const struct emc1812_features emc1813_chip_config = {
200 .name = "emc1813",
201 .phys_channels = 3,
202 .has_ext2_beta_reg = true,
203};
204
205static const struct emc1812_features emc1814_chip_config = {
206 .name = "emc1814",
207 .phys_channels = 4,
208 .has_ext2_beta_reg = false,
209};
210
211static const struct emc1812_features emc1815_chip_config = {
212 .name = "emc1815",
213 .phys_channels = 5,
214 .has_ext2_beta_reg = false,
215};
216
217enum emc1812_limit_type {temp_min, temp_max};
218
219static const u8 emc1812_temp_map[] = {
220 [hwmon_temp_min] = temp_min,
221 [hwmon_temp_max] = temp_max,
222};
223
224static const u8 emc1812_ideality_regs[] = {
225 [0] = 0xff,
226 [1] = EMC1812_EXT1_IDEALITY_FACTOR_ADDR,
227 [2] = EMC1812_EXT2_IDEALITY_FACTOR_ADDR,
228 [3] = EMC1812_EXT3_IDEALITY_FACTOR_ADDR,
229 [4] = EMC1812_EXT4_IDEALITY_FACTOR_ADDR,
230};
231
232static const u8 emc1812_temp_crit_regs[] = {
233 [0] = EMC1812_INT_DIODE_THERM_LIMIT_ADDR,
234 [1] = EMC1812_EXT1_THERM_LIMIT_ADDR,
235 [2] = EMC1812_EXT2_THERM_LIMIT_ADDR,
236 [3] = EMC1812_EXT3_THERM_LIMIT_ADDR,
237 [4] = EMC1812_EXT4_THERM_LIMIT_ADDR,
238};
239
240static const u8 emc1812_limit_regs[][2] = {
241 [0] = {
242 [temp_min] = EMC1812_INT_DIODE_LOW_LIMIT_ADDR,
243 [temp_max] = EMC1812_INT_DIODE_HIGH_LIMIT_ADDR,
244 },
245 [1] = {
246 [temp_min] = EMC1812_EXT1_LOW_LIMIT_HIGH_BYTE_ADDR,
247 [temp_max] = EMC1812_EXT1_HIGH_LIMIT_HIGH_BYTE_ADDR,
248 },
249 [2] = {
250 [temp_min] = EMC1812_EXT2_LOW_LIMIT_HIGH_BYTE_ADDR,
251 [temp_max] = EMC1812_EXT2_HIGH_LIMIT_HIGH_BYTE_ADDR,
252 },
253 [3] = {
254 [temp_min] = EMC1812_EXT3_LOW_LIMIT_HIGH_BYTE_ADDR,
255 [temp_max] = EMC1812_EXT3_HIGH_LIMIT_HIGH_BYTE_ADDR,
256 },
257 [4] = {
258 [temp_min] = EMC1812_EXT4_LOW_LIMIT_HIGH_BYTE_ADDR,
259 [temp_max] = EMC1812_EXT4_HIGH_LIMIT_HIGH_BYTE_ADDR,
260 },
261};
262
263static const u8 emc1812_limit_regs_low[][2] = {
264 [0] = {
265 [temp_min] = 0xff,
266 [temp_max] = 0xff,
267 },
268 [1] = {
269 [temp_min] = EMC1812_EXT1_LOW_LIMIT_LOW_BYTE_ADDR,
270 [temp_max] = EMC1812_EXT1_HIGH_LIMIT_LOW_BYTE_ADDR,
271 },
272 [2] = {
273 [temp_min] = EMC1812_EXT2_LOW_LIMIT_LOW_BYTE_ADDR,
274 [temp_max] = EMC1812_EXT2_HIGH_LIMIT_LOW_BYTE_ADDR,
275 },
276 [3] = {
277 [temp_min] = EMC1812_EXT3_LOW_LIMIT_LOW_BYTE_ADDR,
278 [temp_max] = EMC1812_EXT3_HIGH_LIMIT_LOW_BYTE_ADDR,
279 },
280 [4] = {
281 [temp_min] = EMC1812_EXT4_LOW_LIMIT_LOW_BYTE_ADDR,
282 [temp_max] = EMC1812_EXT4_HIGH_LIMIT_LOW_BYTE_ADDR,
283 },
284};
285
286/* Lookup table for temperature conversion times in msec */
287static const u16 emc1812_conv_time[] = {
288 16000, 8000, 4000, 2000, 1000, 500, 250, 125, 62, 31, 16
289};
290
291/**
292 * struct emc1812_data - information about chip parameters
293 * @labels: labels of the channels
294 * @active_ch_mask: active channels
295 * @chip: pointer to structure holding chip features
296 * @regmap: device register map
297 * @recd34_en: state of Resistance Error Correction (REC) on channels 3 and 4
298 * @recd12_en: state of Resistance Error Correction (REC) on channels 1 and 2
299 * @apdd_en: state of anti-parallel diode mode
300 */
301struct emc1812_data {
302 const char *labels[EMC1812_MAX_NUM_CHANNELS];
303 unsigned long active_ch_mask;
304 const struct emc1812_features *chip;
305 struct regmap *regmap;
306 bool recd34_en;
307 bool recd12_en;
308 bool apdd_en;
309};
310
311/* emc1812 regmap configuration */
312static const struct regmap_range emc1812_regmap_writable_ranges[] = {
313 regmap_reg_range(EMC1812_CFG_ADDR, EMC1812_ONE_SHOT_ADDR),
314 regmap_reg_range(EMC1812_EXT1_HIGH_LIMIT_LOW_BYTE_ADDR, EMC1812_EXT2_THERM_LIMIT_ADDR),
315 regmap_reg_range(EMC1812_DIODE_FAULT_MASK_ADDR, EMC1812_CONSEC_ALERT_ADDR),
316 regmap_reg_range(EMC1812_EXT1_BETA_CONFIG_ADDR, EMC1812_EXT4_IDEALITY_FACTOR_ADDR),
317 regmap_reg_range(EMC1812_ROC_GAIN_ADDR, EMC1812_ROC_CONFIG_ADDR),
318 regmap_reg_range(EMC1812_R1_LIMH_ADDR, EMC1812_R1_SMPL_ADDR),
319 regmap_reg_range(EMC1812_R2_LIMH_ADDR, EMC1812_R2_SMPL_ADDR),
320 regmap_reg_range(EMC1812_FILTER_SEL_ADDR, EMC1812_FILTER_SEL_ADDR),
321 regmap_reg_range(EMC1812_HOTTEST_CFG_ADDR, EMC1812_HOTTEST_CFG_ADDR),
322};
323
324static const struct regmap_access_table emc1812_regmap_wr_table = {
325 .yes_ranges = emc1812_regmap_writable_ranges,
326 .n_yes_ranges = ARRAY_SIZE(emc1812_regmap_writable_ranges),
327};
328
329static const struct regmap_range emc1812_regmap_rd_ranges[] = {
330 regmap_reg_range(EMC1812_STATUS_ADDR, EMC1812_CONFIG_LO_ADDR),
331 regmap_reg_range(EMC1812_CFG_ADDR, EMC1812_ONE_SHOT_ADDR),
332 regmap_reg_range(EMC1812_EXT1_HIGH_LIMIT_LOW_BYTE_ADDR,
333 EMC1812_EXT_DIODE_FAULT_STATUS_ADDR),
334 regmap_reg_range(EMC1812_DIODE_FAULT_MASK_ADDR, EMC1812_CONSEC_ALERT_ADDR),
335 regmap_reg_range(EMC1812_EXT1_BETA_CONFIG_ADDR, EMC1812_FILTER_SEL_ADDR),
336 regmap_reg_range(EMC1812_INT_HIGH_BYTE_ADDR, EMC1812_HOTTEST_CFG_ADDR),
337 regmap_reg_range(EMC1812_PRODUCT_ID_ADDR, EMC1812_REVISION_ADDR),
338};
339
340static const struct regmap_access_table emc1812_regmap_rd_table = {
341 .yes_ranges = emc1812_regmap_rd_ranges,
342 .n_yes_ranges = ARRAY_SIZE(emc1812_regmap_rd_ranges),
343};
344
345static bool emc1812_is_volatile_reg(struct device *dev, unsigned int reg)
346{
347 switch (reg) {
348 case EMC1812_STATUS_ADDR:
349 case EMC1812_EXT_DIODE_FAULT_STATUS_ADDR:
350 case EMC1812_DIODE_FAULT_MASK_ADDR:
351 case EMC1812_EXT1_BETA_CONFIG_ADDR:
352 case EMC1812_EXT2_BETA_CONFIG_ADDR:
353 case EMC1812_HIGH_LIMIT_STATUS_ADDR:
354 case EMC1812_LOW_LIMIT_STATUS_ADDR:
355 case EMC1812_THERM_LIMIT_STATUS_ADDR:
356 case EMC1812_ROC_STATUS_ADDR:
357 case EMC1812_PER_MAXTH_1_ADDR:
358 case EMC1812_PER_MAXT1L_ADDR:
359 case EMC1812_PER_MAXTH_2_ADDR:
360 case EMC1812_PER_MAXT2_3L_ADDR:
361 case EMC1812_GBL_MAXT1H_ADDR:
362 case EMC1812_GBL_MAXT1L_ADDR:
363 case EMC1812_GBL_MAXT2H_ADDR:
364 case EMC1812_GBL_MAXT2L_ADDR:
365 case EMC1812_INT_HIGH_BYTE_ADDR:
366 case EMC1812_INT_LOW_BYTE_ADDR:
367 case EMC1812_EXT1_HIGH_BYTE_ADDR:
368 case EMC1812_EXT1_LOW_BYTE_ADDR:
369 case EMC1812_EXT2_HIGH_BYTE_ADDR:
370 case EMC1812_EXT2_LOW_BYTE_ADDR:
371 case EMC1812_EXT3_HIGH_BYTE_ADDR:
372 case EMC1812_EXT3_LOW_BYTE_ADDR:
373 case EMC1812_EXT4_HIGH_BYTE_ADDR:
374 case EMC1812_EXT4_LOW_BYTE_ADDR:
375 case EMC1812_HOTTEST_DIODE_HIGH_BYTE_ADDR:
376 case EMC1812_HOTTEST_DIODE_LOW_BYTE_ADDR:
377 case EMC1812_HOTTEST_STATUS_ADDR:
378 return true;
379 default:
380 return false;
381 }
382}
383
384static const struct regmap_config emc1812_regmap_config = {
385 .reg_bits = 8,
386 .val_bits = 8,
387 .rd_table = &emc1812_regmap_rd_table,
388 .wr_table = &emc1812_regmap_wr_table,
389 .volatile_reg = emc1812_is_volatile_reg,
390 .max_register = EMC1812_REVISION_ADDR,
391 .cache_type = REGCACHE_MAPLE,
392};
393
394static umode_t emc1812_is_visible(const void *_data, enum hwmon_sensor_types type,
395 u32 attr, int channel)
396{
397 const struct emc1812_data *data = _data;
398
399 switch (type) {
400 case hwmon_temp:
401 /* Don't show channels which are not enabled */
402 if (!(data->active_ch_mask & BIT(channel)))
403 return 0;
404
405 switch (attr) {
406 case hwmon_temp_min:
407 case hwmon_temp_max:
408 case hwmon_temp_crit:
409 case hwmon_temp_crit_hyst:
410 return 0644;
411 case hwmon_temp_crit_alarm:
412 case hwmon_temp_input:
413 case hwmon_temp_fault:
414 case hwmon_temp_max_alarm:
415 case hwmon_temp_max_hyst:
416 case hwmon_temp_min_alarm:
417 return 0444;
418 case hwmon_temp_label:
419 if (data->labels[channel])
420 return 0444;
421 return 0;
422 default:
423 return 0;
424 }
425 case hwmon_chip:
426 switch (attr) {
427 case hwmon_chip_update_interval:
428 return 0644;
429 default:
430 return 0;
431 }
432 default:
433 return 0;
434 }
435};
436
437static int emc1812_get_temp(struct emc1812_data *data, int channel, long *val)
438{
439 __be16 tmp_be16;
440 int ret;
441
442 ret = regmap_bulk_read(data->regmap, EMC1812_TEMP_CH_ADDR(channel),
443 &tmp_be16, sizeof(tmp_be16));
444 if (ret)
445 return ret;
446
447 /* Range is always -64 to 191.875°C */
448 *val = ((be16_to_cpu(tmp_be16) >> 5) - (EMC1812_TEMP_OFFSET << 3)) * 125;
449
450 return 0;
451}
452
453static int emc1812_get_crit_limit_temp(struct emc1812_data *data, int channel, long *val)
454{
455 unsigned int tmp;
456 int ret;
457
458 /* Critical register is 8bits long and keeps only integer part of temperature */
459 ret = regmap_read(data->regmap, emc1812_temp_crit_regs[channel], &tmp);
460 if (ret)
461 return ret;
462
463 *val = tmp;
464 /* Range is always -64 to 191°C */
465 *val = (*val - EMC1812_TEMP_OFFSET) * 1000;
466
467 return 0;
468}
469
470static int emc1812_get_limit_temp(struct emc1812_data *data, int ch,
471 enum emc1812_limit_type type, long *val)
472{
473 unsigned int regvalh;
474 unsigned int regvall = 0;
475 int ret;
476
477 ret = regmap_read(data->regmap, emc1812_limit_regs[ch][type], &regvalh);
478 if (ret < 0)
479 return ret;
480
481 if (ch) {
482 ret = regmap_read(data->regmap, emc1812_limit_regs_low[ch][type], &regvall);
483 if (ret < 0)
484 return ret;
485 }
486
487 /* Range is always -64 to 191.875°C */
488 *val = ((regvalh << 3) | (regvall >> 5));
489 *val = (*val - (EMC1812_TEMP_OFFSET << 3)) * 125;
490
491 return 0;
492}
493
494static int emc1812_read_reg(struct device *dev, struct emc1812_data *data, u32 attr,
495 int channel, long *val)
496{
497 unsigned int hyst;
498 int ret;
499
500 switch (attr) {
501 case hwmon_temp_min:
502 case hwmon_temp_max:
503 return emc1812_get_limit_temp(data, channel, emc1812_temp_map[attr], val);
504 case hwmon_temp_crit:
505 return emc1812_get_crit_limit_temp(data, channel, val);
506 case hwmon_temp_input:
507 return emc1812_get_temp(data, channel, val);
508 case hwmon_temp_max_hyst:
509 ret = emc1812_get_limit_temp(data, channel, temp_max, val);
510 if (ret < 0)
511 return ret;
512
513 ret = regmap_read(data->regmap, EMC1812_THRM_HYS_ADDR, &hyst);
514 if (ret < 0)
515 return ret;
516
517 *val -= (long)hyst * 1000;
518
519 return 0;
520 case hwmon_temp_crit_hyst:
521 ret = emc1812_get_crit_limit_temp(data, channel, val);
522 if (ret < 0)
523 return ret;
524
525 ret = regmap_read(data->regmap, EMC1812_THRM_HYS_ADDR, &hyst);
526 if (ret < 0)
527 return ret;
528
529 *val -= (long)hyst * 1000;
530
531 return 0;
532 case hwmon_temp_min_alarm:
533 *val = regmap_test_bits(data->regmap, EMC1812_LOW_LIMIT_STATUS_ADDR,
534 BIT(channel));
535 if (*val < 0)
536 return *val;
537
538 return 0;
539 case hwmon_temp_max_alarm:
540 *val = regmap_test_bits(data->regmap, EMC1812_HIGH_LIMIT_STATUS_ADDR,
541 BIT(channel));
542 if (*val < 0)
543 return *val;
544
545 return 0;
546 case hwmon_temp_crit_alarm:
547 *val = regmap_test_bits(data->regmap, EMC1812_THERM_LIMIT_STATUS_ADDR,
548 BIT(channel));
549 if (*val < 0)
550 return *val;
551
552 return 0;
553 case hwmon_temp_fault:
554 *val = regmap_test_bits(data->regmap, EMC1812_EXT_DIODE_FAULT_STATUS_ADDR,
555 BIT(channel));
556 if (*val < 0)
557 return *val;
558
559 return 0;
560 default:
561 return -EOPNOTSUPP;
562 }
563}
564
565static int emc1812_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
566 int channel, long *val)
567{
568 struct emc1812_data *data = dev_get_drvdata(dev);
569 unsigned int convrate;
570 int ret;
571
572 switch (type) {
573 case hwmon_temp:
574 return emc1812_read_reg(dev, data, attr, channel, val);
575 case hwmon_chip:
576 switch (attr) {
577 case hwmon_chip_update_interval:
578 ret = regmap_read(data->regmap, EMC1812_CONV_ADDR, &convrate);
579 if (ret < 0)
580 return ret;
581
582 if (convrate > 10)
583 convrate = 4;
584
585 *val = DIV_ROUND_CLOSEST(16000, 1 << convrate);
586 return 0;
587 default:
588 return -EOPNOTSUPP;
589 }
590 default:
591 return -EOPNOTSUPP;
592 }
593}
594
595static int emc1812_read_string(struct device *dev, enum hwmon_sensor_types type,
596 u32 attr, int channel, const char **str)
597{
598 struct emc1812_data *data = dev_get_drvdata(dev);
599
600 if (channel >= data->chip->phys_channels)
601 return -EOPNOTSUPP;
602
603 switch (type) {
604 case hwmon_temp:
605 switch (attr) {
606 case hwmon_temp_label:
607 *str = data->labels[channel];
608 return 0;
609 default:
610 return -EOPNOTSUPP;
611 }
612 default:
613 return -EOPNOTSUPP;
614 }
615}
616
617static int emc1812_set_hyst(struct emc1812_data *data, int channel, int val)
618{
619 unsigned int limit;
620 int hyst, ret;
621
622 /* Critical register is 8bits long and keeps only integer part of temperature */
623 ret = regmap_read(data->regmap, emc1812_temp_crit_regs[channel], &limit);
624 if (ret)
625 return ret;
626
627 hyst = clamp_val((int)limit - val, 0, 255);
628
629 ret = regmap_write(data->regmap, EMC1812_THRM_HYS_ADDR, hyst);
630
631 return ret;
632}
633
634static int emc1812_set_temp(struct emc1812_data *data, int channel,
635 enum emc1812_limit_type map, int val)
636{
637 unsigned int valh, vall;
638 u8 regh, regl;
639 int ret;
640
641 regh = emc1812_limit_regs[channel][map];
642 regl = emc1812_limit_regs_low[channel][map];
643
644 if (channel) {
645 val = DIV_ROUND_CLOSEST(val, 125);
646 valh = (val >> 3) & 0xff;
647 vall = (val & 0x07) << 5;
648 } else {
649 /* Temperature limit for internal channel is stored on 8bits */
650 valh = DIV_ROUND_CLOSEST(val, 1000);
651 valh = clamp_val(valh, 0, 255);
652 }
653
654 ret = regmap_write(data->regmap, regh, valh);
655 if (ret < 0)
656 return ret;
657
658 if (channel)
659 ret = regmap_write(data->regmap, regl, vall);
660
661 return ret;
662}
663
664static int emc1812_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
665 int channel, long val)
666{
667 struct emc1812_data *data = dev_get_drvdata(dev);
668 unsigned int interval, tmp;
669
670 switch (type) {
671 case hwmon_temp:
672 /* Range should be -64000 to 191875°C + (EMC1812_TEMP_OFFSET * 1000) */
673 val = clamp_val(val, -64000, 191875);
674 val = val + (EMC1812_TEMP_OFFSET * 1000);
675
676 switch (attr) {
677 case hwmon_temp_min:
678 case hwmon_temp_max:
679 return emc1812_set_temp(data, channel, emc1812_temp_map[attr], val);
680 case hwmon_temp_crit:
681 /* Critical temperature limit is stored on 8bits */
682 val = DIV_ROUND_CLOSEST(val, 1000);
683 tmp = clamp_val(val, 0, 255);
684 return regmap_write(data->regmap, emc1812_temp_crit_regs[channel], tmp);
685 case hwmon_temp_crit_hyst:
686 /* Critical temperature hysteresis is stored on 8bits */
687 val = DIV_ROUND_CLOSEST(val, 1000);
688 tmp = clamp_val(val, 0, 255);
689 return emc1812_set_hyst(data, channel, tmp);
690 default:
691 return -EOPNOTSUPP;
692 }
693 case hwmon_chip:
694 switch (attr) {
695 case hwmon_chip_update_interval:
696 interval = clamp_val(val, 0, 16000);
697 tmp = find_closest_descending(interval, emc1812_conv_time,
698 ARRAY_SIZE(emc1812_conv_time));
699 return regmap_write(data->regmap, EMC1812_CONV_ADDR, tmp);
700 default:
701 return -EOPNOTSUPP;
702 }
703 default:
704 return -EOPNOTSUPP;
705 }
706}
707
708static int emc1812_init(struct emc1812_data *priv)
709{
710 int i, ret;
711 u8 val;
712
713 ret = regmap_write(priv->regmap, EMC1812_THRM_HYS_ADDR, 0x0A);
714 if (ret)
715 return ret;
716
717 ret = regmap_write(priv->regmap, EMC1812_CONSEC_ALERT_ADDR, 0x70);
718 if (ret)
719 return ret;
720
721 ret = regmap_write(priv->regmap, EMC1812_FILTER_SEL_ADDR, 0);
722 if (ret)
723 return ret;
724
725 ret = regmap_write(priv->regmap, EMC1812_HOTTEST_CFG_ADDR, 0);
726 if (ret)
727 return ret;
728
729 /* Enables the beta compensation factor auto-detection function for beta1 and beta2 */
730 ret = regmap_write(priv->regmap, EMC1812_EXT1_BETA_CONFIG_ADDR,
731 EMC1812_BETA_LOCK_VAL);
732 if (ret)
733 return ret;
734
735 if (priv->chip->has_ext2_beta_reg) {
736 ret = regmap_write(priv->regmap, EMC1812_EXT2_BETA_CONFIG_ADDR,
737 EMC1812_BETA_LOCK_VAL);
738 if (ret)
739 return ret;
740 }
741
742 for (i = 0; i < priv->chip->phys_channels; i++) {
743 if (!test_bit(i, &priv->active_ch_mask))
744 continue;
745
746 /* Update the max temperature limit for extended temperature range. */
747 ret = emc1812_set_temp(priv, i, emc1812_temp_map[hwmon_temp_max],
748 EMC1812_HIGH_LIMIT_DEFAULT * 1000);
749 if (ret)
750 return ret;
751
752 /* Update the critical temperature limit for extended temperature range. */
753 ret = regmap_write(priv->regmap, emc1812_temp_crit_regs[i],
754 EMC1812_HIGH_LIMIT_DEFAULT);
755 if (ret)
756 return ret;
757
758 /* Set the ideality factor */
759 if (i > 0) {
760 ret = regmap_write(priv->regmap, emc1812_ideality_regs[i],
761 EMC1812_DEFAULT_IDEALITY_FACTOR);
762 if (ret)
763 return ret;
764 }
765 }
766
767 /*
768 * Set default values in registers. APDD, RECD12 and RECD34 are active on 0.
769 * Set the device to be in Run (Active) state and converting on all
770 * channels.
771 * Don't change conversion rate. After reset, default is 4 conversions/seconds.
772 * The temperature measurement range is -64°C to +191.875°C.
773 * Set ALERT/THERM2 pin to be in comparator mode (When the ALERT/THERM2 pin is
774 * asserted in comparator mode, the corresponding High Limit Status bits are set.
775 * Reading these bits does not clear them until the ALERT/THERM2 pin is deasserted.
776 * Once the ALERT/THERM2 pin is deasserted, the status bits are automatically
777 * cleared.).
778 */
779 val = FIELD_PREP(EMC1812_CFG_MSKAL, 0) |
780 FIELD_PREP(EMC1812_CFG_RS, 0) |
781 FIELD_PREP(EMC1812_CFG_ATTHM, 1) |
782 FIELD_PREP(EMC1812_CFG_RECD12, !priv->recd12_en) |
783 FIELD_PREP(EMC1812_CFG_RECD34, !priv->recd34_en) |
784 FIELD_PREP(EMC1812_CFG_RANGE, 1) |
785 FIELD_PREP(EMC1812_CFG_DA_ENA, 0) |
786 FIELD_PREP(EMC1812_CFG_APDD, !priv->apdd_en);
787
788 return regmap_write(priv->regmap, EMC1812_CFG_ADDR, val);
789}
790
791static int emc1812_parse_fw_config(struct emc1812_data *data, struct device *dev)
792{
793 unsigned int reg_nr = 0;
794 int ret;
795
796 /* To be able to load the driver in case we don't have device tree */
797 if (!dev_fwnode(dev)) {
798 data->active_ch_mask = BIT(data->chip->phys_channels) - 1;
799 return 0;
800 }
801
802 data->apdd_en = device_property_read_bool(dev, "microchip,enable-anti-parallel");
803 data->recd12_en = device_property_read_bool(dev, "microchip,parasitic-res-on-channel1-2");
804 data->recd34_en = device_property_read_bool(dev, "microchip,parasitic-res-on-channel3-4");
805
806 /* Internal temperature channel is always active */
807 data->labels[reg_nr] = "internal_diode";
808 set_bit(reg_nr, &data->active_ch_mask);
809
810 device_for_each_child_node_scoped(dev, child) {
811 ret = fwnode_property_read_u32(child, "reg", &reg_nr);
812 if (ret || reg_nr >= data->chip->phys_channels)
813 return dev_err_probe(dev, -EINVAL,
814 "The index is higher then the chip supports\n");
815 /* Mark channel as active */
816 set_bit(reg_nr, &data->active_ch_mask);
817
818 fwnode_property_read_string(child, "label", &data->labels[reg_nr]);
819 }
820
821 return 0;
822}
823
824static int emc1812_chip_identify(struct emc1812_data *data, struct i2c_client *client)
825{
826 const struct emc1812_features *chip;
827 struct device *dev = &client->dev;
828 unsigned int tmp;
829 int ret;
830
831 ret = regmap_read(data->regmap, EMC1812_PRODUCT_ID_ADDR, &tmp);
832 if (ret)
833 return ret;
834
835 switch (tmp) {
836 case EMC1812_PID:
837 data->chip = &emc1812_chip_config;
838 break;
839 case EMC1813_PID:
840 data->chip = &emc1813_chip_config;
841 break;
842 case EMC1814_PID:
843 data->chip = &emc1814_chip_config;
844 break;
845 case EMC1815_PID:
846 data->chip = &emc1815_chip_config;
847 break;
848 case EMC1833_PID:
849 data->chip = &emc1833_chip_config;
850 break;
851 default:
852 /*
853 * If failed to identify the hardware based on internal registers,
854 * try using fallback compatible in device tree to deal with some
855 * newer part number.
856 */
857 chip = i2c_get_match_data(client);
858 if (!chip)
859 return -ENODEV;
860
861 dev_warn(dev, "Unrecognized hardware ID 0x%x, using %s from devicetree data\n",
862 tmp, chip->name);
863
864 data->chip = chip;
865
866 return 0;
867 }
868
869 return 0;
870}
871
872static const struct hwmon_ops emc1812_ops = {
873 .is_visible = emc1812_is_visible,
874 .read = emc1812_read,
875 .read_string = emc1812_read_string,
876 .write = emc1812_write,
877};
878
879static const struct hwmon_chip_info emc1812_chip_info = {
880 .ops = &emc1812_ops,
881 .info = emc1812_info,
882};
883
884static int emc1812_probe(struct i2c_client *client)
885{
886 struct device *dev = &client->dev;
887 struct emc1812_data *data;
888 struct device *hwmon_dev;
889 int ret;
890
891 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
892 if (!data)
893 return -ENOMEM;
894
895 data->regmap = devm_regmap_init_i2c(client, &emc1812_regmap_config);
896 if (IS_ERR(data->regmap))
897 return dev_err_probe(dev, PTR_ERR(data->regmap),
898 "Cannot initialize register map\n");
899
900 ret = emc1812_chip_identify(data, client);
901 if (ret)
902 return dev_err_probe(dev, ret, "Chip identification fails\n");
903
904 ret = emc1812_parse_fw_config(data, dev);
905 if (ret)
906 return ret;
907
908 ret = emc1812_init(data);
909 if (ret)
910 return dev_err_probe(dev, ret, "Cannot initialize device\n");
911
912 hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data,
913 &emc1812_chip_info, NULL);
914
915 return PTR_ERR_OR_ZERO(hwmon_dev);
916}
917
918static const struct i2c_device_id emc1812_id[] = {
919 { .name = "emc1812", .driver_data = (kernel_ulong_t)&emc1812_chip_config },
920 { .name = "emc1813", .driver_data = (kernel_ulong_t)&emc1813_chip_config },
921 { .name = "emc1814", .driver_data = (kernel_ulong_t)&emc1814_chip_config },
922 { .name = "emc1815", .driver_data = (kernel_ulong_t)&emc1815_chip_config },
923 { .name = "emc1833", .driver_data = (kernel_ulong_t)&emc1833_chip_config },
924 { }
925};
926MODULE_DEVICE_TABLE(i2c, emc1812_id);
927
928static const struct of_device_id emc1812_of_match[] = {
929 {
930 .compatible = "microchip,emc1812",
931 .data = &emc1812_chip_config
932 },
933 {
934 .compatible = "microchip,emc1813",
935 .data = &emc1813_chip_config
936 },
937 {
938 .compatible = "microchip,emc1814",
939 .data = &emc1814_chip_config
940 },
941 {
942 .compatible = "microchip,emc1815",
943 .data = &emc1815_chip_config
944 },
945 {
946 .compatible = "microchip,emc1833",
947 .data = &emc1833_chip_config
948 },
949 { }
950};
951MODULE_DEVICE_TABLE(of, emc1812_of_match);
952
953static struct i2c_driver emc1812_driver = {
954 .driver = {
955 .name = "emc1812",
956 .of_match_table = emc1812_of_match,
957 },
958 .probe = emc1812_probe,
959 .id_table = emc1812_id,
960};
961module_i2c_driver(emc1812_driver);
962
963MODULE_AUTHOR("Marius Cristea <[email protected]>");
964MODULE_DESCRIPTION("EMC1812/13/14/15/33 high-accuracy remote diode temperature monitor Driver");
965MODULE_LICENSE("GPL");