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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * fam15h_power.c - AMD Family 15h processor power monitoring
4 *
5 * Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
6 * Author: Andreas Herrmann <[email protected]>
7 */
8
9#include <linux/err.h>
10#include <linux/hwmon.h>
11#include <linux/hwmon-sysfs.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/pci.h>
15#include <linux/bitops.h>
16#include <linux/cpu.h>
17#include <linux/cpumask.h>
18#include <linux/time.h>
19#include <linux/sched.h>
20#include <linux/topology.h>
21#include <asm/processor.h>
22#include <asm/cpuid/api.h>
23#include <asm/msr.h>
24
25MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
26MODULE_AUTHOR("Andreas Herrmann <[email protected]>");
27MODULE_LICENSE("GPL");
28
29/* D18F3 */
30#define REG_NORTHBRIDGE_CAP 0xe8
31
32/* D18F4 */
33#define REG_PROCESSOR_TDP 0x1b8
34
35/* D18F5 */
36#define REG_TDP_RUNNING_AVERAGE 0xe0
37#define REG_TDP_LIMIT3 0xe8
38
39#define FAM15H_MIN_NUM_ATTRS 2
40#define FAM15H_NUM_GROUPS 2
41#define MAX_CUS 8
42
43/* set maximum interval as 1 second */
44#define MAX_INTERVAL 1000
45
46#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
47
48struct fam15h_power_data {
49 struct pci_dev *pdev;
50 unsigned int tdp_to_watts;
51 unsigned int base_tdp;
52 unsigned int processor_pwr_watts;
53 unsigned int cpu_pwr_sample_ratio;
54 const struct attribute_group *groups[FAM15H_NUM_GROUPS];
55 struct attribute_group group;
56 /* maximum accumulated power of a compute unit */
57 u64 max_cu_acc_power;
58 /* accumulated power of the compute units */
59 u64 cu_acc_power[MAX_CUS];
60 /* performance timestamp counter */
61 u64 cpu_sw_pwr_ptsc[MAX_CUS];
62 /* online/offline status of current compute unit */
63 int cu_on[MAX_CUS];
64 unsigned long power_period;
65};
66
67static bool is_carrizo_or_later(void)
68{
69 return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
70}
71
72static ssize_t power1_input_show(struct device *dev,
73 struct device_attribute *attr, char *buf)
74{
75 u32 val, tdp_limit, running_avg_range;
76 s32 running_avg_capture;
77 u64 curr_pwr_watts;
78 struct fam15h_power_data *data = dev_get_drvdata(dev);
79 struct pci_dev *f4 = data->pdev;
80
81 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
82 REG_TDP_RUNNING_AVERAGE, &val);
83
84 /*
85 * On Carrizo and later platforms, TdpRunAvgAccCap bit field
86 * is extended to 4:31 from 4:25.
87 */
88 if (is_carrizo_or_later()) {
89 running_avg_capture = val >> 4;
90 running_avg_capture = sign_extend32(running_avg_capture, 27);
91 } else {
92 running_avg_capture = (val >> 4) & 0x3fffff;
93 running_avg_capture = sign_extend32(running_avg_capture, 21);
94 }
95
96 running_avg_range = (val & 0xf) + 1;
97
98 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
99 REG_TDP_LIMIT3, &val);
100
101 /*
102 * On Carrizo and later platforms, ApmTdpLimit bit field
103 * is extended to 16:31 from 16:28.
104 */
105 if (is_carrizo_or_later())
106 tdp_limit = val >> 16;
107 else
108 tdp_limit = (val >> 16) & 0x1fff;
109
110 curr_pwr_watts = ((u64)(tdp_limit +
111 data->base_tdp)) << running_avg_range;
112 curr_pwr_watts -= running_avg_capture;
113 curr_pwr_watts *= data->tdp_to_watts;
114
115 /*
116 * Convert to microWatt
117 *
118 * power is in Watt provided as fixed point integer with
119 * scaling factor 1/(2^16). For conversion we use
120 * (10^6)/(2^16) = 15625/(2^10)
121 */
122 curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
123 return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
124}
125static DEVICE_ATTR_RO(power1_input);
126
127static ssize_t power1_crit_show(struct device *dev,
128 struct device_attribute *attr, char *buf)
129{
130 struct fam15h_power_data *data = dev_get_drvdata(dev);
131
132 return sprintf(buf, "%u\n", data->processor_pwr_watts);
133}
134static DEVICE_ATTR_RO(power1_crit);
135
136static void do_read_registers_on_cu(void *_data)
137{
138 struct fam15h_power_data *data = _data;
139 int cu;
140
141 /*
142 * With the new x86 topology modelling, cpu core id actually
143 * is compute unit id.
144 */
145 cu = topology_core_id(smp_processor_id());
146
147 rdmsrq_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
148 rdmsrq_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);
149
150 data->cu_on[cu] = 1;
151}
152
153/*
154 * This function is only able to be called when CPUID
155 * Fn8000_0007:EDX[12] is set.
156 */
157static int read_registers(struct fam15h_power_data *data)
158{
159 int core, this_core;
160 cpumask_var_t mask;
161 int ret, cpu;
162
163 ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
164 if (!ret)
165 return -ENOMEM;
166
167 memset(data->cu_on, 0, sizeof(int) * MAX_CUS);
168
169 cpus_read_lock();
170
171 /*
172 * Choose the first online core of each compute unit, and then
173 * read their MSR value of power and ptsc in a single IPI,
174 * because the MSR value of CPU core represent the compute
175 * unit's.
176 */
177 core = -1;
178
179 for_each_online_cpu(cpu) {
180 this_core = topology_core_id(cpu);
181
182 if (this_core == core)
183 continue;
184
185 core = this_core;
186
187 /* get any CPU on this compute unit */
188 cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
189 }
190
191 on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);
192
193 cpus_read_unlock();
194 free_cpumask_var(mask);
195
196 return 0;
197}
198
199static ssize_t power1_average_show(struct device *dev,
200 struct device_attribute *attr, char *buf)
201{
202 struct fam15h_power_data *data = dev_get_drvdata(dev);
203 u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
204 jdelta[MAX_CUS];
205 u64 tdelta, avg_acc;
206 int cu, cu_num, ret;
207 signed long leftover;
208
209 /*
210 * With the new x86 topology modelling, x86_max_cores is the
211 * compute unit number.
212 */
213 cu_num = topology_num_cores_per_package();
214
215 ret = read_registers(data);
216 if (ret)
217 return 0;
218
219 for (cu = 0; cu < cu_num; cu++) {
220 prev_cu_acc_power[cu] = data->cu_acc_power[cu];
221 prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
222 }
223
224 leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
225 if (leftover)
226 return 0;
227
228 ret = read_registers(data);
229 if (ret)
230 return 0;
231
232 for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
233 /* check if current compute unit is online */
234 if (data->cu_on[cu] == 0)
235 continue;
236
237 if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
238 jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
239 jdelta[cu] -= prev_cu_acc_power[cu];
240 } else {
241 jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
242 }
243 tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
244 jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000;
245 do_div(jdelta[cu], tdelta);
246
247 /* the unit is microWatt */
248 avg_acc += jdelta[cu];
249 }
250
251 return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
252}
253static DEVICE_ATTR_RO(power1_average);
254
255static ssize_t power1_average_interval_show(struct device *dev,
256 struct device_attribute *attr,
257 char *buf)
258{
259 struct fam15h_power_data *data = dev_get_drvdata(dev);
260
261 return sprintf(buf, "%lu\n", data->power_period);
262}
263
264static ssize_t power1_average_interval_store(struct device *dev,
265 struct device_attribute *attr,
266 const char *buf, size_t count)
267{
268 struct fam15h_power_data *data = dev_get_drvdata(dev);
269 unsigned long temp;
270 int ret;
271
272 ret = kstrtoul(buf, 10, &temp);
273 if (ret)
274 return ret;
275
276 if (temp > MAX_INTERVAL)
277 return -EINVAL;
278
279 /* the interval value should be greater than 0 */
280 if (temp <= 0)
281 return -EINVAL;
282
283 data->power_period = temp;
284
285 return count;
286}
287static DEVICE_ATTR_RW(power1_average_interval);
288
289static int fam15h_power_init_attrs(struct pci_dev *pdev,
290 struct fam15h_power_data *data)
291{
292 int n = FAM15H_MIN_NUM_ATTRS;
293 struct attribute **fam15h_power_attrs;
294 struct cpuinfo_x86 *c = &boot_cpu_data;
295
296 if (c->x86 == 0x15 &&
297 (c->x86_model <= 0xf ||
298 (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
299 n += 1;
300
301 /* check if processor supports accumulated power */
302 if (boot_cpu_has(X86_FEATURE_ACC_POWER))
303 n += 2;
304
305 fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
306 sizeof(*fam15h_power_attrs),
307 GFP_KERNEL);
308
309 if (!fam15h_power_attrs)
310 return -ENOMEM;
311
312 n = 0;
313 fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
314 if (c->x86 == 0x15 &&
315 (c->x86_model <= 0xf ||
316 (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
317 fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
318
319 if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
320 fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
321 fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
322 }
323
324 data->group.attrs = fam15h_power_attrs;
325
326 return 0;
327}
328
329static bool should_load_on_this_node(struct pci_dev *f4)
330{
331 u32 val;
332
333 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
334 REG_NORTHBRIDGE_CAP, &val);
335 if ((val & BIT(29)) && ((val >> 30) & 3))
336 return false;
337
338 return true;
339}
340
341/*
342 * Newer BKDG versions have an updated recommendation on how to properly
343 * initialize the running average range (was: 0xE, now: 0x9). This avoids
344 * counter saturations resulting in bogus power readings.
345 * We correct this value ourselves to cope with older BIOSes.
346 */
347static const struct pci_device_id affected_device[] = {
348 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
349 { 0 }
350};
351
352static void tweak_runavg_range(struct pci_dev *pdev)
353{
354 u32 val;
355
356 /*
357 * let this quirk apply only to the current version of the
358 * northbridge, since future versions may change the behavior
359 */
360 if (!pci_match_id(affected_device, pdev))
361 return;
362
363 pci_bus_read_config_dword(pdev->bus,
364 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
365 REG_TDP_RUNNING_AVERAGE, &val);
366 if ((val & 0xf) != 0xe)
367 return;
368
369 val &= ~0xf;
370 val |= 0x9;
371 pci_bus_write_config_dword(pdev->bus,
372 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
373 REG_TDP_RUNNING_AVERAGE, val);
374}
375
376static int fam15h_power_resume(struct device *dev)
377{
378 struct pci_dev *pdev = to_pci_dev(dev);
379 tweak_runavg_range(pdev);
380 return 0;
381}
382
383static DEFINE_SIMPLE_DEV_PM_OPS(fam15h_power_ops, NULL, fam15h_power_resume);
384
385static int fam15h_power_init_data(struct pci_dev *f4,
386 struct fam15h_power_data *data)
387{
388 u32 val;
389 u64 tmp;
390 int ret;
391
392 pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
393 data->base_tdp = val >> 16;
394 tmp = val & 0xffff;
395
396 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
397 REG_TDP_LIMIT3, &val);
398
399 data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
400 tmp *= data->tdp_to_watts;
401
402 /* result not allowed to be >= 256W */
403 if ((tmp >> 16) >= 256)
404 dev_warn(&f4->dev,
405 "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
406 (unsigned int) (tmp >> 16));
407
408 /* convert to microWatt */
409 data->processor_pwr_watts = (tmp * 15625) >> 10;
410
411 ret = fam15h_power_init_attrs(f4, data);
412 if (ret)
413 return ret;
414
415
416 /* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
417 if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
418 return 0;
419
420 /*
421 * determine the ratio of the compute unit power accumulator
422 * sample period to the PTSC counter period by executing CPUID
423 * Fn8000_0007:ECX
424 */
425 data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
426
427 if (rdmsrq_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
428 pr_err("Failed to read max compute unit power accumulator MSR\n");
429 return -ENODEV;
430 }
431
432 data->max_cu_acc_power = tmp;
433
434 /*
435 * Milliseconds are a reasonable interval for the measurement.
436 * But it shouldn't set too long here, because several seconds
437 * would cause the read function to hang. So set default
438 * interval as 10 ms.
439 */
440 data->power_period = 10;
441
442 return read_registers(data);
443}
444
445static int fam15h_power_probe(struct pci_dev *pdev,
446 const struct pci_device_id *id)
447{
448 struct fam15h_power_data *data;
449 struct device *dev = &pdev->dev;
450 struct device *hwmon_dev;
451 int ret;
452
453 /*
454 * though we ignore every other northbridge, we still have to
455 * do the tweaking on _each_ node in MCM processors as the counters
456 * are working hand-in-hand
457 */
458 tweak_runavg_range(pdev);
459
460 if (!should_load_on_this_node(pdev))
461 return -ENODEV;
462
463 data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
464 if (!data)
465 return -ENOMEM;
466
467 ret = fam15h_power_init_data(pdev, data);
468 if (ret)
469 return ret;
470
471 data->pdev = pdev;
472
473 data->groups[0] = &data->group;
474
475 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
476 data,
477 &data->groups[0]);
478 return PTR_ERR_OR_ZERO(hwmon_dev);
479}
480
481static const struct pci_device_id fam15h_power_id_table[] = {
482 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
483 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
484 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
485 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
486 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
487 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
488 {}
489};
490MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
491
492static struct pci_driver fam15h_power_driver = {
493 .name = "fam15h_power",
494 .id_table = fam15h_power_id_table,
495 .probe = fam15h_power_probe,
496 .driver.pm = &fam15h_power_ops,
497};
498
499module_pci_driver(fam15h_power_driver);