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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <dt-bindings/interconnect/qcom,maili-rpmh.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16
17static struct qcom_icc_node ddr_eff_veto_slave = {
18 .name = "ddr_eff_veto_slave",
19 .channels = 1,
20 .buswidth = 4,
21};
22
23static struct qcom_icc_node qup0_core_slave = {
24 .name = "qup0_core_slave",
25 .channels = 1,
26 .buswidth = 4,
27};
28
29static struct qcom_icc_node qup1_core_slave = {
30 .name = "qup1_core_slave",
31 .channels = 1,
32 .buswidth = 4,
33};
34
35static struct qcom_icc_node qup2_core_slave = {
36 .name = "qup2_core_slave",
37 .channels = 1,
38 .buswidth = 4,
39};
40
41static struct qcom_icc_node qup3_core_slave = {
42 .name = "qup3_core_slave",
43 .channels = 1,
44 .buswidth = 4,
45};
46
47static struct qcom_icc_node qup4_core_slave = {
48 .name = "qup4_core_slave",
49 .channels = 1,
50 .buswidth = 4,
51};
52
53static struct qcom_icc_node qup5_core_slave = {
54 .name = "qup5_core_slave",
55 .channels = 1,
56 .buswidth = 4,
57};
58
59static struct qcom_icc_node qhs_aoss = {
60 .name = "qhs_aoss",
61 .channels = 1,
62 .buswidth = 4,
63};
64
65static struct qcom_icc_node qhs_ipa = {
66 .name = "qhs_ipa",
67 .channels = 1,
68 .buswidth = 4,
69};
70
71static struct qcom_icc_node qhs_ipc_router_fence = {
72 .name = "qhs_ipc_router_fence",
73 .channels = 1,
74 .buswidth = 4,
75};
76
77static struct qcom_icc_node qhs_soccp = {
78 .name = "qhs_soccp",
79 .channels = 1,
80 .buswidth = 4,
81};
82
83static struct qcom_icc_node qhs_tme_cfg = {
84 .name = "qhs_tme_cfg",
85 .channels = 1,
86 .buswidth = 4,
87};
88
89static struct qcom_icc_node qss_ddrss_cfg = {
90 .name = "qss_ddrss_cfg",
91 .channels = 1,
92 .buswidth = 4,
93};
94
95static struct qcom_icc_node qxs_imem = {
96 .name = "qxs_imem",
97 .channels = 1,
98 .buswidth = 8,
99};
100
101static struct qcom_icc_node xs_pcie = {
102 .name = "xs_pcie",
103 .channels = 1,
104 .buswidth = 8,
105};
106
107static struct qcom_icc_node xs_pcie_g4x1 = {
108 .name = "xs_pcie_g4x1",
109 .channels = 1,
110 .buswidth = 8,
111};
112
113static struct qcom_icc_node qhs_lpi_cc = {
114 .name = "qhs_lpi_cc",
115 .channels = 1,
116 .buswidth = 4,
117};
118
119static struct qcom_icc_node qns_lb = {
120 .name = "qns_lb",
121 .channels = 4,
122 .buswidth = 16,
123};
124
125static struct qcom_icc_node srvc_llclpi_noc = {
126 .name = "srvc_llclpi_noc",
127 .channels = 1,
128 .buswidth = 4,
129};
130
131static struct qcom_icc_node srvc_llclpi_noc_chipcx = {
132 .name = "srvc_llclpi_noc_chipcx",
133 .channels = 1,
134 .buswidth = 4,
135};
136
137static struct qcom_icc_node ebi = {
138 .name = "ebi",
139 .channels = 4,
140 .buswidth = 4,
141};
142
143static struct qcom_icc_node ddr_rt_slave = {
144 .name = "ddr_rt_slave",
145 .channels = 4,
146 .buswidth = 4,
147};
148
149static struct qcom_icc_node srvc_pcie_aggre_noc = {
150 .name = "srvc_pcie_aggre_noc",
151 .channels = 1,
152 .buswidth = 4,
153};
154
155static struct qcom_icc_node qhs_ahb2phy0 = {
156 .name = "qhs_ahb2phy0",
157 .channels = 1,
158 .buswidth = 4,
159};
160
161static struct qcom_icc_node qhs_boot_rom = {
162 .name = "qhs_boot_rom",
163 .channels = 1,
164 .buswidth = 4,
165};
166
167static struct qcom_icc_node qhs_camera_cfg = {
168 .name = "qhs_camera_cfg",
169 .channels = 1,
170 .buswidth = 4,
171};
172
173static struct qcom_icc_node qhs_clk_ctl = {
174 .name = "qhs_clk_ctl",
175 .channels = 1,
176 .buswidth = 4,
177};
178
179static struct qcom_icc_node qhs_crypto_cfg = {
180 .name = "qhs_crypto_cfg",
181 .channels = 1,
182 .buswidth = 4,
183};
184
185static struct qcom_icc_node qhs_display_cfg = {
186 .name = "qhs_display_cfg",
187 .channels = 1,
188 .buswidth = 4,
189};
190
191static struct qcom_icc_node qhs_eva_cfg = {
192 .name = "qhs_eva_cfg",
193 .channels = 1,
194 .buswidth = 4,
195};
196
197static struct qcom_icc_node qhs_gpuss_cfg = {
198 .name = "qhs_gpuss_cfg",
199 .channels = 1,
200 .buswidth = 8,
201};
202
203static struct qcom_icc_node qhs_i2c = {
204 .name = "qhs_i2c",
205 .channels = 1,
206 .buswidth = 4,
207};
208
209static struct qcom_icc_node qhs_imem_cfg = {
210 .name = "qhs_imem_cfg",
211 .channels = 1,
212 .buswidth = 4,
213};
214
215static struct qcom_icc_node qhs_ipc_router = {
216 .name = "qhs_ipc_router",
217 .channels = 4,
218 .buswidth = 4,
219};
220
221static struct qcom_icc_node qhs_iris_cfg = {
222 .name = "qhs_iris_cfg",
223 .channels = 1,
224 .buswidth = 4,
225};
226
227static struct qcom_icc_node qhs_mss_cfg = {
228 .name = "qhs_mss_cfg",
229 .channels = 1,
230 .buswidth = 4,
231};
232
233static struct qcom_icc_node qhs_pcie_cfg = {
234 .name = "qhs_pcie_cfg",
235 .channels = 1,
236 .buswidth = 4,
237};
238
239static struct qcom_icc_node qhs_pcie_g4x1_cfg = {
240 .name = "qhs_pcie_g4x1_cfg",
241 .channels = 1,
242 .buswidth = 4,
243};
244
245static struct qcom_icc_node qhs_prng = {
246 .name = "qhs_prng",
247 .channels = 1,
248 .buswidth = 4,
249};
250
251static struct qcom_icc_node qhs_qspi = {
252 .name = "qhs_qspi",
253 .channels = 1,
254 .buswidth = 4,
255};
256
257static struct qcom_icc_node qhs_qup1 = {
258 .name = "qhs_qup1",
259 .channels = 1,
260 .buswidth = 4,
261};
262
263static struct qcom_icc_node qhs_qup2 = {
264 .name = "qhs_qup2",
265 .channels = 1,
266 .buswidth = 4,
267};
268
269static struct qcom_icc_node qhs_qup3 = {
270 .name = "qhs_qup3",
271 .channels = 1,
272 .buswidth = 4,
273};
274
275static struct qcom_icc_node qhs_qup4 = {
276 .name = "qhs_qup4",
277 .channels = 1,
278 .buswidth = 4,
279};
280
281static struct qcom_icc_node qhs_qup5 = {
282 .name = "qhs_qup5",
283 .channels = 1,
284 .buswidth = 4,
285};
286
287static struct qcom_icc_node qhs_sdc2 = {
288 .name = "qhs_sdc2",
289 .channels = 1,
290 .buswidth = 4,
291};
292
293static struct qcom_icc_node qhs_sdc4 = {
294 .name = "qhs_sdc4",
295 .channels = 1,
296 .buswidth = 4,
297};
298
299static struct qcom_icc_node qhs_tlmm = {
300 .name = "qhs_tlmm",
301 .channels = 1,
302 .buswidth = 4,
303};
304
305static struct qcom_icc_node qhs_ufs_mem_cfg = {
306 .name = "qhs_ufs_mem_cfg",
307 .channels = 1,
308 .buswidth = 4,
309};
310
311static struct qcom_icc_node qhs_usb3 = {
312 .name = "qhs_usb3",
313 .channels = 1,
314 .buswidth = 4,
315};
316
317static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
318 .name = "qhs_vsense_ctrl_cfg",
319 .channels = 1,
320 .buswidth = 4,
321};
322
323static struct qcom_icc_node qss_qdss_cfg = {
324 .name = "qss_qdss_cfg",
325 .channels = 1,
326 .buswidth = 4,
327};
328
329static struct qcom_icc_node qss_qdss_stm = {
330 .name = "qss_qdss_stm",
331 .channels = 1,
332 .buswidth = 4,
333};
334
335static struct qcom_icc_node qss_tcsr = {
336 .name = "qss_tcsr",
337 .channels = 1,
338 .buswidth = 4,
339};
340
341static struct qcom_icc_node xs_sys_tcu_cfg = {
342 .name = "xs_sys_tcu_cfg",
343 .channels = 1,
344 .buswidth = 8,
345};
346
347static struct qcom_icc_node ddr_eff_veto_master = {
348 .name = "ddr_eff_veto_master",
349 .channels = 1,
350 .buswidth = 4,
351 .num_links = 1,
352 .link_nodes = { &ddr_eff_veto_slave },
353};
354
355static struct qcom_icc_node qup0_core_master = {
356 .name = "qup0_core_master",
357 .channels = 1,
358 .buswidth = 4,
359 .num_links = 1,
360 .link_nodes = { &qup0_core_slave },
361};
362
363static struct qcom_icc_node qup1_core_master = {
364 .name = "qup1_core_master",
365 .channels = 1,
366 .buswidth = 4,
367 .num_links = 1,
368 .link_nodes = { &qup1_core_slave },
369};
370
371static struct qcom_icc_node qup2_core_master = {
372 .name = "qup2_core_master",
373 .channels = 1,
374 .buswidth = 4,
375 .num_links = 1,
376 .link_nodes = { &qup2_core_slave },
377};
378
379static struct qcom_icc_node qup3_core_master = {
380 .name = "qup3_core_master",
381 .channels = 1,
382 .buswidth = 4,
383 .num_links = 1,
384 .link_nodes = { &qup3_core_slave },
385};
386
387static struct qcom_icc_node qup4_core_master = {
388 .name = "qup4_core_master",
389 .channels = 1,
390 .buswidth = 4,
391 .num_links = 1,
392 .link_nodes = { &qup4_core_slave },
393};
394
395static struct qcom_icc_node qup5_core_master = {
396 .name = "qup5_core_master",
397 .channels = 1,
398 .buswidth = 4,
399 .num_links = 1,
400 .link_nodes = { &qup5_core_slave },
401};
402
403static struct qcom_icc_node qnm_gemnoc_pcie = {
404 .name = "qnm_gemnoc_pcie",
405 .channels = 1,
406 .buswidth = 8,
407 .num_links = 2,
408 .link_nodes = { &xs_pcie, &xs_pcie_g4x1 },
409};
410
411static struct qcom_icc_node qnm_lpiaon_noc_llclpi_noc = {
412 .name = "qnm_lpiaon_noc_llclpi_noc",
413 .channels = 1,
414 .buswidth = 16,
415 .num_links = 4,
416 .link_nodes = { &qhs_lpi_cc, &qns_lb,
417 &srvc_llclpi_noc, &srvc_llclpi_noc_chipcx },
418};
419
420static struct qcom_icc_node llcc_mc = {
421 .name = "llcc_mc",
422 .channels = 4,
423 .buswidth = 4,
424 .num_links = 1,
425 .link_nodes = { &ebi },
426};
427
428static struct qcom_icc_node ddr_rt_mc = {
429 .name = "ddr_rt_mc",
430 .channels = 4,
431 .buswidth = 4,
432 .num_links = 1,
433 .link_nodes = { &ddr_rt_slave },
434};
435
436static struct qcom_icc_node qsm_pcie_anoc_cfg = {
437 .name = "qsm_pcie_anoc_cfg",
438 .channels = 1,
439 .buswidth = 4,
440 .num_links = 1,
441 .link_nodes = { &srvc_pcie_aggre_noc },
442};
443
444static struct qcom_icc_node qsm_cfg_center = {
445 .name = "qsm_cfg_center",
446 .channels = 1,
447 .buswidth = 4,
448 .num_links = 14,
449 .link_nodes = { &qhs_boot_rom, &qhs_clk_ctl,
450 &qhs_crypto_cfg, &qhs_gpuss_cfg,
451 &qhs_imem_cfg, &qhs_ipc_router,
452 &qhs_mss_cfg, &qhs_prng,
453 &qhs_tlmm, &qhs_vsense_ctrl_cfg,
454 &qss_qdss_cfg, &qss_qdss_stm,
455 &qss_tcsr, &xs_sys_tcu_cfg },
456};
457
458static struct qcom_icc_node qsm_cfg_east = {
459 .name = "qsm_cfg_east",
460 .channels = 1,
461 .buswidth = 4,
462 .num_links = 2,
463 .link_nodes = { &qhs_qup2, &qhs_qup4 },
464};
465
466static struct qcom_icc_node qsm_cfg_mm_hf = {
467 .name = "qsm_cfg_mm_hf",
468 .channels = 1,
469 .buswidth = 4,
470 .num_links = 1,
471 .link_nodes = { &qhs_display_cfg },
472};
473
474static struct qcom_icc_node qsm_cfg_mm_sf = {
475 .name = "qsm_cfg_mm_sf",
476 .channels = 1,
477 .buswidth = 4,
478 .num_links = 3,
479 .link_nodes = { &qhs_camera_cfg, &qhs_eva_cfg,
480 &qhs_iris_cfg },
481};
482
483static struct qcom_icc_node qsm_cfg_north = {
484 .name = "qsm_cfg_north",
485 .channels = 1,
486 .buswidth = 4,
487 .num_links = 3,
488 .link_nodes = { &qhs_ahb2phy0, &qhs_ufs_mem_cfg,
489 &qhs_usb3 },
490};
491
492static struct qcom_icc_node qsm_cfg_west = {
493 .name = "qsm_cfg_west",
494 .channels = 1,
495 .buswidth = 4,
496 .num_links = 2,
497 .link_nodes = { &qhs_qup1, &qhs_sdc2 },
498};
499
500static struct qcom_icc_node qns_llcc = {
501 .name = "qns_llcc",
502 .channels = 4,
503 .buswidth = 16,
504 .num_links = 1,
505 .link_nodes = { &llcc_mc },
506};
507
508static struct qcom_icc_node qns_pcie = {
509 .name = "qns_pcie",
510 .channels = 1,
511 .buswidth = 8,
512 .num_links = 1,
513 .link_nodes = { &qnm_gemnoc_pcie },
514};
515
516static struct qcom_icc_node qns_llc_lpinoc = {
517 .name = "qns_llc_lpinoc",
518 .channels = 1,
519 .buswidth = 16,
520 .num_links = 1,
521 .link_nodes = { &qnm_lpiaon_noc_llclpi_noc },
522};
523
524static struct qcom_icc_node qss_pcie_anoc_cfg = {
525 .name = "qss_pcie_anoc_cfg",
526 .channels = 1,
527 .buswidth = 4,
528 .num_links = 1,
529 .link_nodes = { &qsm_pcie_anoc_cfg },
530};
531
532static struct qcom_icc_node qss_stdst_center_cfg = {
533 .name = "qss_stdst_center_cfg",
534 .channels = 1,
535 .buswidth = 4,
536 .num_links = 1,
537 .link_nodes = { &qsm_cfg_center },
538};
539
540static struct qcom_icc_node qss_stdst_east_cfg = {
541 .name = "qss_stdst_east_cfg",
542 .channels = 1,
543 .buswidth = 4,
544 .num_links = 1,
545 .link_nodes = { &qsm_cfg_east },
546};
547
548static struct qcom_icc_node qss_stdst_mm_hf_cfg = {
549 .name = "qss_stdst_mm_hf_cfg",
550 .channels = 1,
551 .buswidth = 4,
552 .num_links = 1,
553 .link_nodes = { &qsm_cfg_mm_hf },
554};
555
556static struct qcom_icc_node qss_stdst_mm_sf_cfg = {
557 .name = "qss_stdst_mm_sf_cfg",
558 .channels = 1,
559 .buswidth = 4,
560 .num_links = 1,
561 .link_nodes = { &qsm_cfg_mm_sf },
562};
563
564static struct qcom_icc_node qss_stdst_north_cfg = {
565 .name = "qss_stdst_north_cfg",
566 .channels = 1,
567 .buswidth = 4,
568 .num_links = 1,
569 .link_nodes = { &qsm_cfg_north },
570};
571
572static struct qcom_icc_node qss_stdst_west_cfg = {
573 .name = "qss_stdst_west_cfg",
574 .channels = 1,
575 .buswidth = 4,
576 .num_links = 1,
577 .link_nodes = { &qsm_cfg_west },
578};
579
580static struct qcom_icc_node alm_gic = {
581 .name = "alm_gic",
582 .channels = 1,
583 .buswidth = 8,
584 .qosbox = &(const struct qcom_icc_qosbox) {
585 .num_ports = 1,
586 .port_offsets = { 0x14d000 },
587 .prio = 4,
588 .urg_fwd = 0,
589 .prio_fwd_disable = 1,
590 },
591 .num_links = 1,
592 .link_nodes = { &qns_llcc },
593};
594
595static struct qcom_icc_node qnm_qpace = {
596 .name = "qnm_qpace",
597 .channels = 1,
598 .buswidth = 32,
599 .qosbox = &(const struct qcom_icc_qosbox) {
600 .num_ports = 1,
601 .port_offsets = { 0x153000 },
602 .prio = 0,
603 .urg_fwd = 0,
604 .prio_fwd_disable = 1,
605 },
606 .num_links = 1,
607 .link_nodes = { &qns_llcc },
608};
609
610static struct qcom_icc_node qsm_cfg_south = {
611 .name = "qsm_cfg_south",
612 .channels = 1,
613 .buswidth = 4,
614 .num_links = 8,
615 .link_nodes = { &qhs_i2c, &qhs_pcie_cfg,
616 &qhs_pcie_g4x1_cfg, &qhs_qspi,
617 &qhs_qup3, &qhs_qup5,
618 &qhs_sdc4, &qss_pcie_anoc_cfg },
619};
620
621static struct qcom_icc_node qss_stdst_south_cfg = {
622 .name = "qss_stdst_south_cfg",
623 .channels = 1,
624 .buswidth = 4,
625 .num_links = 1,
626 .link_nodes = { &qsm_cfg_south },
627};
628
629static struct qcom_icc_node qsm_cnoc_main = {
630 .name = "qsm_cnoc_main",
631 .channels = 1,
632 .buswidth = 4,
633 .num_links = 7,
634 .link_nodes = { &qss_stdst_center_cfg, &qss_stdst_east_cfg,
635 &qss_stdst_mm_hf_cfg, &qss_stdst_mm_sf_cfg,
636 &qss_stdst_north_cfg, &qss_stdst_south_cfg,
637 &qss_stdst_west_cfg },
638};
639
640static struct qcom_icc_node qss_cfg = {
641 .name = "qss_cfg",
642 .channels = 1,
643 .buswidth = 4,
644 .num_links = 1,
645 .link_nodes = { &qsm_cnoc_main },
646};
647
648static struct qcom_icc_node qnm_gemnoc_cnoc = {
649 .name = "qnm_gemnoc_cnoc",
650 .channels = 1,
651 .buswidth = 16,
652 .num_links = 8,
653 .link_nodes = { &qhs_aoss, &qhs_ipa,
654 &qhs_ipc_router_fence, &qhs_soccp,
655 &qhs_tme_cfg, &qss_cfg,
656 &qss_ddrss_cfg, &qxs_imem },
657};
658
659static struct qcom_icc_node qns_gem_noc_cnoc = {
660 .name = "qns_gem_noc_cnoc",
661 .channels = 1,
662 .buswidth = 16,
663 .num_links = 1,
664 .link_nodes = { &qnm_gemnoc_cnoc },
665};
666
667static struct qcom_icc_node alm_gpu_tcu = {
668 .name = "alm_gpu_tcu",
669 .channels = 1,
670 .buswidth = 8,
671 .qosbox = &(const struct qcom_icc_qosbox) {
672 .num_ports = 1,
673 .port_offsets = { 0x145000 },
674 .prio = 1,
675 .urg_fwd = 0,
676 .prio_fwd_disable = 1,
677 },
678 .num_links = 2,
679 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
680};
681
682static struct qcom_icc_node alm_sys_tcu = {
683 .name = "alm_sys_tcu",
684 .channels = 1,
685 .buswidth = 8,
686 .qosbox = &(const struct qcom_icc_qosbox) {
687 .num_ports = 1,
688 .port_offsets = { 0x147000 },
689 .prio = 6,
690 .urg_fwd = 0,
691 .prio_fwd_disable = 1,
692 },
693 .num_links = 2,
694 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
695};
696
697static struct qcom_icc_node chm_apps = {
698 .name = "chm_apps",
699 .channels = 2,
700 .buswidth = 32,
701 .num_links = 3,
702 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
703 &qns_pcie },
704};
705
706static struct qcom_icc_node qnm_gpu = {
707 .name = "qnm_gpu",
708 .channels = 2,
709 .buswidth = 32,
710 .qosbox = &(const struct qcom_icc_qosbox) {
711 .num_ports = 2,
712 .port_offsets = { 0x51000, 0xd1000 },
713 .prio = 0,
714 .urg_fwd = 0,
715 .prio_fwd_disable = 1,
716 },
717 .num_links = 3,
718 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
719 &qns_pcie },
720};
721
722static struct qcom_icc_node qnm_lpass_gemnoc = {
723 .name = "qnm_lpass_gemnoc",
724 .channels = 1,
725 .buswidth = 32,
726 .qosbox = &(const struct qcom_icc_qosbox) {
727 .num_ports = 1,
728 .port_offsets = { 0x149000 },
729 .prio = 0,
730 .urg_fwd = 1,
731 .prio_fwd_disable = 0,
732 },
733 .num_links = 3,
734 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
735 &qns_pcie },
736};
737
738static struct qcom_icc_node qnm_mdsp = {
739 .name = "qnm_mdsp",
740 .channels = 1,
741 .buswidth = 16,
742 .num_links = 3,
743 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
744 &qns_pcie },
745};
746
747static struct qcom_icc_node qnm_mnoc_hf = {
748 .name = "qnm_mnoc_hf",
749 .channels = 2,
750 .buswidth = 32,
751 .qosbox = &(const struct qcom_icc_qosbox) {
752 .num_ports = 2,
753 .port_offsets = { 0x55000, 0xd5000 },
754 .prio = 0,
755 .urg_fwd = 1,
756 .prio_fwd_disable = 0,
757 },
758 .num_links = 3,
759 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
760 &qns_pcie },
761};
762
763static struct qcom_icc_node qnm_mnoc_sf = {
764 .name = "qnm_mnoc_sf",
765 .channels = 2,
766 .buswidth = 32,
767 .qosbox = &(const struct qcom_icc_qosbox) {
768 .num_ports = 2,
769 .port_offsets = { 0x57000, 0xd7000 },
770 .prio = 0,
771 .urg_fwd = 1,
772 .prio_fwd_disable = 0,
773 },
774 .num_links = 3,
775 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
776 &qns_pcie },
777};
778
779static struct qcom_icc_node qnm_nsp_gemnoc = {
780 .name = "qnm_nsp_gemnoc",
781 .channels = 2,
782 .buswidth = 32,
783 .qosbox = &(const struct qcom_icc_qosbox) {
784 .num_ports = 2,
785 .port_offsets = { 0x59000, 0xd9000 },
786 .prio = 0,
787 .urg_fwd = 0,
788 .prio_fwd_disable = 1,
789 },
790 .num_links = 3,
791 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
792 &qns_pcie },
793};
794
795static struct qcom_icc_node qnm_pcie = {
796 .name = "qnm_pcie",
797 .channels = 1,
798 .buswidth = 16,
799 .qosbox = &(const struct qcom_icc_qosbox) {
800 .num_ports = 1,
801 .port_offsets = { 0x14b000 },
802 .prio = 0,
803 .urg_fwd = 1,
804 .prio_fwd_disable = 0,
805 },
806 .num_links = 2,
807 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
808};
809
810static struct qcom_icc_node qnm_snoc_sf = {
811 .name = "qnm_snoc_sf",
812 .channels = 1,
813 .buswidth = 32,
814 .qosbox = &(const struct qcom_icc_qosbox) {
815 .num_ports = 1,
816 .port_offsets = { 0x14f000 },
817 .prio = 0,
818 .urg_fwd = 1,
819 .prio_fwd_disable = 0,
820 },
821 .num_links = 3,
822 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
823 &qns_pcie },
824};
825
826static struct qcom_icc_node qnm_wlan_q6 = {
827 .name = "qnm_wlan_q6",
828 .channels = 1,
829 .buswidth = 8,
830 .num_links = 3,
831 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
832 &qns_pcie },
833};
834
835static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
836 .name = "qns_lpass_ag_noc_gemnoc",
837 .channels = 1,
838 .buswidth = 32,
839 .num_links = 1,
840 .link_nodes = { &qnm_lpass_gemnoc },
841};
842
843static struct qcom_icc_node qns_mem_noc_hf = {
844 .name = "qns_mem_noc_hf",
845 .channels = 2,
846 .buswidth = 32,
847 .num_links = 1,
848 .link_nodes = { &qnm_mnoc_hf },
849};
850
851static struct qcom_icc_node qns_mem_noc_sf = {
852 .name = "qns_mem_noc_sf",
853 .channels = 2,
854 .buswidth = 32,
855 .num_links = 1,
856 .link_nodes = { &qnm_mnoc_sf },
857};
858
859static struct qcom_icc_node qns_nsp_gemnoc = {
860 .name = "qns_nsp_gemnoc",
861 .channels = 2,
862 .buswidth = 32,
863 .num_links = 1,
864 .link_nodes = { &qnm_nsp_gemnoc },
865};
866
867static struct qcom_icc_node qns_pcie_gemnoc = {
868 .name = "qns_pcie_gemnoc",
869 .channels = 1,
870 .buswidth = 16,
871 .num_links = 1,
872 .link_nodes = { &qnm_pcie },
873};
874
875static struct qcom_icc_node qns_gemnoc_sf = {
876 .name = "qns_gemnoc_sf",
877 .channels = 1,
878 .buswidth = 32,
879 .num_links = 1,
880 .link_nodes = { &qnm_snoc_sf },
881};
882
883static struct qcom_icc_node qnm_lpiaon_noc = {
884 .name = "qnm_lpiaon_noc",
885 .channels = 1,
886 .buswidth = 32,
887 .num_links = 1,
888 .link_nodes = { &qns_lpass_ag_noc_gemnoc },
889};
890
891static struct qcom_icc_node qnm_camnoc_hf = {
892 .name = "qnm_camnoc_hf",
893 .channels = 2,
894 .buswidth = 32,
895 .qosbox = &(const struct qcom_icc_qosbox) {
896 .num_ports = 2,
897 .port_offsets = { 0x50000, 0x51000 },
898 .prio = 0,
899 .urg_fwd = 1,
900 .prio_fwd_disable = 0,
901 },
902 .num_links = 1,
903 .link_nodes = { &qns_mem_noc_hf },
904};
905
906static struct qcom_icc_node qnm_mdp = {
907 .name = "qnm_mdp",
908 .channels = 2,
909 .buswidth = 32,
910 .qosbox = &(const struct qcom_icc_qosbox) {
911 .num_ports = 2,
912 .port_offsets = { 0x52000, 0x53000 },
913 .prio = 0,
914 .urg_fwd = 1,
915 .prio_fwd_disable = 0,
916 },
917 .num_links = 1,
918 .link_nodes = { &qns_mem_noc_hf },
919};
920
921static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = {
922 .name = "qnm_camnoc_nrt_icp_sf",
923 .channels = 1,
924 .buswidth = 8,
925 .qosbox = &(const struct qcom_icc_qosbox) {
926 .num_ports = 1,
927 .port_offsets = { 0x20000 },
928 .prio = 4,
929 .urg_fwd = 0,
930 .prio_fwd_disable = 1,
931 },
932 .num_links = 1,
933 .link_nodes = { &qns_mem_noc_sf },
934};
935
936static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = {
937 .name = "qnm_camnoc_rt_cdm_sf",
938 .channels = 1,
939 .buswidth = 8,
940 .qosbox = &(const struct qcom_icc_qosbox) {
941 .num_ports = 1,
942 .port_offsets = { 0x28000 },
943 .prio = 2,
944 .urg_fwd = 0,
945 .prio_fwd_disable = 1,
946 },
947 .num_links = 1,
948 .link_nodes = { &qns_mem_noc_sf },
949};
950
951static struct qcom_icc_node qnm_camnoc_sf = {
952 .name = "qnm_camnoc_sf",
953 .channels = 2,
954 .buswidth = 32,
955 .qosbox = &(const struct qcom_icc_qosbox) {
956 .num_ports = 2,
957 .port_offsets = { 0x21000, 0x22000 },
958 .prio = 0,
959 .urg_fwd = 1,
960 .prio_fwd_disable = 0,
961 },
962 .num_links = 1,
963 .link_nodes = { &qns_mem_noc_sf },
964};
965
966static struct qcom_icc_node qnm_mdss_dcp = {
967 .name = "qnm_mdss_dcp",
968 .channels = 1,
969 .buswidth = 8,
970 .qosbox = &(const struct qcom_icc_qosbox) {
971 .num_ports = 1,
972 .port_offsets = { 0x29000 },
973 .prio = 0,
974 .urg_fwd = 1,
975 .prio_fwd_disable = 0,
976 },
977 .num_links = 1,
978 .link_nodes = { &qns_mem_noc_sf },
979};
980
981static struct qcom_icc_node qnm_vapss_hcp = {
982 .name = "qnm_vapss_hcp",
983 .channels = 1,
984 .buswidth = 32,
985 .num_links = 1,
986 .link_nodes = { &qns_mem_noc_sf },
987};
988
989static struct qcom_icc_node qnm_video_cv_cpu = {
990 .name = "qnm_video_cv_cpu",
991 .channels = 1,
992 .buswidth = 8,
993 .qosbox = &(const struct qcom_icc_qosbox) {
994 .num_ports = 1,
995 .port_offsets = { 0x24000 },
996 .prio = 4,
997 .urg_fwd = 0,
998 .prio_fwd_disable = 1,
999 },
1000 .num_links = 1,
1001 .link_nodes = { &qns_mem_noc_sf },
1002};
1003
1004static struct qcom_icc_node qnm_video_eva = {
1005 .name = "qnm_video_eva",
1006 .channels = 2,
1007 .buswidth = 32,
1008 .qosbox = &(const struct qcom_icc_qosbox) {
1009 .num_ports = 2,
1010 .port_offsets = { 0x25000, 0x26000 },
1011 .prio = 0,
1012 .urg_fwd = 1,
1013 .prio_fwd_disable = 0,
1014 },
1015 .num_links = 1,
1016 .link_nodes = { &qns_mem_noc_sf },
1017};
1018
1019static struct qcom_icc_node qnm_video_mvp = {
1020 .name = "qnm_video_mvp",
1021 .channels = 1,
1022 .buswidth = 32,
1023 .qosbox = &(const struct qcom_icc_qosbox) {
1024 .num_ports = 1,
1025 .port_offsets = { 0x23000 },
1026 .prio = 0,
1027 .urg_fwd = 1,
1028 .prio_fwd_disable = 0,
1029 },
1030 .num_links = 1,
1031 .link_nodes = { &qns_mem_noc_sf },
1032};
1033
1034static struct qcom_icc_node qnm_video_v_cpu = {
1035 .name = "qnm_video_v_cpu",
1036 .channels = 1,
1037 .buswidth = 8,
1038 .qosbox = &(const struct qcom_icc_qosbox) {
1039 .num_ports = 1,
1040 .port_offsets = { 0x27000 },
1041 .prio = 4,
1042 .urg_fwd = 0,
1043 .prio_fwd_disable = 1,
1044 },
1045 .num_links = 1,
1046 .link_nodes = { &qns_mem_noc_sf },
1047};
1048
1049static struct qcom_icc_node qnm_nsp = {
1050 .name = "qnm_nsp",
1051 .channels = 2,
1052 .buswidth = 32,
1053 .num_links = 1,
1054 .link_nodes = { &qns_nsp_gemnoc },
1055};
1056
1057static struct qcom_icc_node xm_pcie = {
1058 .name = "xm_pcie",
1059 .channels = 1,
1060 .buswidth = 8,
1061 .qosbox = &(const struct qcom_icc_qosbox) {
1062 .num_ports = 1,
1063 .port_offsets = { 0xc000 },
1064 .prio = 3,
1065 .urg_fwd = 0,
1066 .prio_fwd_disable = 1,
1067 },
1068 .num_links = 1,
1069 .link_nodes = { &qns_pcie_gemnoc },
1070};
1071
1072static struct qcom_icc_node xm_pcie_g4x1 = {
1073 .name = "xm_pcie_g4x1",
1074 .channels = 1,
1075 .buswidth = 8,
1076 .qosbox = &(const struct qcom_icc_qosbox) {
1077 .num_ports = 1,
1078 .port_offsets = { 0xd000 },
1079 .prio = 2,
1080 .urg_fwd = 0,
1081 .prio_fwd_disable = 1,
1082 },
1083 .num_links = 1,
1084 .link_nodes = { &qns_pcie_gemnoc },
1085};
1086
1087static struct qcom_icc_node qnm_aggre_noc = {
1088 .name = "qnm_aggre_noc",
1089 .channels = 1,
1090 .buswidth = 32,
1091 .qosbox = &(const struct qcom_icc_qosbox) {
1092 .num_ports = 1,
1093 .port_offsets = { 0x20000 },
1094 .prio = 2,
1095 .urg_fwd = 1,
1096 .prio_fwd_disable = 0,
1097 },
1098 .num_links = 1,
1099 .link_nodes = { &qns_gemnoc_sf },
1100};
1101
1102static struct qcom_icc_node qnm_apss_noc = {
1103 .name = "qnm_apss_noc",
1104 .channels = 1,
1105 .buswidth = 8,
1106 .qosbox = &(const struct qcom_icc_qosbox) {
1107 .num_ports = 1,
1108 .port_offsets = { 0x1e000 },
1109 .prio = 2,
1110 .urg_fwd = 0,
1111 .prio_fwd_disable = 1,
1112 },
1113 .num_links = 1,
1114 .link_nodes = { &qns_gemnoc_sf },
1115};
1116
1117static struct qcom_icc_node qnm_cnoc_data = {
1118 .name = "qnm_cnoc_data",
1119 .channels = 1,
1120 .buswidth = 8,
1121 .qosbox = &(const struct qcom_icc_qosbox) {
1122 .num_ports = 1,
1123 .port_offsets = { 0x1f000 },
1124 .prio = 2,
1125 .urg_fwd = 0,
1126 .prio_fwd_disable = 1,
1127 },
1128 .num_links = 1,
1129 .link_nodes = { &qns_gemnoc_sf },
1130};
1131
1132static struct qcom_icc_node qns_a1noc_snoc = {
1133 .name = "qns_a1noc_snoc",
1134 .channels = 1,
1135 .buswidth = 32,
1136 .num_links = 1,
1137 .link_nodes = { &qnm_aggre_noc },
1138};
1139
1140static struct qcom_icc_node qns_lpass_aggnoc = {
1141 .name = "qns_lpass_aggnoc",
1142 .channels = 1,
1143 .buswidth = 32,
1144 .num_links = 1,
1145 .link_nodes = { &qnm_lpiaon_noc },
1146};
1147
1148static struct qcom_icc_node qhm_qspi = {
1149 .name = "qhm_qspi",
1150 .channels = 1,
1151 .buswidth = 4,
1152 .qosbox = &(const struct qcom_icc_qosbox) {
1153 .num_ports = 1,
1154 .port_offsets = { 0x49000 },
1155 .prio = 0,
1156 .urg_fwd = 0,
1157 .prio_fwd_disable = 1,
1158 },
1159 .num_links = 1,
1160 .link_nodes = { &qns_a1noc_snoc },
1161};
1162
1163static struct qcom_icc_node qhm_qup2 = {
1164 .name = "qhm_qup2",
1165 .channels = 1,
1166 .buswidth = 4,
1167 .qosbox = &(const struct qcom_icc_qosbox) {
1168 .num_ports = 1,
1169 .port_offsets = { 0x48000 },
1170 .prio = 0,
1171 .urg_fwd = 0,
1172 .prio_fwd_disable = 1,
1173 },
1174 .num_links = 1,
1175 .link_nodes = { &qns_a1noc_snoc },
1176};
1177
1178static struct qcom_icc_node qhm_qup3 = {
1179 .name = "qhm_qup3",
1180 .channels = 1,
1181 .buswidth = 4,
1182 .qosbox = &(const struct qcom_icc_qosbox) {
1183 .num_ports = 1,
1184 .port_offsets = { 0x46000 },
1185 .prio = 0,
1186 .urg_fwd = 0,
1187 .prio_fwd_disable = 1,
1188 },
1189 .num_links = 1,
1190 .link_nodes = { &qns_a1noc_snoc },
1191};
1192
1193static struct qcom_icc_node qhm_qup4 = {
1194 .name = "qhm_qup4",
1195 .channels = 1,
1196 .buswidth = 4,
1197 .qosbox = &(const struct qcom_icc_qosbox) {
1198 .num_ports = 1,
1199 .port_offsets = { 0x47000 },
1200 .prio = 0,
1201 .urg_fwd = 0,
1202 .prio_fwd_disable = 1,
1203 },
1204 .num_links = 1,
1205 .link_nodes = { &qns_a1noc_snoc },
1206};
1207
1208static struct qcom_icc_node qhm_qup5 = {
1209 .name = "qhm_qup5",
1210 .channels = 1,
1211 .buswidth = 4,
1212 .qosbox = &(const struct qcom_icc_qosbox) {
1213 .num_ports = 1,
1214 .port_offsets = { 0x4e000 },
1215 .prio = 0,
1216 .urg_fwd = 0,
1217 .prio_fwd_disable = 1,
1218 },
1219 .num_links = 1,
1220 .link_nodes = { &qns_a1noc_snoc },
1221};
1222
1223static struct qcom_icc_node qxm_crypto = {
1224 .name = "qxm_crypto",
1225 .channels = 1,
1226 .buswidth = 32,
1227 .qosbox = &(const struct qcom_icc_qosbox) {
1228 .num_ports = 1,
1229 .port_offsets = { 0x40000 },
1230 .prio = 0,
1231 .urg_fwd = 0,
1232 .prio_fwd_disable = 1,
1233 },
1234 .num_links = 1,
1235 .link_nodes = { &qns_a1noc_snoc },
1236};
1237
1238static struct qcom_icc_node qxm_ipa = {
1239 .name = "qxm_ipa",
1240 .channels = 1,
1241 .buswidth = 16,
1242 .qosbox = &(const struct qcom_icc_qosbox) {
1243 .num_ports = 1,
1244 .port_offsets = { 0x41000 },
1245 .prio = 0,
1246 .urg_fwd = 0,
1247 .prio_fwd_disable = 1,
1248 },
1249 .num_links = 1,
1250 .link_nodes = { &qns_a1noc_snoc },
1251};
1252
1253static struct qcom_icc_node qxm_qup1 = {
1254 .name = "qxm_qup1",
1255 .channels = 1,
1256 .buswidth = 8,
1257 .qosbox = &(const struct qcom_icc_qosbox) {
1258 .num_ports = 1,
1259 .port_offsets = { 0x4d000 },
1260 .prio = 0,
1261 .urg_fwd = 0,
1262 .prio_fwd_disable = 1,
1263 },
1264 .num_links = 1,
1265 .link_nodes = { &qns_a1noc_snoc },
1266};
1267
1268static struct qcom_icc_node qxm_soccp = {
1269 .name = "qxm_soccp",
1270 .channels = 1,
1271 .buswidth = 8,
1272 .qosbox = &(const struct qcom_icc_qosbox) {
1273 .num_ports = 1,
1274 .port_offsets = { 0x45000 },
1275 .prio = 0,
1276 .urg_fwd = 0,
1277 .prio_fwd_disable = 1,
1278 },
1279 .num_links = 1,
1280 .link_nodes = { &qns_a1noc_snoc },
1281};
1282
1283static struct qcom_icc_node xm_qdss_etr_0 = {
1284 .name = "xm_qdss_etr_0",
1285 .channels = 1,
1286 .buswidth = 8,
1287 .qosbox = &(const struct qcom_icc_qosbox) {
1288 .num_ports = 1,
1289 .port_offsets = { 0x42000 },
1290 .prio = 0,
1291 .urg_fwd = 0,
1292 .prio_fwd_disable = 1,
1293 },
1294 .num_links = 1,
1295 .link_nodes = { &qns_a1noc_snoc },
1296};
1297
1298static struct qcom_icc_node xm_qdss_etr_1 = {
1299 .name = "xm_qdss_etr_1",
1300 .channels = 1,
1301 .buswidth = 8,
1302 .qosbox = &(const struct qcom_icc_qosbox) {
1303 .num_ports = 1,
1304 .port_offsets = { 0x43000 },
1305 .prio = 0,
1306 .urg_fwd = 0,
1307 .prio_fwd_disable = 1,
1308 },
1309 .num_links = 1,
1310 .link_nodes = { &qns_a1noc_snoc },
1311};
1312
1313static struct qcom_icc_node xm_sdc2 = {
1314 .name = "xm_sdc2",
1315 .channels = 1,
1316 .buswidth = 8,
1317 .qosbox = &(const struct qcom_icc_qosbox) {
1318 .num_ports = 1,
1319 .port_offsets = { 0x44000 },
1320 .prio = 0,
1321 .urg_fwd = 0,
1322 .prio_fwd_disable = 1,
1323 },
1324 .num_links = 1,
1325 .link_nodes = { &qns_a1noc_snoc },
1326};
1327
1328static struct qcom_icc_node xm_sdc4 = {
1329 .name = "xm_sdc4",
1330 .channels = 1,
1331 .buswidth = 8,
1332 .num_links = 1,
1333 .link_nodes = { &qns_a1noc_snoc },
1334};
1335
1336static struct qcom_icc_node xm_ufs_mem = {
1337 .name = "xm_ufs_mem",
1338 .channels = 1,
1339 .buswidth = 32,
1340 .qosbox = &(const struct qcom_icc_qosbox) {
1341 .num_ports = 1,
1342 .port_offsets = { 0x4b000 },
1343 .prio = 0,
1344 .urg_fwd = 0,
1345 .prio_fwd_disable = 1,
1346 },
1347 .num_links = 1,
1348 .link_nodes = { &qns_a1noc_snoc },
1349};
1350
1351static struct qcom_icc_node xm_usb3 = {
1352 .name = "xm_usb3",
1353 .channels = 1,
1354 .buswidth = 8,
1355 .qosbox = &(const struct qcom_icc_qosbox) {
1356 .num_ports = 1,
1357 .port_offsets = { 0x4c000 },
1358 .prio = 0,
1359 .urg_fwd = 0,
1360 .prio_fwd_disable = 1,
1361 },
1362 .num_links = 1,
1363 .link_nodes = { &qns_a1noc_snoc },
1364};
1365
1366static struct qcom_icc_node qnm_lpass_lpinoc = {
1367 .name = "qnm_lpass_lpinoc",
1368 .channels = 1,
1369 .buswidth = 32,
1370 .num_links = 2,
1371 .link_nodes = { &qns_llc_lpinoc, &qns_lpass_aggnoc },
1372};
1373
1374static struct qcom_icc_node qns_lpi_aon_noc = {
1375 .name = "qns_lpi_aon_noc",
1376 .channels = 1,
1377 .buswidth = 32,
1378 .num_links = 1,
1379 .link_nodes = { &qnm_lpass_lpinoc },
1380};
1381
1382static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
1383 .name = "qnm_lpinoc_dsp_qns4m",
1384 .channels = 1,
1385 .buswidth = 32,
1386 .num_links = 1,
1387 .link_nodes = { &qns_lpi_aon_noc },
1388};
1389
1390static struct qcom_icc_bcm bcm_acv = {
1391 .name = "ACV",
1392 .enable_mask = BIT(3),
1393 .num_nodes = 1,
1394 .nodes = { &ebi },
1395};
1396
1397static struct qcom_icc_bcm bcm_ce0 = {
1398 .name = "CE0",
1399 .num_nodes = 1,
1400 .nodes = { &qxm_crypto },
1401};
1402
1403static struct qcom_icc_bcm bcm_cn0 = {
1404 .name = "CN0",
1405 .enable_mask = BIT(0),
1406 .keepalive = true,
1407 .num_nodes = 25,
1408 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1409 &qhs_aoss, &qhs_ipa,
1410 &qhs_ipc_router_fence, &qhs_soccp,
1411 &qhs_tme_cfg, &qss_cfg,
1412 &qss_ddrss_cfg, &qxs_imem,
1413 &xs_pcie, &xs_pcie_g4x1,
1414 &qsm_cfg_center, &qsm_cfg_east,
1415 &qsm_cfg_mm_hf, &qsm_cfg_mm_sf,
1416 &qsm_cfg_north, &qsm_cfg_south,
1417 &qsm_cfg_west, &qhs_ahb2phy0,
1418 &qhs_boot_rom, &qhs_camera_cfg,
1419 &qhs_clk_ctl, &qhs_crypto_cfg,
1420 &qhs_eva_cfg },
1421};
1422
1423static struct qcom_icc_bcm bcm_cn1 = {
1424 .name = "CN1",
1425 .num_nodes = 6,
1426 .nodes = { &qhs_display_cfg, &qhs_qup1,
1427 &qhs_qup2, &qhs_qup3,
1428 &qhs_qup4, &qhs_qup5 },
1429};
1430
1431static struct qcom_icc_bcm bcm_co0 = {
1432 .name = "CO0",
1433 .enable_mask = BIT(0),
1434 .num_nodes = 2,
1435 .nodes = { &qnm_nsp, &qns_nsp_gemnoc },
1436};
1437
1438static struct qcom_icc_bcm bcm_de0 = {
1439 .name = "DE0",
1440 .enable_mask = BIT(0),
1441 .num_nodes = 1,
1442 .nodes = { &ddr_eff_veto_slave },
1443};
1444
1445static struct qcom_icc_bcm bcm_lp0 = {
1446 .name = "LP0",
1447 .num_nodes = 5,
1448 .nodes = { &qnm_lpiaon_noc_llclpi_noc, &qns_lb,
1449 &qnm_lpass_lpinoc, &qns_llc_lpinoc,
1450 &qns_lpass_aggnoc },
1451};
1452
1453static struct qcom_icc_bcm bcm_mc0 = {
1454 .name = "MC0",
1455 .keepalive = true,
1456 .num_nodes = 1,
1457 .nodes = { &ebi },
1458};
1459
1460static struct qcom_icc_bcm bcm_mc5 = {
1461 .name = "MC5",
1462 .num_nodes = 1,
1463 .nodes = { &ddr_rt_slave },
1464};
1465
1466static struct qcom_icc_bcm bcm_mm0 = {
1467 .name = "MM0",
1468 .num_nodes = 1,
1469 .nodes = { &qns_mem_noc_hf },
1470};
1471
1472static struct qcom_icc_bcm bcm_mm1 = {
1473 .name = "MM1",
1474 .enable_mask = BIT(0),
1475 .num_nodes = 9,
1476 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf,
1477 &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf,
1478 &qnm_vapss_hcp, &qnm_video_cv_cpu,
1479 &qnm_video_mvp, &qnm_video_v_cpu,
1480 &qns_mem_noc_sf },
1481};
1482
1483static struct qcom_icc_bcm bcm_qpc0 = {
1484 .name = "QPC0",
1485 .num_nodes = 1,
1486 .nodes = { &qnm_qpace },
1487};
1488
1489static struct qcom_icc_bcm bcm_qup0 = {
1490 .name = "QUP0",
1491 .vote_scale = 1,
1492 .keepalive = true,
1493 .num_nodes = 1,
1494 .nodes = { &qup0_core_slave },
1495};
1496
1497static struct qcom_icc_bcm bcm_qup1 = {
1498 .name = "QUP1",
1499 .vote_scale = 1,
1500 .keepalive = true,
1501 .num_nodes = 1,
1502 .nodes = { &qup1_core_slave },
1503};
1504
1505static struct qcom_icc_bcm bcm_qup2 = {
1506 .name = "QUP2",
1507 .vote_scale = 1,
1508 .keepalive = true,
1509 .num_nodes = 1,
1510 .nodes = { &qup2_core_slave },
1511};
1512
1513static struct qcom_icc_bcm bcm_qup3 = {
1514 .name = "QUP3",
1515 .vote_scale = 1,
1516 .keepalive = true,
1517 .num_nodes = 1,
1518 .nodes = { &qup3_core_slave },
1519};
1520
1521static struct qcom_icc_bcm bcm_qup4 = {
1522 .name = "QUP4",
1523 .vote_scale = 1,
1524 .keepalive = true,
1525 .num_nodes = 1,
1526 .nodes = { &qup4_core_slave },
1527};
1528
1529static struct qcom_icc_bcm bcm_qup5 = {
1530 .name = "QUP5",
1531 .vote_scale = 1,
1532 .keepalive = true,
1533 .num_nodes = 1,
1534 .nodes = { &qup5_core_slave },
1535};
1536
1537static struct qcom_icc_bcm bcm_sh0 = {
1538 .name = "SH0",
1539 .keepalive = true,
1540 .num_nodes = 1,
1541 .nodes = { &qns_llcc },
1542};
1543
1544static struct qcom_icc_bcm bcm_sh1 = {
1545 .name = "SH1",
1546 .enable_mask = BIT(0),
1547 .num_nodes = 15,
1548 .nodes = { &alm_gic, &alm_gpu_tcu,
1549 &alm_sys_tcu, &chm_apps,
1550 &qnm_gpu, &qnm_lpass_gemnoc,
1551 &qnm_mdsp, &qnm_mnoc_hf,
1552 &qnm_mnoc_sf, &qnm_nsp_gemnoc,
1553 &qnm_pcie, &qnm_snoc_sf,
1554 &qnm_wlan_q6, &qns_gem_noc_cnoc,
1555 &qns_pcie },
1556};
1557
1558static struct qcom_icc_bcm bcm_sn0 = {
1559 .name = "SN0",
1560 .keepalive = true,
1561 .num_nodes = 1,
1562 .nodes = { &qns_gemnoc_sf },
1563};
1564
1565static struct qcom_icc_bcm bcm_sn2 = {
1566 .name = "SN2",
1567 .num_nodes = 1,
1568 .nodes = { &qnm_aggre_noc },
1569};
1570
1571static struct qcom_icc_bcm bcm_sn3 = {
1572 .name = "SN3",
1573 .num_nodes = 1,
1574 .nodes = { &qns_pcie_gemnoc },
1575};
1576
1577static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1578 &bcm_ce0,
1579};
1580
1581static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1582 [MASTER_QSPI_0] = &qhm_qspi,
1583 [MASTER_QUP_2] = &qhm_qup2,
1584 [MASTER_QUP_3] = &qhm_qup3,
1585 [MASTER_QUP_4] = &qhm_qup4,
1586 [MASTER_QUP_5] = &qhm_qup5,
1587 [MASTER_CRYPTO] = &qxm_crypto,
1588 [MASTER_IPA] = &qxm_ipa,
1589 [MASTER_QUP_1] = &qxm_qup1,
1590 [MASTER_SOCCP_PROC] = &qxm_soccp,
1591 [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1592 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1593 [MASTER_SDCC_2] = &xm_sdc2,
1594 [MASTER_SDCC_4] = &xm_sdc4,
1595 [MASTER_UFS_MEM] = &xm_ufs_mem,
1596 [MASTER_USB3] = &xm_usb3,
1597 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1598};
1599
1600static const struct regmap_config maili_aggre1_noc_regmap_config = {
1601 .reg_bits = 32,
1602 .reg_stride = 4,
1603 .val_bits = 32,
1604 .max_register = 0x56200,
1605 .fast_io = true,
1606};
1607
1608static const struct qcom_icc_desc maili_aggre1_noc = {
1609 .config = &maili_aggre1_noc_regmap_config,
1610 .nodes = aggre1_noc_nodes,
1611 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1612 .bcms = aggre1_noc_bcms,
1613 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1614 .qos_requires_clocks = true,
1615};
1616
1617static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1618 &bcm_de0,
1619 &bcm_qup0,
1620 &bcm_qup1,
1621 &bcm_qup2,
1622 &bcm_qup3,
1623 &bcm_qup4,
1624 &bcm_qup5,
1625};
1626
1627static struct qcom_icc_node * const clk_virt_nodes[] = {
1628 [MASTER_DDR_EFF_VETO] = &ddr_eff_veto_master,
1629 [MASTER_QUP_CORE_0] = &qup0_core_master,
1630 [MASTER_QUP_CORE_1] = &qup1_core_master,
1631 [MASTER_QUP_CORE_2] = &qup2_core_master,
1632 [MASTER_QUP_CORE_3] = &qup3_core_master,
1633 [MASTER_QUP_CORE_4] = &qup4_core_master,
1634 [MASTER_QUP_CORE_5] = &qup5_core_master,
1635 [SLAVE_DDR_EFF_VETO] = &ddr_eff_veto_slave,
1636 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1637 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1638 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1639 [SLAVE_QUP_CORE_3] = &qup3_core_slave,
1640 [SLAVE_QUP_CORE_4] = &qup4_core_slave,
1641 [SLAVE_QUP_CORE_5] = &qup5_core_slave,
1642};
1643
1644static const struct qcom_icc_desc maili_clk_virt = {
1645 .nodes = clk_virt_nodes,
1646 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1647 .bcms = clk_virt_bcms,
1648 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1649};
1650
1651static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1652 &bcm_cn0,
1653};
1654
1655static struct qcom_icc_node * const cnoc_main_nodes[] = {
1656 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1657 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1658 [SLAVE_AOSS] = &qhs_aoss,
1659 [SLAVE_IPA_CFG] = &qhs_ipa,
1660 [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence,
1661 [SLAVE_SOCCP] = &qhs_soccp,
1662 [SLAVE_TME_CFG] = &qhs_tme_cfg,
1663 [SLAVE_CNOC_CFG] = &qss_cfg,
1664 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1665 [SLAVE_IMEM] = &qxs_imem,
1666 [SLAVE_PCIE_0] = &xs_pcie,
1667 [SLAVE_PCIE_1] = &xs_pcie_g4x1,
1668};
1669
1670static const struct regmap_config maili_cnoc_main_regmap_config = {
1671 .reg_bits = 32,
1672 .reg_stride = 4,
1673 .val_bits = 32,
1674 .max_register = 0x20000,
1675 .fast_io = true,
1676};
1677
1678static const struct qcom_icc_desc maili_cnoc_main = {
1679 .config = &maili_cnoc_main_regmap_config,
1680 .nodes = cnoc_main_nodes,
1681 .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1682 .bcms = cnoc_main_bcms,
1683 .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1684};
1685
1686static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1687 &bcm_qpc0,
1688 &bcm_sh0,
1689 &bcm_sh1,
1690};
1691
1692static struct qcom_icc_node * const gem_noc_nodes[] = {
1693 [MASTER_GIC] = &alm_gic,
1694 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1695 [MASTER_SYS_TCU] = &alm_sys_tcu,
1696 [MASTER_APPSS_PROC] = &chm_apps,
1697 [MASTER_GFX3D] = &qnm_gpu,
1698 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1699 [MASTER_MSS_PROC] = &qnm_mdsp,
1700 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1701 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1702 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1703 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1704 [MASTER_QPACE] = &qnm_qpace,
1705 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1706 [MASTER_WLAN_Q6] = &qnm_wlan_q6,
1707 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1708 [SLAVE_LLCC] = &qns_llcc,
1709 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1710};
1711
1712static const struct regmap_config maili_gem_noc_regmap_config = {
1713 .reg_bits = 32,
1714 .reg_stride = 4,
1715 .val_bits = 32,
1716 .max_register = 0x160200,
1717 .fast_io = true,
1718};
1719
1720static const struct qcom_icc_desc maili_gem_noc = {
1721 .config = &maili_gem_noc_regmap_config,
1722 .nodes = gem_noc_nodes,
1723 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1724 .bcms = gem_noc_bcms,
1725 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1726};
1727
1728static struct qcom_icc_bcm * const llclpi_noc_bcms[] = {
1729 &bcm_lp0,
1730};
1731
1732static struct qcom_icc_node * const llclpi_noc_nodes[] = {
1733 [MASTER_LPIAON_NOC_LLCLPI_NOC] = &qnm_lpiaon_noc_llclpi_noc,
1734 [SLAVE_LPASS_LPI_CC] = &qhs_lpi_cc,
1735 [SLAVE_LLCC_ISLAND] = &qns_lb,
1736 [SLAVE_SERVICE_LLCLPI_NOC] = &srvc_llclpi_noc,
1737 [SLAVE_SERVICE_LLCLPI_NOC_CHIPCX] = &srvc_llclpi_noc_chipcx,
1738};
1739
1740static const struct regmap_config maili_llclpi_noc_regmap_config = {
1741 .reg_bits = 32,
1742 .reg_stride = 4,
1743 .val_bits = 32,
1744 .max_register = 0x17200,
1745 .fast_io = true,
1746};
1747
1748static const struct qcom_icc_desc maili_llclpi_noc = {
1749 .config = &maili_llclpi_noc_regmap_config,
1750 .nodes = llclpi_noc_nodes,
1751 .num_nodes = ARRAY_SIZE(llclpi_noc_nodes),
1752 .bcms = llclpi_noc_bcms,
1753 .num_bcms = ARRAY_SIZE(llclpi_noc_bcms),
1754};
1755
1756static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1757 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1758 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1759};
1760
1761static const struct regmap_config maili_lpass_ag_noc_regmap_config = {
1762 .reg_bits = 32,
1763 .reg_stride = 4,
1764 .val_bits = 32,
1765 .max_register = 0xc080,
1766 .fast_io = true,
1767};
1768
1769static const struct qcom_icc_desc maili_lpass_ag_noc = {
1770 .config = &maili_lpass_ag_noc_regmap_config,
1771 .nodes = lpass_ag_noc_nodes,
1772 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1773};
1774
1775static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1776 &bcm_lp0,
1777};
1778
1779static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1780 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
1781 [SLAVE_LPIAON_NOC_LLCLPI_NOC] = &qns_llc_lpinoc,
1782 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
1783};
1784
1785static const struct regmap_config maili_lpass_lpiaon_noc_regmap_config = {
1786 .reg_bits = 32,
1787 .reg_stride = 4,
1788 .val_bits = 32,
1789 .max_register = 0x19080,
1790 .fast_io = true,
1791};
1792
1793static const struct qcom_icc_desc maili_lpass_lpiaon_noc = {
1794 .config = &maili_lpass_lpiaon_noc_regmap_config,
1795 .nodes = lpass_lpiaon_noc_nodes,
1796 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
1797 .bcms = lpass_lpiaon_noc_bcms,
1798 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
1799};
1800
1801static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
1802 [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m,
1803 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
1804};
1805
1806static const struct regmap_config maili_lpass_lpicx_noc_regmap_config = {
1807 .reg_bits = 32,
1808 .reg_stride = 4,
1809 .val_bits = 32,
1810 .max_register = 0x46080,
1811 .fast_io = true,
1812};
1813
1814static const struct qcom_icc_desc maili_lpass_lpicx_noc = {
1815 .config = &maili_lpass_lpicx_noc_regmap_config,
1816 .nodes = lpass_lpicx_noc_nodes,
1817 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
1818};
1819
1820static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1821 &bcm_acv,
1822 &bcm_mc0,
1823 &bcm_mc5,
1824};
1825
1826static struct qcom_icc_node * const mc_virt_nodes[] = {
1827 [MASTER_LLCC] = &llcc_mc,
1828 [MASTER_DDR_RT] = &ddr_rt_mc,
1829 [SLAVE_EBI1] = &ebi,
1830 [SLAVE_DDR_RT] = &ddr_rt_slave,
1831};
1832
1833static const struct qcom_icc_desc maili_mc_virt = {
1834 .nodes = mc_virt_nodes,
1835 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1836 .bcms = mc_virt_bcms,
1837 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1838};
1839
1840static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1841 &bcm_mm0,
1842 &bcm_mm1,
1843};
1844
1845static struct qcom_icc_node * const mmss_noc_nodes[] = {
1846 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1847 [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
1848 [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf,
1849 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1850 [MASTER_MDP] = &qnm_mdp,
1851 [MASTER_MDSS_DCP] = &qnm_mdss_dcp,
1852 [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1853 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1854 [MASTER_VIDEO_EVA] = &qnm_video_eva,
1855 [MASTER_VIDEO_MVP] = &qnm_video_mvp,
1856 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1857 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1858 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1859};
1860
1861static const struct regmap_config maili_mmss_noc_regmap_config = {
1862 .reg_bits = 32,
1863 .reg_stride = 4,
1864 .val_bits = 32,
1865 .max_register = 0x5f800,
1866 .fast_io = true,
1867};
1868
1869static const struct qcom_icc_desc maili_mmss_noc = {
1870 .config = &maili_mmss_noc_regmap_config,
1871 .nodes = mmss_noc_nodes,
1872 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1873 .bcms = mmss_noc_bcms,
1874 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1875};
1876
1877static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1878 &bcm_co0,
1879};
1880
1881static struct qcom_icc_node * const nsp_noc_nodes[] = {
1882 [MASTER_CDSP_PROC] = &qnm_nsp,
1883 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1884};
1885
1886static const struct regmap_config maili_nsp_noc_regmap_config = {
1887 .reg_bits = 32,
1888 .reg_stride = 4,
1889 .val_bits = 32,
1890 .max_register = 0x21280,
1891 .fast_io = true,
1892};
1893
1894static const struct qcom_icc_desc maili_nsp_noc = {
1895 .config = &maili_nsp_noc_regmap_config,
1896 .nodes = nsp_noc_nodes,
1897 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1898 .bcms = nsp_noc_bcms,
1899 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1900};
1901
1902static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1903 &bcm_sn3,
1904};
1905
1906static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1907 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
1908 [MASTER_PCIE_0] = &xm_pcie,
1909 [MASTER_PCIE_1] = &xm_pcie_g4x1,
1910 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
1911 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1912};
1913
1914static const struct regmap_config maili_pcie_anoc_regmap_config = {
1915 .reg_bits = 32,
1916 .reg_stride = 4,
1917 .val_bits = 32,
1918 .max_register = 0x12400,
1919 .fast_io = true,
1920};
1921
1922static const struct qcom_icc_desc maili_pcie_anoc = {
1923 .config = &maili_pcie_anoc_regmap_config,
1924 .nodes = pcie_anoc_nodes,
1925 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1926 .bcms = pcie_anoc_bcms,
1927 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1928 .qos_requires_clocks = true,
1929};
1930
1931static struct qcom_icc_bcm * const stdst_cfg_bcms[] = {
1932 &bcm_cn0,
1933 &bcm_cn1,
1934};
1935
1936static struct qcom_icc_node * const stdst_cfg_nodes[] = {
1937 [MASTER_CFG_CENTER] = &qsm_cfg_center,
1938 [MASTER_CFG_EAST] = &qsm_cfg_east,
1939 [MASTER_CFG_MM_HF] = &qsm_cfg_mm_hf,
1940 [MASTER_CFG_MM_SF] = &qsm_cfg_mm_sf,
1941 [MASTER_CFG_NORTH] = &qsm_cfg_north,
1942 [MASTER_CFG_SOUTH] = &qsm_cfg_south,
1943 [MASTER_CFG_WEST] = &qsm_cfg_west,
1944 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1945 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
1946 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1947 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1948 [SLAVE_CRYPTO_CFG] = &qhs_crypto_cfg,
1949 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1950 [SLAVE_EVA_CFG] = &qhs_eva_cfg,
1951 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1952 [SLAVE_I2C] = &qhs_i2c,
1953 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1954 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1955 [SLAVE_IRIS_CFG] = &qhs_iris_cfg,
1956 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1957 [SLAVE_PCIE_0_CFG] = &qhs_pcie_cfg,
1958 [SLAVE_PCIE_1_CFG] = &qhs_pcie_g4x1_cfg,
1959 [SLAVE_PRNG] = &qhs_prng,
1960 [SLAVE_QSPI_0] = &qhs_qspi,
1961 [SLAVE_QUP_1] = &qhs_qup1,
1962 [SLAVE_QUP_2] = &qhs_qup2,
1963 [SLAVE_QUP_3] = &qhs_qup3,
1964 [SLAVE_QUP_4] = &qhs_qup4,
1965 [SLAVE_QUP_5] = &qhs_qup5,
1966 [SLAVE_SDCC_2] = &qhs_sdc2,
1967 [SLAVE_SDCC_4] = &qhs_sdc4,
1968 [SLAVE_TLMM] = &qhs_tlmm,
1969 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1970 [SLAVE_USB3] = &qhs_usb3,
1971 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1972 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1973 [SLAVE_QDSS_CFG] = &qss_qdss_cfg,
1974 [SLAVE_QDSS_STM] = &qss_qdss_stm,
1975 [SLAVE_TCSR] = &qss_tcsr,
1976 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1977};
1978
1979static const struct regmap_config maili_stdst_cfg_regmap_config = {
1980 .reg_bits = 32,
1981 .reg_stride = 4,
1982 .val_bits = 32,
1983 .max_register = 0x9000,
1984 .fast_io = true,
1985};
1986
1987static const struct qcom_icc_desc maili_stdst_cfg = {
1988 .config = &maili_stdst_cfg_regmap_config,
1989 .nodes = stdst_cfg_nodes,
1990 .num_nodes = ARRAY_SIZE(stdst_cfg_nodes),
1991 .bcms = stdst_cfg_bcms,
1992 .num_bcms = ARRAY_SIZE(stdst_cfg_bcms),
1993};
1994
1995static struct qcom_icc_node * const stdst_main_nodes[] = {
1996 [MASTER_CNOC_STARDUST] = &qsm_cnoc_main,
1997 [SLAVE_STARDUST_CENTER_CFG] = &qss_stdst_center_cfg,
1998 [SLAVE_STARDUST_EAST_CFG] = &qss_stdst_east_cfg,
1999 [SLAVE_STARDUST_MM_HF_CFG] = &qss_stdst_mm_hf_cfg,
2000 [SLAVE_STARDUST_MM_SF_CFG] = &qss_stdst_mm_sf_cfg,
2001 [SLAVE_STARDUST_NORTH_CFG] = &qss_stdst_north_cfg,
2002 [SLAVE_STARDUST_SOUTH_CFG] = &qss_stdst_south_cfg,
2003 [SLAVE_STARDUST_WEST_CFG] = &qss_stdst_west_cfg,
2004};
2005
2006static const struct regmap_config maili_stdst_main_regmap_config = {
2007 .reg_bits = 32,
2008 .reg_stride = 4,
2009 .val_bits = 32,
2010 .max_register = 0xf9000,
2011 .fast_io = true,
2012};
2013
2014static const struct qcom_icc_desc maili_stdst_main = {
2015 .config = &maili_stdst_main_regmap_config,
2016 .nodes = stdst_main_nodes,
2017 .num_nodes = ARRAY_SIZE(stdst_main_nodes),
2018};
2019
2020static struct qcom_icc_bcm * const system_noc_bcms[] = {
2021 &bcm_sn0,
2022 &bcm_sn2,
2023};
2024
2025static struct qcom_icc_node * const system_noc_nodes[] = {
2026 [MASTER_A1NOC_SNOC] = &qnm_aggre_noc,
2027 [MASTER_APSS_NOC] = &qnm_apss_noc,
2028 [MASTER_CNOC_SNOC] = &qnm_cnoc_data,
2029 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2030};
2031
2032static const struct regmap_config maili_system_noc_regmap_config = {
2033 .reg_bits = 32,
2034 .reg_stride = 4,
2035 .val_bits = 32,
2036 .max_register = 0x20080,
2037 .fast_io = true,
2038};
2039
2040static const struct qcom_icc_desc maili_system_noc = {
2041 .config = &maili_system_noc_regmap_config,
2042 .nodes = system_noc_nodes,
2043 .num_nodes = ARRAY_SIZE(system_noc_nodes),
2044 .bcms = system_noc_bcms,
2045 .num_bcms = ARRAY_SIZE(system_noc_bcms),
2046};
2047
2048static const struct of_device_id qnoc_of_match[] = {
2049 { .compatible = "qcom,maili-aggre-noc", .data = &maili_aggre1_noc },
2050 { .compatible = "qcom,maili-clk-virt", .data = &maili_clk_virt },
2051 { .compatible = "qcom,maili-cnoc-main", .data = &maili_cnoc_main },
2052 { .compatible = "qcom,maili-gem-noc", .data = &maili_gem_noc },
2053 { .compatible = "qcom,maili-llclpi-noc", .data = &maili_llclpi_noc },
2054 { .compatible = "qcom,maili-lpass-ag-noc", .data = &maili_lpass_ag_noc },
2055 { .compatible = "qcom,maili-lpass-lpiaon-noc", .data = &maili_lpass_lpiaon_noc },
2056 { .compatible = "qcom,maili-lpass-lpicx-noc", .data = &maili_lpass_lpicx_noc },
2057 { .compatible = "qcom,maili-mc-virt", .data = &maili_mc_virt },
2058 { .compatible = "qcom,maili-mmss-noc", .data = &maili_mmss_noc },
2059 { .compatible = "qcom,maili-nsp-noc", .data = &maili_nsp_noc },
2060 { .compatible = "qcom,maili-pcie-anoc", .data = &maili_pcie_anoc },
2061 { .compatible = "qcom,maili-stdst-cfg", .data = &maili_stdst_cfg },
2062 { .compatible = "qcom,maili-stdst-main", .data = &maili_stdst_main },
2063 { .compatible = "qcom,maili-system-noc", .data = &maili_system_noc },
2064 { }
2065};
2066MODULE_DEVICE_TABLE(of, qnoc_of_match);
2067
2068static struct platform_driver qnoc_driver = {
2069 .probe = qcom_icc_rpmh_probe,
2070 .remove = qcom_icc_rpmh_remove,
2071 .driver = {
2072 .name = "qnoc-maili",
2073 .of_match_table = qnoc_of_match,
2074 .sync_state = icc_sync_state,
2075 },
2076};
2077
2078static int __init qnoc_driver_init(void)
2079{
2080 return platform_driver_register(&qnoc_driver);
2081}
2082core_initcall(qnoc_driver_init);
2083
2084static void __exit qnoc_driver_exit(void)
2085{
2086 platform_driver_unregister(&qnoc_driver);
2087}
2088module_exit(qnoc_driver_exit);
2089
2090MODULE_DESCRIPTION("Qualcomm Maili NoC driver");
2091MODULE_LICENSE("GPL");