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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Linaro Ltd
4 */
5
6#include <dt-bindings/interconnect/qcom,qcs404.h>
7#include <linux/device.h>
8#include <linux/interconnect-provider.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/regmap.h>
13
14
15#include "icc-rpm.h"
16
17enum {
18 QCS404_MASTER_AMPSS_M0 = 1,
19 QCS404_MASTER_GRAPHICS_3D,
20 QCS404_MASTER_MDP_PORT0,
21 QCS404_SNOC_BIMC_1_MAS,
22 QCS404_MASTER_TCU_0,
23 QCS404_MASTER_SPDM,
24 QCS404_MASTER_BLSP_1,
25 QCS404_MASTER_BLSP_2,
26 QCS404_MASTER_XM_USB_HS1,
27 QCS404_MASTER_CRYPTO_CORE0,
28 QCS404_MASTER_SDCC_1,
29 QCS404_MASTER_SDCC_2,
30 QCS404_SNOC_PNOC_MAS,
31 QCS404_MASTER_QPIC,
32 QCS404_MASTER_QDSS_BAM,
33 QCS404_BIMC_SNOC_MAS,
34 QCS404_PNOC_SNOC_MAS,
35 QCS404_MASTER_QDSS_ETR,
36 QCS404_MASTER_EMAC,
37 QCS404_MASTER_PCIE,
38 QCS404_MASTER_USB3,
39 QCS404_PNOC_INT_0,
40 QCS404_PNOC_INT_2,
41 QCS404_PNOC_INT_3,
42 QCS404_PNOC_SLV_0,
43 QCS404_PNOC_SLV_1,
44 QCS404_PNOC_SLV_2,
45 QCS404_PNOC_SLV_3,
46 QCS404_PNOC_SLV_4,
47 QCS404_PNOC_SLV_6,
48 QCS404_PNOC_SLV_7,
49 QCS404_PNOC_SLV_8,
50 QCS404_PNOC_SLV_9,
51 QCS404_PNOC_SLV_10,
52 QCS404_PNOC_SLV_11,
53 QCS404_SNOC_QDSS_INT,
54 QCS404_SNOC_INT_0,
55 QCS404_SNOC_INT_1,
56 QCS404_SNOC_INT_2,
57 QCS404_SLAVE_EBI_CH0,
58 QCS404_BIMC_SNOC_SLV,
59 QCS404_SLAVE_SPDM_WRAPPER,
60 QCS404_SLAVE_PDM,
61 QCS404_SLAVE_PRNG,
62 QCS404_SLAVE_TCSR,
63 QCS404_SLAVE_SNOC_CFG,
64 QCS404_SLAVE_MESSAGE_RAM,
65 QCS404_SLAVE_DISPLAY_CFG,
66 QCS404_SLAVE_GRAPHICS_3D_CFG,
67 QCS404_SLAVE_BLSP_1,
68 QCS404_SLAVE_TLMM_NORTH,
69 QCS404_SLAVE_PCIE_1,
70 QCS404_SLAVE_EMAC_CFG,
71 QCS404_SLAVE_BLSP_2,
72 QCS404_SLAVE_TLMM_EAST,
73 QCS404_SLAVE_TCU,
74 QCS404_SLAVE_PMIC_ARB,
75 QCS404_SLAVE_SDCC_1,
76 QCS404_SLAVE_SDCC_2,
77 QCS404_SLAVE_TLMM_SOUTH,
78 QCS404_SLAVE_USB_HS,
79 QCS404_SLAVE_USB3,
80 QCS404_SLAVE_CRYPTO_0_CFG,
81 QCS404_PNOC_SNOC_SLV,
82 QCS404_SLAVE_APPSS,
83 QCS404_SLAVE_WCSS,
84 QCS404_SNOC_BIMC_1_SLV,
85 QCS404_SLAVE_OCIMEM,
86 QCS404_SNOC_PNOC_SLV,
87 QCS404_SLAVE_QDSS_STM,
88 QCS404_SLAVE_CATS_128,
89 QCS404_SLAVE_OCMEM_64,
90 QCS404_SLAVE_LPASS,
91};
92
93static const u16 mas_apps_proc_links[] = {
94 QCS404_SLAVE_EBI_CH0,
95 QCS404_BIMC_SNOC_SLV
96};
97
98static struct qcom_icc_node mas_apps_proc = {
99 .name = "mas_apps_proc",
100 .id = QCS404_MASTER_AMPSS_M0,
101 .buswidth = 8,
102 .mas_rpm_id = 0,
103 .slv_rpm_id = -1,
104 .qos.ap_owned = true,
105 .qos.qos_mode = NOC_QOS_MODE_FIXED,
106 .qos.areq_prio = 0,
107 .qos.prio_level = 0,
108 .qos.qos_port = 0,
109 .num_links = ARRAY_SIZE(mas_apps_proc_links),
110 .links = mas_apps_proc_links,
111};
112
113static const u16 mas_oxili_links[] = {
114 QCS404_SLAVE_EBI_CH0,
115 QCS404_BIMC_SNOC_SLV
116};
117
118static struct qcom_icc_node mas_oxili = {
119 .name = "mas_oxili",
120 .id = QCS404_MASTER_GRAPHICS_3D,
121 .buswidth = 8,
122 .mas_rpm_id = -1,
123 .slv_rpm_id = -1,
124 .qos.ap_owned = true,
125 .qos.qos_mode = NOC_QOS_MODE_FIXED,
126 .qos.areq_prio = 0,
127 .qos.prio_level = 0,
128 .qos.qos_port = 2,
129 .num_links = ARRAY_SIZE(mas_oxili_links),
130 .links = mas_oxili_links,
131};
132
133static const u16 mas_mdp_links[] = {
134 QCS404_SLAVE_EBI_CH0,
135 QCS404_BIMC_SNOC_SLV
136};
137
138static struct qcom_icc_node mas_mdp = {
139 .name = "mas_mdp",
140 .id = QCS404_MASTER_MDP_PORT0,
141 .buswidth = 8,
142 .mas_rpm_id = -1,
143 .slv_rpm_id = -1,
144 .qos.ap_owned = true,
145 .qos.qos_mode = NOC_QOS_MODE_FIXED,
146 .qos.areq_prio = 0,
147 .qos.prio_level = 1,
148 .qos.qos_port = 4,
149 .num_links = ARRAY_SIZE(mas_mdp_links),
150 .links = mas_mdp_links,
151};
152
153static const u16 mas_snoc_bimc_1_links[] = {
154 QCS404_SLAVE_EBI_CH0
155};
156
157static struct qcom_icc_node mas_snoc_bimc_1 = {
158 .name = "mas_snoc_bimc_1",
159 .id = QCS404_SNOC_BIMC_1_MAS,
160 .buswidth = 8,
161 .mas_rpm_id = 76,
162 .slv_rpm_id = -1,
163 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
164 .qos.areq_prio = 0,
165 .qos.prio_level = 0,
166 .qos.qos_port = 5,
167 .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
168 .links = mas_snoc_bimc_1_links,
169};
170
171static const u16 mas_tcu_0_links[] = {
172 QCS404_SLAVE_EBI_CH0,
173 QCS404_BIMC_SNOC_SLV
174};
175
176static struct qcom_icc_node mas_tcu_0 = {
177 .name = "mas_tcu_0",
178 .id = QCS404_MASTER_TCU_0,
179 .buswidth = 8,
180 .mas_rpm_id = -1,
181 .slv_rpm_id = -1,
182 .qos.ap_owned = true,
183 .qos.qos_mode = NOC_QOS_MODE_FIXED,
184 .qos.areq_prio = 0,
185 .qos.prio_level = 2,
186 .qos.qos_port = 6,
187 .num_links = ARRAY_SIZE(mas_tcu_0_links),
188 .links = mas_tcu_0_links,
189};
190
191static const u16 mas_spdm_links[] = {
192 QCS404_PNOC_INT_3
193};
194
195static struct qcom_icc_node mas_spdm = {
196 .name = "mas_spdm",
197 .id = QCS404_MASTER_SPDM,
198 .buswidth = 4,
199 .mas_rpm_id = -1,
200 .slv_rpm_id = -1,
201 .qos.ap_owned = true,
202 .qos.qos_mode = NOC_QOS_MODE_INVALID,
203 .num_links = ARRAY_SIZE(mas_spdm_links),
204 .links = mas_spdm_links,
205};
206
207static const u16 mas_blsp_1_links[] = {
208 QCS404_PNOC_INT_3
209};
210
211static struct qcom_icc_node mas_blsp_1 = {
212 .name = "mas_blsp_1",
213 .id = QCS404_MASTER_BLSP_1,
214 .buswidth = 4,
215 .mas_rpm_id = 41,
216 .slv_rpm_id = -1,
217 .num_links = ARRAY_SIZE(mas_blsp_1_links),
218 .links = mas_blsp_1_links,
219};
220
221static const u16 mas_blsp_2_links[] = {
222 QCS404_PNOC_INT_3
223};
224
225static struct qcom_icc_node mas_blsp_2 = {
226 .name = "mas_blsp_2",
227 .id = QCS404_MASTER_BLSP_2,
228 .buswidth = 4,
229 .mas_rpm_id = 39,
230 .slv_rpm_id = -1,
231 .num_links = ARRAY_SIZE(mas_blsp_2_links),
232 .links = mas_blsp_2_links,
233};
234
235static const u16 mas_xi_usb_hs1_links[] = {
236 QCS404_PNOC_INT_0
237};
238
239static struct qcom_icc_node mas_xi_usb_hs1 = {
240 .name = "mas_xi_usb_hs1",
241 .id = QCS404_MASTER_XM_USB_HS1,
242 .buswidth = 8,
243 .mas_rpm_id = 138,
244 .slv_rpm_id = -1,
245 .num_links = ARRAY_SIZE(mas_xi_usb_hs1_links),
246 .links = mas_xi_usb_hs1_links,
247};
248
249static const u16 mas_crypto_links[] = {
250 QCS404_PNOC_SNOC_SLV,
251 QCS404_PNOC_INT_2
252};
253
254static struct qcom_icc_node mas_crypto = {
255 .name = "mas_crypto",
256 .id = QCS404_MASTER_CRYPTO_CORE0,
257 .buswidth = 8,
258 .mas_rpm_id = 23,
259 .slv_rpm_id = -1,
260 .qos.ap_owned = true,
261 .qos.qos_mode = NOC_QOS_MODE_FIXED,
262 .qos.areq_prio = 1,
263 .qos.prio_level = 1,
264 .qos.qos_port = 0,
265 .num_links = ARRAY_SIZE(mas_crypto_links),
266 .links = mas_crypto_links,
267};
268
269static const u16 mas_sdcc_1_links[] = {
270 QCS404_PNOC_INT_0
271};
272
273static struct qcom_icc_node mas_sdcc_1 = {
274 .name = "mas_sdcc_1",
275 .id = QCS404_MASTER_SDCC_1,
276 .buswidth = 8,
277 .mas_rpm_id = 33,
278 .slv_rpm_id = -1,
279 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
280 .links = mas_sdcc_1_links,
281};
282
283static const u16 mas_sdcc_2_links[] = {
284 QCS404_PNOC_INT_0
285};
286
287static struct qcom_icc_node mas_sdcc_2 = {
288 .name = "mas_sdcc_2",
289 .id = QCS404_MASTER_SDCC_2,
290 .buswidth = 8,
291 .mas_rpm_id = 35,
292 .slv_rpm_id = -1,
293 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
294 .links = mas_sdcc_2_links,
295};
296
297static const u16 mas_snoc_pcnoc_links[] = {
298 QCS404_PNOC_INT_2
299};
300
301static struct qcom_icc_node mas_snoc_pcnoc = {
302 .name = "mas_snoc_pcnoc",
303 .id = QCS404_SNOC_PNOC_MAS,
304 .buswidth = 8,
305 .mas_rpm_id = 77,
306 .slv_rpm_id = -1,
307 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links),
308 .links = mas_snoc_pcnoc_links,
309};
310
311static const u16 mas_qpic_links[] = {
312 QCS404_PNOC_INT_0
313};
314
315static struct qcom_icc_node mas_qpic = {
316 .name = "mas_qpic",
317 .id = QCS404_MASTER_QPIC,
318 .buswidth = 4,
319 .mas_rpm_id = -1,
320 .slv_rpm_id = -1,
321 .qos.ap_owned = true,
322 .qos.qos_mode = NOC_QOS_MODE_FIXED,
323 .qos.areq_prio = 1,
324 .qos.prio_level = 1,
325 .qos.qos_port = 14,
326 .num_links = ARRAY_SIZE(mas_qpic_links),
327 .links = mas_qpic_links,
328};
329
330static const u16 mas_qdss_bam_links[] = {
331 QCS404_SNOC_QDSS_INT
332};
333
334static struct qcom_icc_node mas_qdss_bam = {
335 .name = "mas_qdss_bam",
336 .id = QCS404_MASTER_QDSS_BAM,
337 .buswidth = 4,
338 .mas_rpm_id = -1,
339 .slv_rpm_id = -1,
340 .qos.ap_owned = true,
341 .qos.qos_mode = NOC_QOS_MODE_FIXED,
342 .qos.areq_prio = 1,
343 .qos.prio_level = 1,
344 .qos.qos_port = 1,
345 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
346 .links = mas_qdss_bam_links,
347};
348
349static const u16 mas_bimc_snoc_links[] = {
350 QCS404_SLAVE_OCMEM_64,
351 QCS404_SLAVE_CATS_128,
352 QCS404_SNOC_INT_0,
353 QCS404_SNOC_INT_1
354};
355
356static struct qcom_icc_node mas_bimc_snoc = {
357 .name = "mas_bimc_snoc",
358 .id = QCS404_BIMC_SNOC_MAS,
359 .buswidth = 8,
360 .mas_rpm_id = 21,
361 .slv_rpm_id = -1,
362 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
363 .links = mas_bimc_snoc_links,
364};
365
366static const u16 mas_pcnoc_snoc_links[] = {
367 QCS404_SNOC_BIMC_1_SLV,
368 QCS404_SNOC_INT_2,
369 QCS404_SNOC_INT_0
370};
371
372static struct qcom_icc_node mas_pcnoc_snoc = {
373 .name = "mas_pcnoc_snoc",
374 .id = QCS404_PNOC_SNOC_MAS,
375 .buswidth = 8,
376 .mas_rpm_id = 29,
377 .slv_rpm_id = -1,
378 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links),
379 .links = mas_pcnoc_snoc_links,
380};
381
382static const u16 mas_qdss_etr_links[] = {
383 QCS404_SNOC_QDSS_INT
384};
385
386static struct qcom_icc_node mas_qdss_etr = {
387 .name = "mas_qdss_etr",
388 .id = QCS404_MASTER_QDSS_ETR,
389 .buswidth = 8,
390 .mas_rpm_id = -1,
391 .slv_rpm_id = -1,
392 .qos.ap_owned = true,
393 .qos.qos_mode = NOC_QOS_MODE_FIXED,
394 .qos.areq_prio = 1,
395 .qos.prio_level = 1,
396 .qos.qos_port = 0,
397 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
398 .links = mas_qdss_etr_links,
399};
400
401static const u16 mas_emac_links[] = {
402 QCS404_SNOC_BIMC_1_SLV,
403 QCS404_SNOC_INT_1
404};
405
406static struct qcom_icc_node mas_emac = {
407 .name = "mas_emac",
408 .id = QCS404_MASTER_EMAC,
409 .buswidth = 8,
410 .mas_rpm_id = -1,
411 .slv_rpm_id = -1,
412 .qos.ap_owned = true,
413 .qos.qos_mode = NOC_QOS_MODE_FIXED,
414 .qos.areq_prio = 1,
415 .qos.prio_level = 1,
416 .qos.qos_port = 17,
417 .num_links = ARRAY_SIZE(mas_emac_links),
418 .links = mas_emac_links,
419};
420
421static const u16 mas_pcie_links[] = {
422 QCS404_SNOC_BIMC_1_SLV,
423 QCS404_SNOC_INT_1
424};
425
426static struct qcom_icc_node mas_pcie = {
427 .name = "mas_pcie",
428 .id = QCS404_MASTER_PCIE,
429 .buswidth = 8,
430 .mas_rpm_id = -1,
431 .slv_rpm_id = -1,
432 .qos.ap_owned = true,
433 .qos.qos_mode = NOC_QOS_MODE_FIXED,
434 .qos.areq_prio = 1,
435 .qos.prio_level = 1,
436 .qos.qos_port = 8,
437 .num_links = ARRAY_SIZE(mas_pcie_links),
438 .links = mas_pcie_links,
439};
440
441static const u16 mas_usb3_links[] = {
442 QCS404_SNOC_BIMC_1_SLV,
443 QCS404_SNOC_INT_1
444};
445
446static struct qcom_icc_node mas_usb3 = {
447 .name = "mas_usb3",
448 .id = QCS404_MASTER_USB3,
449 .buswidth = 8,
450 .mas_rpm_id = -1,
451 .slv_rpm_id = -1,
452 .qos.ap_owned = true,
453 .qos.qos_mode = NOC_QOS_MODE_FIXED,
454 .qos.areq_prio = 1,
455 .qos.prio_level = 1,
456 .qos.qos_port = 16,
457 .num_links = ARRAY_SIZE(mas_usb3_links),
458 .links = mas_usb3_links,
459};
460
461static const u16 pcnoc_int_0_links[] = {
462 QCS404_PNOC_SNOC_SLV,
463 QCS404_PNOC_INT_2
464};
465
466static struct qcom_icc_node pcnoc_int_0 = {
467 .name = "pcnoc_int_0",
468 .id = QCS404_PNOC_INT_0,
469 .buswidth = 8,
470 .mas_rpm_id = 85,
471 .slv_rpm_id = 114,
472 .num_links = ARRAY_SIZE(pcnoc_int_0_links),
473 .links = pcnoc_int_0_links,
474};
475
476static const u16 pcnoc_int_2_links[] = {
477 QCS404_PNOC_SLV_10,
478 QCS404_SLAVE_TCU,
479 QCS404_PNOC_SLV_11,
480 QCS404_PNOC_SLV_2,
481 QCS404_PNOC_SLV_3,
482 QCS404_PNOC_SLV_0,
483 QCS404_PNOC_SLV_1,
484 QCS404_PNOC_SLV_6,
485 QCS404_PNOC_SLV_7,
486 QCS404_PNOC_SLV_4,
487 QCS404_PNOC_SLV_8,
488 QCS404_PNOC_SLV_9
489};
490
491static struct qcom_icc_node pcnoc_int_2 = {
492 .name = "pcnoc_int_2",
493 .id = QCS404_PNOC_INT_2,
494 .buswidth = 8,
495 .mas_rpm_id = 124,
496 .slv_rpm_id = 184,
497 .num_links = ARRAY_SIZE(pcnoc_int_2_links),
498 .links = pcnoc_int_2_links,
499};
500
501static const u16 pcnoc_int_3_links[] = {
502 QCS404_PNOC_SNOC_SLV
503};
504
505static struct qcom_icc_node pcnoc_int_3 = {
506 .name = "pcnoc_int_3",
507 .id = QCS404_PNOC_INT_3,
508 .buswidth = 8,
509 .mas_rpm_id = 125,
510 .slv_rpm_id = 185,
511 .num_links = ARRAY_SIZE(pcnoc_int_3_links),
512 .links = pcnoc_int_3_links,
513};
514
515static const u16 pcnoc_s_0_links[] = {
516 QCS404_SLAVE_PRNG,
517 QCS404_SLAVE_SPDM_WRAPPER,
518 QCS404_SLAVE_PDM
519};
520
521static struct qcom_icc_node pcnoc_s_0 = {
522 .name = "pcnoc_s_0",
523 .id = QCS404_PNOC_SLV_0,
524 .buswidth = 4,
525 .mas_rpm_id = 89,
526 .slv_rpm_id = 118,
527 .num_links = ARRAY_SIZE(pcnoc_s_0_links),
528 .links = pcnoc_s_0_links,
529};
530
531static const u16 pcnoc_s_1_links[] = {
532 QCS404_SLAVE_TCSR
533};
534
535static struct qcom_icc_node pcnoc_s_1 = {
536 .name = "pcnoc_s_1",
537 .id = QCS404_PNOC_SLV_1,
538 .buswidth = 4,
539 .mas_rpm_id = 90,
540 .slv_rpm_id = 119,
541 .num_links = ARRAY_SIZE(pcnoc_s_1_links),
542 .links = pcnoc_s_1_links,
543};
544
545static const u16 pcnoc_s_2_links[] = {
546 QCS404_SLAVE_GRAPHICS_3D_CFG
547};
548
549static struct qcom_icc_node pcnoc_s_2 = {
550 .name = "pcnoc_s_2",
551 .id = QCS404_PNOC_SLV_2,
552 .buswidth = 4,
553 .mas_rpm_id = -1,
554 .slv_rpm_id = -1,
555 .qos.ap_owned = true,
556 .qos.qos_mode = NOC_QOS_MODE_INVALID,
557 .num_links = ARRAY_SIZE(pcnoc_s_2_links),
558 .links = pcnoc_s_2_links,
559};
560
561static const u16 pcnoc_s_3_links[] = {
562 QCS404_SLAVE_MESSAGE_RAM
563};
564
565static struct qcom_icc_node pcnoc_s_3 = {
566 .name = "pcnoc_s_3",
567 .id = QCS404_PNOC_SLV_3,
568 .buswidth = 4,
569 .mas_rpm_id = 92,
570 .slv_rpm_id = 121,
571 .num_links = ARRAY_SIZE(pcnoc_s_3_links),
572 .links = pcnoc_s_3_links,
573};
574
575static const u16 pcnoc_s_4_links[] = {
576 QCS404_SLAVE_SNOC_CFG
577};
578
579static struct qcom_icc_node pcnoc_s_4 = {
580 .name = "pcnoc_s_4",
581 .id = QCS404_PNOC_SLV_4,
582 .buswidth = 4,
583 .mas_rpm_id = 93,
584 .slv_rpm_id = 122,
585 .num_links = ARRAY_SIZE(pcnoc_s_4_links),
586 .links = pcnoc_s_4_links,
587};
588
589static const u16 pcnoc_s_6_links[] = {
590 QCS404_SLAVE_BLSP_1,
591 QCS404_SLAVE_TLMM_NORTH,
592 QCS404_SLAVE_EMAC_CFG
593};
594
595static struct qcom_icc_node pcnoc_s_6 = {
596 .name = "pcnoc_s_6",
597 .id = QCS404_PNOC_SLV_6,
598 .buswidth = 4,
599 .mas_rpm_id = 94,
600 .slv_rpm_id = 123,
601 .num_links = ARRAY_SIZE(pcnoc_s_6_links),
602 .links = pcnoc_s_6_links,
603};
604
605static const u16 pcnoc_s_7_links[] = {
606 QCS404_SLAVE_TLMM_SOUTH,
607 QCS404_SLAVE_DISPLAY_CFG,
608 QCS404_SLAVE_SDCC_1,
609 QCS404_SLAVE_PCIE_1,
610 QCS404_SLAVE_SDCC_2
611};
612
613static struct qcom_icc_node pcnoc_s_7 = {
614 .name = "pcnoc_s_7",
615 .id = QCS404_PNOC_SLV_7,
616 .buswidth = 4,
617 .mas_rpm_id = 95,
618 .slv_rpm_id = 124,
619 .num_links = ARRAY_SIZE(pcnoc_s_7_links),
620 .links = pcnoc_s_7_links,
621};
622
623static const u16 pcnoc_s_8_links[] = {
624 QCS404_SLAVE_CRYPTO_0_CFG
625};
626
627static struct qcom_icc_node pcnoc_s_8 = {
628 .name = "pcnoc_s_8",
629 .id = QCS404_PNOC_SLV_8,
630 .buswidth = 4,
631 .mas_rpm_id = 96,
632 .slv_rpm_id = 125,
633 .num_links = ARRAY_SIZE(pcnoc_s_8_links),
634 .links = pcnoc_s_8_links,
635};
636
637static const u16 pcnoc_s_9_links[] = {
638 QCS404_SLAVE_BLSP_2,
639 QCS404_SLAVE_TLMM_EAST,
640 QCS404_SLAVE_PMIC_ARB
641};
642
643static struct qcom_icc_node pcnoc_s_9 = {
644 .name = "pcnoc_s_9",
645 .id = QCS404_PNOC_SLV_9,
646 .buswidth = 4,
647 .mas_rpm_id = 97,
648 .slv_rpm_id = 126,
649 .num_links = ARRAY_SIZE(pcnoc_s_9_links),
650 .links = pcnoc_s_9_links,
651};
652
653static const u16 pcnoc_s_10_links[] = {
654 QCS404_SLAVE_USB_HS
655};
656
657static struct qcom_icc_node pcnoc_s_10 = {
658 .name = "pcnoc_s_10",
659 .id = QCS404_PNOC_SLV_10,
660 .buswidth = 4,
661 .mas_rpm_id = 157,
662 .slv_rpm_id = -1,
663 .num_links = ARRAY_SIZE(pcnoc_s_10_links),
664 .links = pcnoc_s_10_links,
665};
666
667static const u16 pcnoc_s_11_links[] = {
668 QCS404_SLAVE_USB3
669};
670
671static struct qcom_icc_node pcnoc_s_11 = {
672 .name = "pcnoc_s_11",
673 .id = QCS404_PNOC_SLV_11,
674 .buswidth = 4,
675 .mas_rpm_id = 158,
676 .slv_rpm_id = 246,
677 .num_links = ARRAY_SIZE(pcnoc_s_11_links),
678 .links = pcnoc_s_11_links,
679};
680
681static const u16 qdss_int_links[] = {
682 QCS404_SNOC_BIMC_1_SLV,
683 QCS404_SNOC_INT_1
684};
685
686static struct qcom_icc_node qdss_int = {
687 .name = "qdss_int",
688 .id = QCS404_SNOC_QDSS_INT,
689 .buswidth = 8,
690 .mas_rpm_id = -1,
691 .slv_rpm_id = -1,
692 .qos.ap_owned = true,
693 .qos.qos_mode = NOC_QOS_MODE_INVALID,
694 .num_links = ARRAY_SIZE(qdss_int_links),
695 .links = qdss_int_links,
696};
697
698static const u16 snoc_int_0_links[] = {
699 QCS404_SLAVE_LPASS,
700 QCS404_SLAVE_APPSS,
701 QCS404_SLAVE_WCSS
702};
703
704static struct qcom_icc_node snoc_int_0 = {
705 .name = "snoc_int_0",
706 .id = QCS404_SNOC_INT_0,
707 .buswidth = 8,
708 .mas_rpm_id = 99,
709 .slv_rpm_id = 130,
710 .num_links = ARRAY_SIZE(snoc_int_0_links),
711 .links = snoc_int_0_links,
712};
713
714static const u16 snoc_int_1_links[] = {
715 QCS404_SNOC_PNOC_SLV,
716 QCS404_SNOC_INT_2
717};
718
719static struct qcom_icc_node snoc_int_1 = {
720 .name = "snoc_int_1",
721 .id = QCS404_SNOC_INT_1,
722 .buswidth = 8,
723 .mas_rpm_id = 100,
724 .slv_rpm_id = 131,
725 .num_links = ARRAY_SIZE(snoc_int_1_links),
726 .links = snoc_int_1_links,
727};
728
729static const u16 snoc_int_2_links[] = {
730 QCS404_SLAVE_QDSS_STM,
731 QCS404_SLAVE_OCIMEM
732};
733
734static struct qcom_icc_node snoc_int_2 = {
735 .name = "snoc_int_2",
736 .id = QCS404_SNOC_INT_2,
737 .buswidth = 8,
738 .mas_rpm_id = 134,
739 .slv_rpm_id = 197,
740 .num_links = ARRAY_SIZE(snoc_int_2_links),
741 .links = snoc_int_2_links,
742};
743
744static struct qcom_icc_node slv_ebi = {
745 .name = "slv_ebi",
746 .id = QCS404_SLAVE_EBI_CH0,
747 .buswidth = 8,
748 .mas_rpm_id = -1,
749 .slv_rpm_id = 0,
750};
751
752static const u16 slv_bimc_snoc_links[] = {
753 QCS404_BIMC_SNOC_MAS
754};
755
756static struct qcom_icc_node slv_bimc_snoc = {
757 .name = "slv_bimc_snoc",
758 .id = QCS404_BIMC_SNOC_SLV,
759 .buswidth = 8,
760 .mas_rpm_id = -1,
761 .slv_rpm_id = 2,
762 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
763 .links = slv_bimc_snoc_links,
764};
765
766static struct qcom_icc_node slv_spdm = {
767 .name = "slv_spdm",
768 .id = QCS404_SLAVE_SPDM_WRAPPER,
769 .buswidth = 4,
770 .mas_rpm_id = -1,
771 .slv_rpm_id = -1,
772 .qos.ap_owned = true,
773 .qos.qos_mode = NOC_QOS_MODE_INVALID,
774};
775
776static struct qcom_icc_node slv_pdm = {
777 .name = "slv_pdm",
778 .id = QCS404_SLAVE_PDM,
779 .buswidth = 4,
780 .mas_rpm_id = -1,
781 .slv_rpm_id = 41,
782};
783
784static struct qcom_icc_node slv_prng = {
785 .name = "slv_prng",
786 .id = QCS404_SLAVE_PRNG,
787 .buswidth = 4,
788 .mas_rpm_id = -1,
789 .slv_rpm_id = 44,
790};
791
792static struct qcom_icc_node slv_tcsr = {
793 .name = "slv_tcsr",
794 .id = QCS404_SLAVE_TCSR,
795 .buswidth = 4,
796 .mas_rpm_id = -1,
797 .slv_rpm_id = 50,
798};
799
800static struct qcom_icc_node slv_snoc_cfg = {
801 .name = "slv_snoc_cfg",
802 .id = QCS404_SLAVE_SNOC_CFG,
803 .buswidth = 4,
804 .mas_rpm_id = -1,
805 .slv_rpm_id = 70,
806};
807
808static struct qcom_icc_node slv_message_ram = {
809 .name = "slv_message_ram",
810 .id = QCS404_SLAVE_MESSAGE_RAM,
811 .buswidth = 4,
812 .mas_rpm_id = -1,
813 .slv_rpm_id = 55,
814};
815
816static struct qcom_icc_node slv_disp_ss_cfg = {
817 .name = "slv_disp_ss_cfg",
818 .id = QCS404_SLAVE_DISPLAY_CFG,
819 .buswidth = 4,
820 .mas_rpm_id = -1,
821 .slv_rpm_id = -1,
822 .qos.ap_owned = true,
823 .qos.qos_mode = NOC_QOS_MODE_INVALID,
824};
825
826static struct qcom_icc_node slv_gpu_cfg = {
827 .name = "slv_gpu_cfg",
828 .id = QCS404_SLAVE_GRAPHICS_3D_CFG,
829 .buswidth = 4,
830 .mas_rpm_id = -1,
831 .slv_rpm_id = -1,
832 .qos.ap_owned = true,
833 .qos.qos_mode = NOC_QOS_MODE_INVALID,
834};
835
836static struct qcom_icc_node slv_blsp_1 = {
837 .name = "slv_blsp_1",
838 .id = QCS404_SLAVE_BLSP_1,
839 .buswidth = 4,
840 .mas_rpm_id = -1,
841 .slv_rpm_id = 39,
842};
843
844static struct qcom_icc_node slv_tlmm_north = {
845 .name = "slv_tlmm_north",
846 .id = QCS404_SLAVE_TLMM_NORTH,
847 .buswidth = 4,
848 .mas_rpm_id = -1,
849 .slv_rpm_id = 214,
850};
851
852static struct qcom_icc_node slv_pcie = {
853 .name = "slv_pcie",
854 .id = QCS404_SLAVE_PCIE_1,
855 .buswidth = 4,
856 .mas_rpm_id = -1,
857 .slv_rpm_id = -1,
858 .qos.ap_owned = true,
859 .qos.qos_mode = NOC_QOS_MODE_INVALID,
860};
861
862static struct qcom_icc_node slv_ethernet = {
863 .name = "slv_ethernet",
864 .id = QCS404_SLAVE_EMAC_CFG,
865 .buswidth = 4,
866 .mas_rpm_id = -1,
867 .slv_rpm_id = -1,
868 .qos.ap_owned = true,
869 .qos.qos_mode = NOC_QOS_MODE_INVALID,
870};
871
872static struct qcom_icc_node slv_blsp_2 = {
873 .name = "slv_blsp_2",
874 .id = QCS404_SLAVE_BLSP_2,
875 .buswidth = 4,
876 .mas_rpm_id = -1,
877 .slv_rpm_id = 37,
878};
879
880static struct qcom_icc_node slv_tlmm_east = {
881 .name = "slv_tlmm_east",
882 .id = QCS404_SLAVE_TLMM_EAST,
883 .buswidth = 4,
884 .mas_rpm_id = -1,
885 .slv_rpm_id = 213,
886};
887
888static struct qcom_icc_node slv_tcu = {
889 .name = "slv_tcu",
890 .id = QCS404_SLAVE_TCU,
891 .buswidth = 8,
892 .mas_rpm_id = -1,
893 .slv_rpm_id = -1,
894 .qos.ap_owned = true,
895 .qos.qos_mode = NOC_QOS_MODE_INVALID,
896};
897
898static struct qcom_icc_node slv_pmic_arb = {
899 .name = "slv_pmic_arb",
900 .id = QCS404_SLAVE_PMIC_ARB,
901 .buswidth = 4,
902 .mas_rpm_id = -1,
903 .slv_rpm_id = 59,
904};
905
906static struct qcom_icc_node slv_sdcc_1 = {
907 .name = "slv_sdcc_1",
908 .id = QCS404_SLAVE_SDCC_1,
909 .buswidth = 4,
910 .mas_rpm_id = -1,
911 .slv_rpm_id = 31,
912};
913
914static struct qcom_icc_node slv_sdcc_2 = {
915 .name = "slv_sdcc_2",
916 .id = QCS404_SLAVE_SDCC_2,
917 .buswidth = 4,
918 .mas_rpm_id = -1,
919 .slv_rpm_id = 33,
920};
921
922static struct qcom_icc_node slv_tlmm_south = {
923 .name = "slv_tlmm_south",
924 .id = QCS404_SLAVE_TLMM_SOUTH,
925 .buswidth = 4,
926 .mas_rpm_id = -1,
927 .slv_rpm_id = -1,
928};
929
930static struct qcom_icc_node slv_usb_hs = {
931 .name = "slv_usb_hs",
932 .id = QCS404_SLAVE_USB_HS,
933 .buswidth = 4,
934 .mas_rpm_id = -1,
935 .slv_rpm_id = 40,
936};
937
938static struct qcom_icc_node slv_usb3 = {
939 .name = "slv_usb3",
940 .id = QCS404_SLAVE_USB3,
941 .buswidth = 4,
942 .mas_rpm_id = -1,
943 .slv_rpm_id = 22,
944};
945
946static struct qcom_icc_node slv_crypto_0_cfg = {
947 .name = "slv_crypto_0_cfg",
948 .id = QCS404_SLAVE_CRYPTO_0_CFG,
949 .buswidth = 4,
950 .mas_rpm_id = -1,
951 .slv_rpm_id = 52,
952};
953
954static const u16 slv_pcnoc_snoc_links[] = {
955 QCS404_PNOC_SNOC_MAS
956};
957
958static struct qcom_icc_node slv_pcnoc_snoc = {
959 .name = "slv_pcnoc_snoc",
960 .id = QCS404_PNOC_SNOC_SLV,
961 .buswidth = 8,
962 .mas_rpm_id = -1,
963 .slv_rpm_id = 45,
964 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links),
965 .links = slv_pcnoc_snoc_links,
966};
967
968static struct qcom_icc_node slv_kpss_ahb = {
969 .name = "slv_kpss_ahb",
970 .id = QCS404_SLAVE_APPSS,
971 .buswidth = 4,
972 .mas_rpm_id = -1,
973 .slv_rpm_id = -1,
974 .qos.ap_owned = true,
975 .qos.qos_mode = NOC_QOS_MODE_INVALID,
976};
977
978static struct qcom_icc_node slv_wcss = {
979 .name = "slv_wcss",
980 .id = QCS404_SLAVE_WCSS,
981 .buswidth = 4,
982 .mas_rpm_id = -1,
983 .slv_rpm_id = 23,
984};
985
986static const u16 slv_snoc_bimc_1_links[] = {
987 QCS404_SNOC_BIMC_1_MAS
988};
989
990static struct qcom_icc_node slv_snoc_bimc_1 = {
991 .name = "slv_snoc_bimc_1",
992 .id = QCS404_SNOC_BIMC_1_SLV,
993 .buswidth = 8,
994 .mas_rpm_id = -1,
995 .slv_rpm_id = 104,
996 .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links),
997 .links = slv_snoc_bimc_1_links,
998};
999
1000static struct qcom_icc_node slv_imem = {
1001 .name = "slv_imem",
1002 .id = QCS404_SLAVE_OCIMEM,
1003 .buswidth = 8,
1004 .mas_rpm_id = -1,
1005 .slv_rpm_id = 26,
1006};
1007
1008static const u16 slv_snoc_pcnoc_links[] = {
1009 QCS404_SNOC_PNOC_MAS
1010};
1011
1012static struct qcom_icc_node slv_snoc_pcnoc = {
1013 .name = "slv_snoc_pcnoc",
1014 .id = QCS404_SNOC_PNOC_SLV,
1015 .buswidth = 8,
1016 .mas_rpm_id = -1,
1017 .slv_rpm_id = 28,
1018 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links),
1019 .links = slv_snoc_pcnoc_links,
1020};
1021
1022static struct qcom_icc_node slv_qdss_stm = {
1023 .name = "slv_qdss_stm",
1024 .id = QCS404_SLAVE_QDSS_STM,
1025 .buswidth = 4,
1026 .mas_rpm_id = -1,
1027 .slv_rpm_id = 30,
1028};
1029
1030static struct qcom_icc_node slv_cats_0 = {
1031 .name = "slv_cats_0",
1032 .id = QCS404_SLAVE_CATS_128,
1033 .buswidth = 16,
1034 .mas_rpm_id = -1,
1035 .slv_rpm_id = -1,
1036 .qos.ap_owned = true,
1037 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1038};
1039
1040static struct qcom_icc_node slv_cats_1 = {
1041 .name = "slv_cats_1",
1042 .id = QCS404_SLAVE_OCMEM_64,
1043 .buswidth = 8,
1044 .mas_rpm_id = -1,
1045 .slv_rpm_id = -1,
1046 .qos.ap_owned = true,
1047 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1048};
1049
1050static struct qcom_icc_node slv_lpass = {
1051 .name = "slv_lpass",
1052 .id = QCS404_SLAVE_LPASS,
1053 .buswidth = 4,
1054 .mas_rpm_id = -1,
1055 .slv_rpm_id = -1,
1056 .qos.ap_owned = true,
1057 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1058};
1059
1060static struct qcom_icc_node * const qcs404_bimc_nodes[] = {
1061 [MASTER_AMPSS_M0] = &mas_apps_proc,
1062 [MASTER_OXILI] = &mas_oxili,
1063 [MASTER_MDP_PORT0] = &mas_mdp,
1064 [MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1,
1065 [MASTER_TCU_0] = &mas_tcu_0,
1066 [SLAVE_EBI_CH0] = &slv_ebi,
1067 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
1068};
1069
1070static const struct regmap_config qcs404_bimc_regmap_config = {
1071 .reg_bits = 32,
1072 .reg_stride = 4,
1073 .val_bits = 32,
1074 .max_register = 0x80000,
1075 .fast_io = true,
1076};
1077
1078static const struct qcom_icc_desc qcs404_bimc = {
1079 .type = QCOM_ICC_BIMC,
1080 .nodes = qcs404_bimc_nodes,
1081 .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
1082 .bus_clk_desc = &bimc_clk,
1083 .regmap_cfg = &qcs404_bimc_regmap_config,
1084 .qos_offset = 0x8000,
1085 .ab_coeff = 153,
1086};
1087
1088static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = {
1089 [MASTER_SPDM] = &mas_spdm,
1090 [MASTER_BLSP_1] = &mas_blsp_1,
1091 [MASTER_BLSP_2] = &mas_blsp_2,
1092 [MASTER_XI_USB_HS1] = &mas_xi_usb_hs1,
1093 [MASTER_CRYPT0] = &mas_crypto,
1094 [MASTER_SDCC_1] = &mas_sdcc_1,
1095 [MASTER_SDCC_2] = &mas_sdcc_2,
1096 [MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc,
1097 [MASTER_QPIC] = &mas_qpic,
1098 [PCNOC_INT_0] = &pcnoc_int_0,
1099 [PCNOC_INT_2] = &pcnoc_int_2,
1100 [PCNOC_INT_3] = &pcnoc_int_3,
1101 [PCNOC_S_0] = &pcnoc_s_0,
1102 [PCNOC_S_1] = &pcnoc_s_1,
1103 [PCNOC_S_2] = &pcnoc_s_2,
1104 [PCNOC_S_3] = &pcnoc_s_3,
1105 [PCNOC_S_4] = &pcnoc_s_4,
1106 [PCNOC_S_6] = &pcnoc_s_6,
1107 [PCNOC_S_7] = &pcnoc_s_7,
1108 [PCNOC_S_8] = &pcnoc_s_8,
1109 [PCNOC_S_9] = &pcnoc_s_9,
1110 [PCNOC_S_10] = &pcnoc_s_10,
1111 [PCNOC_S_11] = &pcnoc_s_11,
1112 [SLAVE_SPDM] = &slv_spdm,
1113 [SLAVE_PDM] = &slv_pdm,
1114 [SLAVE_PRNG] = &slv_prng,
1115 [SLAVE_TCSR] = &slv_tcsr,
1116 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1117 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1118 [SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg,
1119 [SLAVE_GPU_CFG] = &slv_gpu_cfg,
1120 [SLAVE_BLSP_1] = &slv_blsp_1,
1121 [SLAVE_BLSP_2] = &slv_blsp_2,
1122 [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1123 [SLAVE_PCIE] = &slv_pcie,
1124 [SLAVE_ETHERNET] = &slv_ethernet,
1125 [SLAVE_TLMM_EAST] = &slv_tlmm_east,
1126 [SLAVE_TCU] = &slv_tcu,
1127 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1128 [SLAVE_SDCC_1] = &slv_sdcc_1,
1129 [SLAVE_SDCC_2] = &slv_sdcc_2,
1130 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1131 [SLAVE_USB_HS] = &slv_usb_hs,
1132 [SLAVE_USB3] = &slv_usb3,
1133 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1134 [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
1135};
1136
1137static const struct regmap_config qcs404_pcnoc_regmap_config = {
1138 .reg_bits = 32,
1139 .reg_stride = 4,
1140 .val_bits = 32,
1141 .max_register = 0x15080,
1142 .fast_io = true,
1143};
1144
1145static const struct qcom_icc_desc qcs404_pcnoc = {
1146 .type = QCOM_ICC_NOC,
1147 .nodes = qcs404_pcnoc_nodes,
1148 .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
1149 .bus_clk_desc = &bus_0_clk,
1150 .qos_offset = 0x7000,
1151 .keep_alive = true,
1152 .regmap_cfg = &qcs404_pcnoc_regmap_config,
1153};
1154
1155static struct qcom_icc_node * const qcs404_snoc_nodes[] = {
1156 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1157 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1158 [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc,
1159 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1160 [MASTER_EMAC] = &mas_emac,
1161 [MASTER_PCIE] = &mas_pcie,
1162 [MASTER_USB3] = &mas_usb3,
1163 [QDSS_INT] = &qdss_int,
1164 [SNOC_INT_0] = &snoc_int_0,
1165 [SNOC_INT_1] = &snoc_int_1,
1166 [SNOC_INT_2] = &snoc_int_2,
1167 [SLAVE_KPSS_AHB] = &slv_kpss_ahb,
1168 [SLAVE_WCSS] = &slv_wcss,
1169 [SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1,
1170 [SLAVE_IMEM] = &slv_imem,
1171 [SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc,
1172 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1173 [SLAVE_CATS_0] = &slv_cats_0,
1174 [SLAVE_CATS_1] = &slv_cats_1,
1175 [SLAVE_LPASS] = &slv_lpass,
1176};
1177
1178static const struct regmap_config qcs404_snoc_regmap_config = {
1179 .reg_bits = 32,
1180 .reg_stride = 4,
1181 .val_bits = 32,
1182 .max_register = 0x23080,
1183 .fast_io = true,
1184};
1185
1186static const struct qcom_icc_desc qcs404_snoc = {
1187 .type = QCOM_ICC_NOC,
1188 .nodes = qcs404_snoc_nodes,
1189 .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
1190 .bus_clk_desc = &bus_1_clk,
1191 .qos_offset = 0x11000,
1192 .regmap_cfg = &qcs404_snoc_regmap_config,
1193};
1194
1195
1196static const struct of_device_id qcs404_noc_of_match[] = {
1197 { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc },
1198 { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc },
1199 { .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc },
1200 { },
1201};
1202MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
1203
1204static struct platform_driver qcs404_noc_driver = {
1205 .probe = qnoc_probe,
1206 .remove = qnoc_remove,
1207 .driver = {
1208 .name = "qnoc-qcs404",
1209 .of_match_table = qcs404_noc_of_match,
1210 },
1211};
1212module_platform_driver(qcs404_noc_driver);
1213MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver");
1214MODULE_LICENSE("GPL v2");