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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver
4 * Copyright (C) 2020, AngeloGioacchino Del Regno <[email protected]>
5 */
6
7#include <dt-bindings/interconnect/qcom,sdm660.h>
8#include <linux/device.h>
9#include <linux/interconnect-provider.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14#include <linux/slab.h>
15
16#include "icc-rpm.h"
17
18enum {
19 SDM660_MASTER_IPA = 1,
20 SDM660_MASTER_CNOC_A2NOC,
21 SDM660_MASTER_SDCC_1,
22 SDM660_MASTER_SDCC_2,
23 SDM660_MASTER_BLSP_1,
24 SDM660_MASTER_BLSP_2,
25 SDM660_MASTER_UFS,
26 SDM660_MASTER_USB_HS,
27 SDM660_MASTER_USB3,
28 SDM660_MASTER_CRYPTO_C0,
29 SDM660_MASTER_GNOC_BIMC,
30 SDM660_MASTER_OXILI,
31 SDM660_MASTER_MNOC_BIMC,
32 SDM660_MASTER_SNOC_BIMC,
33 SDM660_MASTER_PIMEM,
34 SDM660_MASTER_SNOC_CNOC,
35 SDM660_MASTER_QDSS_DAP,
36 SDM660_MASTER_APPS_PROC,
37 SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
38 SDM660_MASTER_CNOC_MNOC_CFG,
39 SDM660_MASTER_CPP,
40 SDM660_MASTER_JPEG,
41 SDM660_MASTER_MDP_P0,
42 SDM660_MASTER_MDP_P1,
43 SDM660_MASTER_VENUS,
44 SDM660_MASTER_VFE,
45 SDM660_MASTER_QDSS_ETR,
46 SDM660_MASTER_QDSS_BAM,
47 SDM660_MASTER_SNOC_CFG,
48 SDM660_MASTER_BIMC_SNOC,
49 SDM660_MASTER_A2NOC_SNOC,
50 SDM660_MASTER_GNOC_SNOC,
51
52 SDM660_SLAVE_A2NOC_SNOC,
53 SDM660_SLAVE_EBI,
54 SDM660_SLAVE_HMSS_L3,
55 SDM660_SLAVE_BIMC_SNOC,
56 SDM660_SLAVE_CNOC_A2NOC,
57 SDM660_SLAVE_MPM,
58 SDM660_SLAVE_PMIC_ARB,
59 SDM660_SLAVE_TLMM_NORTH,
60 SDM660_SLAVE_TCSR,
61 SDM660_SLAVE_PIMEM_CFG,
62 SDM660_SLAVE_IMEM_CFG,
63 SDM660_SLAVE_MESSAGE_RAM,
64 SDM660_SLAVE_GLM,
65 SDM660_SLAVE_BIMC_CFG,
66 SDM660_SLAVE_PRNG,
67 SDM660_SLAVE_SPDM,
68 SDM660_SLAVE_QDSS_CFG,
69 SDM660_SLAVE_CNOC_MNOC_CFG,
70 SDM660_SLAVE_SNOC_CFG,
71 SDM660_SLAVE_QM_CFG,
72 SDM660_SLAVE_CLK_CTL,
73 SDM660_SLAVE_MSS_CFG,
74 SDM660_SLAVE_TLMM_SOUTH,
75 SDM660_SLAVE_UFS_CFG,
76 SDM660_SLAVE_A2NOC_CFG,
77 SDM660_SLAVE_A2NOC_SMMU_CFG,
78 SDM660_SLAVE_GPUSS_CFG,
79 SDM660_SLAVE_AHB2PHY,
80 SDM660_SLAVE_BLSP_1,
81 SDM660_SLAVE_SDCC_1,
82 SDM660_SLAVE_SDCC_2,
83 SDM660_SLAVE_TLMM_CENTER,
84 SDM660_SLAVE_BLSP_2,
85 SDM660_SLAVE_PDM,
86 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
87 SDM660_SLAVE_USB_HS,
88 SDM660_SLAVE_USB3_0,
89 SDM660_SLAVE_SRVC_CNOC,
90 SDM660_SLAVE_GNOC_BIMC,
91 SDM660_SLAVE_GNOC_SNOC,
92 SDM660_SLAVE_CAMERA_CFG,
93 SDM660_SLAVE_CAMERA_THROTTLE_CFG,
94 SDM660_SLAVE_MISC_CFG,
95 SDM660_SLAVE_VENUS_THROTTLE_CFG,
96 SDM660_SLAVE_VENUS_CFG,
97 SDM660_SLAVE_MMSS_CLK_XPU_CFG,
98 SDM660_SLAVE_MMSS_CLK_CFG,
99 SDM660_SLAVE_MNOC_MPU_CFG,
100 SDM660_SLAVE_DISPLAY_CFG,
101 SDM660_SLAVE_CSI_PHY_CFG,
102 SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
103 SDM660_SLAVE_SMMU_CFG,
104 SDM660_SLAVE_MNOC_BIMC,
105 SDM660_SLAVE_SRVC_MNOC,
106 SDM660_SLAVE_HMSS,
107 SDM660_SLAVE_LPASS,
108 SDM660_SLAVE_WLAN,
109 SDM660_SLAVE_CDSP,
110 SDM660_SLAVE_IPA,
111 SDM660_SLAVE_SNOC_BIMC,
112 SDM660_SLAVE_SNOC_CNOC,
113 SDM660_SLAVE_IMEM,
114 SDM660_SLAVE_PIMEM,
115 SDM660_SLAVE_QDSS_STM,
116 SDM660_SLAVE_SRVC_SNOC,
117
118 SDM660_A2NOC,
119 SDM660_BIMC,
120 SDM660_CNOC,
121 SDM660_GNOC,
122 SDM660_MNOC,
123 SDM660_SNOC,
124};
125
126static const char * const mm_intf_clocks[] = {
127 "iface",
128};
129
130static const char * const a2noc_intf_clocks[] = {
131 "ipa",
132 "ufs_axi",
133 "aggre2_ufs_axi",
134 "aggre2_usb3_axi",
135 "cfg_noc_usb2_axi",
136};
137
138static const u16 mas_ipa_links[] = {
139 SDM660_SLAVE_A2NOC_SNOC
140};
141
142static struct qcom_icc_node mas_ipa = {
143 .name = "mas_ipa",
144 .id = SDM660_MASTER_IPA,
145 .buswidth = 8,
146 .mas_rpm_id = 59,
147 .slv_rpm_id = -1,
148 .qos.ap_owned = true,
149 .qos.qos_mode = NOC_QOS_MODE_FIXED,
150 .qos.areq_prio = 1,
151 .qos.prio_level = 1,
152 .qos.qos_port = 3,
153 .num_links = ARRAY_SIZE(mas_ipa_links),
154 .links = mas_ipa_links,
155};
156
157static const u16 mas_cnoc_a2noc_links[] = {
158 SDM660_SLAVE_A2NOC_SNOC
159};
160
161static struct qcom_icc_node mas_cnoc_a2noc = {
162 .name = "mas_cnoc_a2noc",
163 .id = SDM660_MASTER_CNOC_A2NOC,
164 .buswidth = 8,
165 .mas_rpm_id = 146,
166 .slv_rpm_id = -1,
167 .qos.ap_owned = true,
168 .qos.qos_mode = NOC_QOS_MODE_INVALID,
169 .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links),
170 .links = mas_cnoc_a2noc_links,
171};
172
173static const u16 mas_sdcc_1_links[] = {
174 SDM660_SLAVE_A2NOC_SNOC
175};
176
177static struct qcom_icc_node mas_sdcc_1 = {
178 .name = "mas_sdcc_1",
179 .id = SDM660_MASTER_SDCC_1,
180 .buswidth = 8,
181 .mas_rpm_id = 33,
182 .slv_rpm_id = -1,
183 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
184 .links = mas_sdcc_1_links,
185};
186
187static const u16 mas_sdcc_2_links[] = {
188 SDM660_SLAVE_A2NOC_SNOC
189};
190
191static struct qcom_icc_node mas_sdcc_2 = {
192 .name = "mas_sdcc_2",
193 .id = SDM660_MASTER_SDCC_2,
194 .buswidth = 8,
195 .mas_rpm_id = 35,
196 .slv_rpm_id = -1,
197 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
198 .links = mas_sdcc_2_links,
199};
200
201static const u16 mas_blsp_1_links[] = {
202 SDM660_SLAVE_A2NOC_SNOC
203};
204
205static struct qcom_icc_node mas_blsp_1 = {
206 .name = "mas_blsp_1",
207 .id = SDM660_MASTER_BLSP_1,
208 .buswidth = 4,
209 .mas_rpm_id = 41,
210 .slv_rpm_id = -1,
211 .num_links = ARRAY_SIZE(mas_blsp_1_links),
212 .links = mas_blsp_1_links,
213};
214
215static const u16 mas_blsp_2_links[] = {
216 SDM660_SLAVE_A2NOC_SNOC
217};
218
219static struct qcom_icc_node mas_blsp_2 = {
220 .name = "mas_blsp_2",
221 .id = SDM660_MASTER_BLSP_2,
222 .buswidth = 4,
223 .mas_rpm_id = 39,
224 .slv_rpm_id = -1,
225 .num_links = ARRAY_SIZE(mas_blsp_2_links),
226 .links = mas_blsp_2_links,
227};
228
229static const u16 mas_ufs_links[] = {
230 SDM660_SLAVE_A2NOC_SNOC
231};
232
233static struct qcom_icc_node mas_ufs = {
234 .name = "mas_ufs",
235 .id = SDM660_MASTER_UFS,
236 .buswidth = 8,
237 .mas_rpm_id = 68,
238 .slv_rpm_id = -1,
239 .qos.ap_owned = true,
240 .qos.qos_mode = NOC_QOS_MODE_FIXED,
241 .qos.areq_prio = 1,
242 .qos.prio_level = 1,
243 .qos.qos_port = 4,
244 .num_links = ARRAY_SIZE(mas_ufs_links),
245 .links = mas_ufs_links,
246};
247
248static const u16 mas_usb_hs_links[] = {
249 SDM660_SLAVE_A2NOC_SNOC
250};
251
252static struct qcom_icc_node mas_usb_hs = {
253 .name = "mas_usb_hs",
254 .id = SDM660_MASTER_USB_HS,
255 .buswidth = 8,
256 .mas_rpm_id = 42,
257 .slv_rpm_id = -1,
258 .qos.ap_owned = true,
259 .qos.qos_mode = NOC_QOS_MODE_FIXED,
260 .qos.areq_prio = 1,
261 .qos.prio_level = 1,
262 .qos.qos_port = 1,
263 .num_links = ARRAY_SIZE(mas_usb_hs_links),
264 .links = mas_usb_hs_links,
265};
266
267static const u16 mas_usb3_links[] = {
268 SDM660_SLAVE_A2NOC_SNOC
269};
270
271static struct qcom_icc_node mas_usb3 = {
272 .name = "mas_usb3",
273 .id = SDM660_MASTER_USB3,
274 .buswidth = 8,
275 .mas_rpm_id = 32,
276 .slv_rpm_id = -1,
277 .qos.ap_owned = true,
278 .qos.qos_mode = NOC_QOS_MODE_FIXED,
279 .qos.areq_prio = 1,
280 .qos.prio_level = 1,
281 .qos.qos_port = 2,
282 .num_links = ARRAY_SIZE(mas_usb3_links),
283 .links = mas_usb3_links,
284};
285
286static const u16 mas_crypto_links[] = {
287 SDM660_SLAVE_A2NOC_SNOC
288};
289
290static struct qcom_icc_node mas_crypto = {
291 .name = "mas_crypto",
292 .id = SDM660_MASTER_CRYPTO_C0,
293 .buswidth = 8,
294 .mas_rpm_id = 23,
295 .slv_rpm_id = -1,
296 .qos.ap_owned = true,
297 .qos.qos_mode = NOC_QOS_MODE_FIXED,
298 .qos.areq_prio = 1,
299 .qos.prio_level = 1,
300 .qos.qos_port = 11,
301 .num_links = ARRAY_SIZE(mas_crypto_links),
302 .links = mas_crypto_links,
303};
304
305static const u16 mas_gnoc_bimc_links[] = {
306 SDM660_SLAVE_EBI
307};
308
309static struct qcom_icc_node mas_gnoc_bimc = {
310 .name = "mas_gnoc_bimc",
311 .id = SDM660_MASTER_GNOC_BIMC,
312 .buswidth = 4,
313 .mas_rpm_id = 144,
314 .slv_rpm_id = -1,
315 .qos.ap_owned = true,
316 .qos.qos_mode = NOC_QOS_MODE_FIXED,
317 .qos.areq_prio = 0,
318 .qos.prio_level = 0,
319 .qos.qos_port = 0,
320 .num_links = ARRAY_SIZE(mas_gnoc_bimc_links),
321 .links = mas_gnoc_bimc_links,
322};
323
324static const u16 mas_oxili_links[] = {
325 SDM660_SLAVE_HMSS_L3,
326 SDM660_SLAVE_EBI,
327 SDM660_SLAVE_BIMC_SNOC
328};
329
330static struct qcom_icc_node mas_oxili = {
331 .name = "mas_oxili",
332 .id = SDM660_MASTER_OXILI,
333 .buswidth = 4,
334 .mas_rpm_id = 6,
335 .slv_rpm_id = -1,
336 .qos.ap_owned = true,
337 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
338 .qos.areq_prio = 0,
339 .qos.prio_level = 0,
340 .qos.qos_port = 1,
341 .num_links = ARRAY_SIZE(mas_oxili_links),
342 .links = mas_oxili_links,
343};
344
345static const u16 mas_mnoc_bimc_links[] = {
346 SDM660_SLAVE_HMSS_L3,
347 SDM660_SLAVE_EBI,
348 SDM660_SLAVE_BIMC_SNOC
349};
350
351static struct qcom_icc_node mas_mnoc_bimc = {
352 .name = "mas_mnoc_bimc",
353 .id = SDM660_MASTER_MNOC_BIMC,
354 .buswidth = 4,
355 .mas_rpm_id = 2,
356 .slv_rpm_id = -1,
357 .qos.ap_owned = true,
358 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
359 .qos.areq_prio = 0,
360 .qos.prio_level = 0,
361 .qos.qos_port = 2,
362 .num_links = ARRAY_SIZE(mas_mnoc_bimc_links),
363 .links = mas_mnoc_bimc_links,
364};
365
366static const u16 mas_snoc_bimc_links[] = {
367 SDM660_SLAVE_HMSS_L3,
368 SDM660_SLAVE_EBI
369};
370
371static struct qcom_icc_node mas_snoc_bimc = {
372 .name = "mas_snoc_bimc",
373 .id = SDM660_MASTER_SNOC_BIMC,
374 .buswidth = 4,
375 .mas_rpm_id = 3,
376 .slv_rpm_id = -1,
377 .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
378 .links = mas_snoc_bimc_links,
379};
380
381static const u16 mas_pimem_links[] = {
382 SDM660_SLAVE_HMSS_L3,
383 SDM660_SLAVE_EBI
384};
385
386static struct qcom_icc_node mas_pimem = {
387 .name = "mas_pimem",
388 .id = SDM660_MASTER_PIMEM,
389 .buswidth = 4,
390 .mas_rpm_id = 113,
391 .slv_rpm_id = -1,
392 .qos.ap_owned = true,
393 .qos.qos_mode = NOC_QOS_MODE_FIXED,
394 .qos.areq_prio = 1,
395 .qos.prio_level = 1,
396 .qos.qos_port = 4,
397 .num_links = ARRAY_SIZE(mas_pimem_links),
398 .links = mas_pimem_links,
399};
400
401static const u16 mas_snoc_cnoc_links[] = {
402 SDM660_SLAVE_CLK_CTL,
403 SDM660_SLAVE_QDSS_CFG,
404 SDM660_SLAVE_QM_CFG,
405 SDM660_SLAVE_SRVC_CNOC,
406 SDM660_SLAVE_UFS_CFG,
407 SDM660_SLAVE_TCSR,
408 SDM660_SLAVE_A2NOC_SMMU_CFG,
409 SDM660_SLAVE_SNOC_CFG,
410 SDM660_SLAVE_TLMM_SOUTH,
411 SDM660_SLAVE_MPM,
412 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
413 SDM660_SLAVE_SDCC_2,
414 SDM660_SLAVE_SDCC_1,
415 SDM660_SLAVE_SPDM,
416 SDM660_SLAVE_PMIC_ARB,
417 SDM660_SLAVE_PRNG,
418 SDM660_SLAVE_MSS_CFG,
419 SDM660_SLAVE_GPUSS_CFG,
420 SDM660_SLAVE_IMEM_CFG,
421 SDM660_SLAVE_USB3_0,
422 SDM660_SLAVE_A2NOC_CFG,
423 SDM660_SLAVE_TLMM_NORTH,
424 SDM660_SLAVE_USB_HS,
425 SDM660_SLAVE_PDM,
426 SDM660_SLAVE_TLMM_CENTER,
427 SDM660_SLAVE_AHB2PHY,
428 SDM660_SLAVE_BLSP_2,
429 SDM660_SLAVE_BLSP_1,
430 SDM660_SLAVE_PIMEM_CFG,
431 SDM660_SLAVE_GLM,
432 SDM660_SLAVE_MESSAGE_RAM,
433 SDM660_SLAVE_BIMC_CFG,
434 SDM660_SLAVE_CNOC_MNOC_CFG
435};
436
437static struct qcom_icc_node mas_snoc_cnoc = {
438 .name = "mas_snoc_cnoc",
439 .id = SDM660_MASTER_SNOC_CNOC,
440 .buswidth = 8,
441 .mas_rpm_id = 52,
442 .slv_rpm_id = -1,
443 .qos.ap_owned = true,
444 .qos.qos_mode = NOC_QOS_MODE_INVALID,
445 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
446 .links = mas_snoc_cnoc_links,
447};
448
449static const u16 mas_qdss_dap_links[] = {
450 SDM660_SLAVE_CLK_CTL,
451 SDM660_SLAVE_QDSS_CFG,
452 SDM660_SLAVE_QM_CFG,
453 SDM660_SLAVE_SRVC_CNOC,
454 SDM660_SLAVE_UFS_CFG,
455 SDM660_SLAVE_TCSR,
456 SDM660_SLAVE_A2NOC_SMMU_CFG,
457 SDM660_SLAVE_SNOC_CFG,
458 SDM660_SLAVE_TLMM_SOUTH,
459 SDM660_SLAVE_MPM,
460 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
461 SDM660_SLAVE_SDCC_2,
462 SDM660_SLAVE_SDCC_1,
463 SDM660_SLAVE_SPDM,
464 SDM660_SLAVE_PMIC_ARB,
465 SDM660_SLAVE_PRNG,
466 SDM660_SLAVE_MSS_CFG,
467 SDM660_SLAVE_GPUSS_CFG,
468 SDM660_SLAVE_IMEM_CFG,
469 SDM660_SLAVE_USB3_0,
470 SDM660_SLAVE_A2NOC_CFG,
471 SDM660_SLAVE_TLMM_NORTH,
472 SDM660_SLAVE_USB_HS,
473 SDM660_SLAVE_PDM,
474 SDM660_SLAVE_TLMM_CENTER,
475 SDM660_SLAVE_AHB2PHY,
476 SDM660_SLAVE_BLSP_2,
477 SDM660_SLAVE_BLSP_1,
478 SDM660_SLAVE_PIMEM_CFG,
479 SDM660_SLAVE_GLM,
480 SDM660_SLAVE_MESSAGE_RAM,
481 SDM660_SLAVE_CNOC_A2NOC,
482 SDM660_SLAVE_BIMC_CFG,
483 SDM660_SLAVE_CNOC_MNOC_CFG
484};
485
486static struct qcom_icc_node mas_qdss_dap = {
487 .name = "mas_qdss_dap",
488 .id = SDM660_MASTER_QDSS_DAP,
489 .buswidth = 8,
490 .mas_rpm_id = 49,
491 .slv_rpm_id = -1,
492 .qos.ap_owned = true,
493 .qos.qos_mode = NOC_QOS_MODE_INVALID,
494 .num_links = ARRAY_SIZE(mas_qdss_dap_links),
495 .links = mas_qdss_dap_links,
496};
497
498static const u16 mas_apss_proc_links[] = {
499 SDM660_SLAVE_GNOC_SNOC,
500 SDM660_SLAVE_GNOC_BIMC
501};
502
503static struct qcom_icc_node mas_apss_proc = {
504 .name = "mas_apss_proc",
505 .id = SDM660_MASTER_APPS_PROC,
506 .buswidth = 16,
507 .mas_rpm_id = 0,
508 .slv_rpm_id = -1,
509 .qos.ap_owned = true,
510 .qos.qos_mode = NOC_QOS_MODE_INVALID,
511 .num_links = ARRAY_SIZE(mas_apss_proc_links),
512 .links = mas_apss_proc_links,
513};
514
515static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
516 SDM660_SLAVE_VENUS_THROTTLE_CFG,
517 SDM660_SLAVE_VENUS_CFG,
518 SDM660_SLAVE_CAMERA_THROTTLE_CFG,
519 SDM660_SLAVE_SMMU_CFG,
520 SDM660_SLAVE_CAMERA_CFG,
521 SDM660_SLAVE_CSI_PHY_CFG,
522 SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
523 SDM660_SLAVE_DISPLAY_CFG,
524 SDM660_SLAVE_MMSS_CLK_CFG,
525 SDM660_SLAVE_MNOC_MPU_CFG,
526 SDM660_SLAVE_MISC_CFG,
527 SDM660_SLAVE_MMSS_CLK_XPU_CFG
528};
529
530static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
531 .name = "mas_cnoc_mnoc_mmss_cfg",
532 .id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
533 .buswidth = 8,
534 .mas_rpm_id = 4,
535 .slv_rpm_id = -1,
536 .qos.ap_owned = true,
537 .qos.qos_mode = NOC_QOS_MODE_INVALID,
538 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
539 .links = mas_cnoc_mnoc_mmss_cfg_links,
540};
541
542static const u16 mas_cnoc_mnoc_cfg_links[] = {
543 SDM660_SLAVE_SRVC_MNOC
544};
545
546static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
547 .name = "mas_cnoc_mnoc_cfg",
548 .id = SDM660_MASTER_CNOC_MNOC_CFG,
549 .buswidth = 4,
550 .mas_rpm_id = 5,
551 .slv_rpm_id = -1,
552 .qos.ap_owned = true,
553 .qos.qos_mode = NOC_QOS_MODE_INVALID,
554 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
555 .links = mas_cnoc_mnoc_cfg_links,
556};
557
558static const u16 mas_cpp_links[] = {
559 SDM660_SLAVE_MNOC_BIMC
560};
561
562static struct qcom_icc_node mas_cpp = {
563 .name = "mas_cpp",
564 .id = SDM660_MASTER_CPP,
565 .buswidth = 16,
566 .mas_rpm_id = 115,
567 .slv_rpm_id = -1,
568 .qos.ap_owned = true,
569 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
570 .qos.areq_prio = 0,
571 .qos.prio_level = 0,
572 .qos.qos_port = 4,
573 .num_links = ARRAY_SIZE(mas_cpp_links),
574 .links = mas_cpp_links,
575};
576
577static const u16 mas_jpeg_links[] = {
578 SDM660_SLAVE_MNOC_BIMC
579};
580
581static struct qcom_icc_node mas_jpeg = {
582 .name = "mas_jpeg",
583 .id = SDM660_MASTER_JPEG,
584 .buswidth = 16,
585 .mas_rpm_id = 7,
586 .slv_rpm_id = -1,
587 .qos.ap_owned = true,
588 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
589 .qos.areq_prio = 0,
590 .qos.prio_level = 0,
591 .qos.qos_port = 6,
592 .num_links = ARRAY_SIZE(mas_jpeg_links),
593 .links = mas_jpeg_links,
594};
595
596static const u16 mas_mdp_p0_links[] = {
597 SDM660_SLAVE_MNOC_BIMC
598};
599
600static struct qcom_icc_node mas_mdp_p0 = {
601 .name = "mas_mdp_p0",
602 .id = SDM660_MASTER_MDP_P0,
603 .buswidth = 16,
604 .ib_coeff = 50,
605 .mas_rpm_id = 8,
606 .slv_rpm_id = -1,
607 .qos.ap_owned = true,
608 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
609 .qos.areq_prio = 0,
610 .qos.prio_level = 0,
611 .qos.qos_port = 0,
612 .num_links = ARRAY_SIZE(mas_mdp_p0_links),
613 .links = mas_mdp_p0_links,
614};
615
616static const u16 mas_mdp_p1_links[] = {
617 SDM660_SLAVE_MNOC_BIMC
618};
619
620static struct qcom_icc_node mas_mdp_p1 = {
621 .name = "mas_mdp_p1",
622 .id = SDM660_MASTER_MDP_P1,
623 .buswidth = 16,
624 .ib_coeff = 50,
625 .mas_rpm_id = 61,
626 .slv_rpm_id = -1,
627 .qos.ap_owned = true,
628 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
629 .qos.areq_prio = 0,
630 .qos.prio_level = 0,
631 .qos.qos_port = 1,
632 .num_links = ARRAY_SIZE(mas_mdp_p1_links),
633 .links = mas_mdp_p1_links,
634};
635
636static const u16 mas_venus_links[] = {
637 SDM660_SLAVE_MNOC_BIMC
638};
639
640static struct qcom_icc_node mas_venus = {
641 .name = "mas_venus",
642 .id = SDM660_MASTER_VENUS,
643 .buswidth = 16,
644 .mas_rpm_id = 9,
645 .slv_rpm_id = -1,
646 .qos.ap_owned = true,
647 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
648 .qos.areq_prio = 0,
649 .qos.prio_level = 0,
650 .qos.qos_port = 1,
651 .num_links = ARRAY_SIZE(mas_venus_links),
652 .links = mas_venus_links,
653};
654
655static const u16 mas_vfe_links[] = {
656 SDM660_SLAVE_MNOC_BIMC
657};
658
659static struct qcom_icc_node mas_vfe = {
660 .name = "mas_vfe",
661 .id = SDM660_MASTER_VFE,
662 .buswidth = 16,
663 .mas_rpm_id = 11,
664 .slv_rpm_id = -1,
665 .qos.ap_owned = true,
666 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
667 .qos.areq_prio = 0,
668 .qos.prio_level = 0,
669 .qos.qos_port = 5,
670 .num_links = ARRAY_SIZE(mas_vfe_links),
671 .links = mas_vfe_links,
672};
673
674static const u16 mas_qdss_etr_links[] = {
675 SDM660_SLAVE_PIMEM,
676 SDM660_SLAVE_IMEM,
677 SDM660_SLAVE_SNOC_CNOC,
678 SDM660_SLAVE_SNOC_BIMC
679};
680
681static struct qcom_icc_node mas_qdss_etr = {
682 .name = "mas_qdss_etr",
683 .id = SDM660_MASTER_QDSS_ETR,
684 .buswidth = 8,
685 .mas_rpm_id = 31,
686 .slv_rpm_id = -1,
687 .qos.ap_owned = true,
688 .qos.qos_mode = NOC_QOS_MODE_FIXED,
689 .qos.areq_prio = 1,
690 .qos.prio_level = 1,
691 .qos.qos_port = 1,
692 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
693 .links = mas_qdss_etr_links,
694};
695
696static const u16 mas_qdss_bam_links[] = {
697 SDM660_SLAVE_PIMEM,
698 SDM660_SLAVE_IMEM,
699 SDM660_SLAVE_SNOC_CNOC,
700 SDM660_SLAVE_SNOC_BIMC
701};
702
703static struct qcom_icc_node mas_qdss_bam = {
704 .name = "mas_qdss_bam",
705 .id = SDM660_MASTER_QDSS_BAM,
706 .buswidth = 4,
707 .mas_rpm_id = 19,
708 .slv_rpm_id = -1,
709 .qos.ap_owned = true,
710 .qos.qos_mode = NOC_QOS_MODE_FIXED,
711 .qos.areq_prio = 1,
712 .qos.prio_level = 1,
713 .qos.qos_port = 0,
714 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
715 .links = mas_qdss_bam_links,
716};
717
718static const u16 mas_snoc_cfg_links[] = {
719 SDM660_SLAVE_SRVC_SNOC
720};
721
722static struct qcom_icc_node mas_snoc_cfg = {
723 .name = "mas_snoc_cfg",
724 .id = SDM660_MASTER_SNOC_CFG,
725 .buswidth = 4,
726 .mas_rpm_id = 20,
727 .slv_rpm_id = -1,
728 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
729 .links = mas_snoc_cfg_links,
730};
731
732static const u16 mas_bimc_snoc_links[] = {
733 SDM660_SLAVE_PIMEM,
734 SDM660_SLAVE_IPA,
735 SDM660_SLAVE_QDSS_STM,
736 SDM660_SLAVE_LPASS,
737 SDM660_SLAVE_HMSS,
738 SDM660_SLAVE_CDSP,
739 SDM660_SLAVE_SNOC_CNOC,
740 SDM660_SLAVE_WLAN,
741 SDM660_SLAVE_IMEM
742};
743
744static struct qcom_icc_node mas_bimc_snoc = {
745 .name = "mas_bimc_snoc",
746 .id = SDM660_MASTER_BIMC_SNOC,
747 .buswidth = 8,
748 .mas_rpm_id = 21,
749 .slv_rpm_id = -1,
750 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
751 .links = mas_bimc_snoc_links,
752};
753
754static const u16 mas_gnoc_snoc_links[] = {
755 SDM660_SLAVE_PIMEM,
756 SDM660_SLAVE_IPA,
757 SDM660_SLAVE_QDSS_STM,
758 SDM660_SLAVE_LPASS,
759 SDM660_SLAVE_HMSS,
760 SDM660_SLAVE_CDSP,
761 SDM660_SLAVE_SNOC_CNOC,
762 SDM660_SLAVE_WLAN,
763 SDM660_SLAVE_IMEM
764};
765
766static struct qcom_icc_node mas_gnoc_snoc = {
767 .name = "mas_gnoc_snoc",
768 .id = SDM660_MASTER_GNOC_SNOC,
769 .buswidth = 8,
770 .mas_rpm_id = 150,
771 .slv_rpm_id = -1,
772 .num_links = ARRAY_SIZE(mas_gnoc_snoc_links),
773 .links = mas_gnoc_snoc_links,
774};
775
776static const u16 mas_a2noc_snoc_links[] = {
777 SDM660_SLAVE_PIMEM,
778 SDM660_SLAVE_IPA,
779 SDM660_SLAVE_QDSS_STM,
780 SDM660_SLAVE_LPASS,
781 SDM660_SLAVE_HMSS,
782 SDM660_SLAVE_SNOC_BIMC,
783 SDM660_SLAVE_CDSP,
784 SDM660_SLAVE_SNOC_CNOC,
785 SDM660_SLAVE_WLAN,
786 SDM660_SLAVE_IMEM
787};
788
789static struct qcom_icc_node mas_a2noc_snoc = {
790 .name = "mas_a2noc_snoc",
791 .id = SDM660_MASTER_A2NOC_SNOC,
792 .buswidth = 16,
793 .mas_rpm_id = 112,
794 .slv_rpm_id = -1,
795 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
796 .links = mas_a2noc_snoc_links,
797};
798
799static const u16 slv_a2noc_snoc_links[] = {
800 SDM660_MASTER_A2NOC_SNOC
801};
802
803static struct qcom_icc_node slv_a2noc_snoc = {
804 .name = "slv_a2noc_snoc",
805 .id = SDM660_SLAVE_A2NOC_SNOC,
806 .buswidth = 16,
807 .mas_rpm_id = -1,
808 .slv_rpm_id = 143,
809 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
810 .links = slv_a2noc_snoc_links,
811};
812
813static struct qcom_icc_node slv_ebi = {
814 .name = "slv_ebi",
815 .id = SDM660_SLAVE_EBI,
816 .buswidth = 4,
817 .mas_rpm_id = -1,
818 .slv_rpm_id = 0,
819};
820
821static struct qcom_icc_node slv_hmss_l3 = {
822 .name = "slv_hmss_l3",
823 .id = SDM660_SLAVE_HMSS_L3,
824 .buswidth = 4,
825 .mas_rpm_id = -1,
826 .slv_rpm_id = 160,
827};
828
829static const u16 slv_bimc_snoc_links[] = {
830 SDM660_MASTER_BIMC_SNOC
831};
832
833static struct qcom_icc_node slv_bimc_snoc = {
834 .name = "slv_bimc_snoc",
835 .id = SDM660_SLAVE_BIMC_SNOC,
836 .buswidth = 4,
837 .mas_rpm_id = -1,
838 .slv_rpm_id = 2,
839 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
840 .links = slv_bimc_snoc_links,
841};
842
843static const u16 slv_cnoc_a2noc_links[] = {
844 SDM660_MASTER_CNOC_A2NOC
845};
846
847static struct qcom_icc_node slv_cnoc_a2noc = {
848 .name = "slv_cnoc_a2noc",
849 .id = SDM660_SLAVE_CNOC_A2NOC,
850 .buswidth = 8,
851 .mas_rpm_id = -1,
852 .slv_rpm_id = 208,
853 .qos.ap_owned = true,
854 .qos.qos_mode = NOC_QOS_MODE_INVALID,
855 .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links),
856 .links = slv_cnoc_a2noc_links,
857};
858
859static struct qcom_icc_node slv_mpm = {
860 .name = "slv_mpm",
861 .id = SDM660_SLAVE_MPM,
862 .buswidth = 4,
863 .mas_rpm_id = -1,
864 .slv_rpm_id = 62,
865 .qos.ap_owned = true,
866 .qos.qos_mode = NOC_QOS_MODE_INVALID,
867};
868
869static struct qcom_icc_node slv_pmic_arb = {
870 .name = "slv_pmic_arb",
871 .id = SDM660_SLAVE_PMIC_ARB,
872 .buswidth = 4,
873 .mas_rpm_id = -1,
874 .slv_rpm_id = 59,
875 .qos.ap_owned = true,
876 .qos.qos_mode = NOC_QOS_MODE_INVALID,
877};
878
879static struct qcom_icc_node slv_tlmm_north = {
880 .name = "slv_tlmm_north",
881 .id = SDM660_SLAVE_TLMM_NORTH,
882 .buswidth = 8,
883 .mas_rpm_id = -1,
884 .slv_rpm_id = 214,
885 .qos.ap_owned = true,
886 .qos.qos_mode = NOC_QOS_MODE_INVALID,
887};
888
889static struct qcom_icc_node slv_tcsr = {
890 .name = "slv_tcsr",
891 .id = SDM660_SLAVE_TCSR,
892 .buswidth = 4,
893 .mas_rpm_id = -1,
894 .slv_rpm_id = 50,
895 .qos.ap_owned = true,
896 .qos.qos_mode = NOC_QOS_MODE_INVALID,
897};
898
899static struct qcom_icc_node slv_pimem_cfg = {
900 .name = "slv_pimem_cfg",
901 .id = SDM660_SLAVE_PIMEM_CFG,
902 .buswidth = 4,
903 .mas_rpm_id = -1,
904 .slv_rpm_id = 167,
905 .qos.ap_owned = true,
906 .qos.qos_mode = NOC_QOS_MODE_INVALID,
907};
908
909static struct qcom_icc_node slv_imem_cfg = {
910 .name = "slv_imem_cfg",
911 .id = SDM660_SLAVE_IMEM_CFG,
912 .buswidth = 4,
913 .mas_rpm_id = -1,
914 .slv_rpm_id = 54,
915 .qos.ap_owned = true,
916 .qos.qos_mode = NOC_QOS_MODE_INVALID,
917};
918
919static struct qcom_icc_node slv_message_ram = {
920 .name = "slv_message_ram",
921 .id = SDM660_SLAVE_MESSAGE_RAM,
922 .buswidth = 4,
923 .mas_rpm_id = -1,
924 .slv_rpm_id = 55,
925 .qos.ap_owned = true,
926 .qos.qos_mode = NOC_QOS_MODE_INVALID,
927};
928
929static struct qcom_icc_node slv_glm = {
930 .name = "slv_glm",
931 .id = SDM660_SLAVE_GLM,
932 .buswidth = 4,
933 .mas_rpm_id = -1,
934 .slv_rpm_id = 209,
935 .qos.ap_owned = true,
936 .qos.qos_mode = NOC_QOS_MODE_INVALID,
937};
938
939static struct qcom_icc_node slv_bimc_cfg = {
940 .name = "slv_bimc_cfg",
941 .id = SDM660_SLAVE_BIMC_CFG,
942 .buswidth = 4,
943 .mas_rpm_id = -1,
944 .slv_rpm_id = 56,
945 .qos.ap_owned = true,
946 .qos.qos_mode = NOC_QOS_MODE_INVALID,
947};
948
949static struct qcom_icc_node slv_prng = {
950 .name = "slv_prng",
951 .id = SDM660_SLAVE_PRNG,
952 .buswidth = 4,
953 .mas_rpm_id = -1,
954 .slv_rpm_id = 44,
955 .qos.ap_owned = true,
956 .qos.qos_mode = NOC_QOS_MODE_INVALID,
957};
958
959static struct qcom_icc_node slv_spdm = {
960 .name = "slv_spdm",
961 .id = SDM660_SLAVE_SPDM,
962 .buswidth = 4,
963 .mas_rpm_id = -1,
964 .slv_rpm_id = 60,
965 .qos.ap_owned = true,
966 .qos.qos_mode = NOC_QOS_MODE_INVALID,
967};
968
969static struct qcom_icc_node slv_qdss_cfg = {
970 .name = "slv_qdss_cfg",
971 .id = SDM660_SLAVE_QDSS_CFG,
972 .buswidth = 4,
973 .mas_rpm_id = -1,
974 .slv_rpm_id = 63,
975 .qos.ap_owned = true,
976 .qos.qos_mode = NOC_QOS_MODE_INVALID,
977};
978
979static const u16 slv_cnoc_mnoc_cfg_links[] = {
980 SDM660_MASTER_CNOC_MNOC_CFG
981};
982
983static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
984 .name = "slv_cnoc_mnoc_cfg",
985 .id = SDM660_SLAVE_CNOC_MNOC_CFG,
986 .buswidth = 4,
987 .mas_rpm_id = -1,
988 .slv_rpm_id = 66,
989 .qos.ap_owned = true,
990 .qos.qos_mode = NOC_QOS_MODE_INVALID,
991 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
992 .links = slv_cnoc_mnoc_cfg_links,
993};
994
995static struct qcom_icc_node slv_snoc_cfg = {
996 .name = "slv_snoc_cfg",
997 .id = SDM660_SLAVE_SNOC_CFG,
998 .buswidth = 4,
999 .mas_rpm_id = -1,
1000 .slv_rpm_id = 70,
1001 .qos.ap_owned = true,
1002 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1003};
1004
1005static struct qcom_icc_node slv_qm_cfg = {
1006 .name = "slv_qm_cfg",
1007 .id = SDM660_SLAVE_QM_CFG,
1008 .buswidth = 4,
1009 .mas_rpm_id = -1,
1010 .slv_rpm_id = 212,
1011 .qos.ap_owned = true,
1012 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1013};
1014
1015static struct qcom_icc_node slv_clk_ctl = {
1016 .name = "slv_clk_ctl",
1017 .id = SDM660_SLAVE_CLK_CTL,
1018 .buswidth = 4,
1019 .mas_rpm_id = -1,
1020 .slv_rpm_id = 47,
1021 .qos.ap_owned = true,
1022 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1023};
1024
1025static struct qcom_icc_node slv_mss_cfg = {
1026 .name = "slv_mss_cfg",
1027 .id = SDM660_SLAVE_MSS_CFG,
1028 .buswidth = 4,
1029 .mas_rpm_id = -1,
1030 .slv_rpm_id = 48,
1031 .qos.ap_owned = true,
1032 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1033};
1034
1035static struct qcom_icc_node slv_tlmm_south = {
1036 .name = "slv_tlmm_south",
1037 .id = SDM660_SLAVE_TLMM_SOUTH,
1038 .buswidth = 4,
1039 .mas_rpm_id = -1,
1040 .slv_rpm_id = 217,
1041 .qos.ap_owned = true,
1042 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1043};
1044
1045static struct qcom_icc_node slv_ufs_cfg = {
1046 .name = "slv_ufs_cfg",
1047 .id = SDM660_SLAVE_UFS_CFG,
1048 .buswidth = 4,
1049 .mas_rpm_id = -1,
1050 .slv_rpm_id = 92,
1051 .qos.ap_owned = true,
1052 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1053};
1054
1055static struct qcom_icc_node slv_a2noc_cfg = {
1056 .name = "slv_a2noc_cfg",
1057 .id = SDM660_SLAVE_A2NOC_CFG,
1058 .buswidth = 4,
1059 .mas_rpm_id = -1,
1060 .slv_rpm_id = 150,
1061 .qos.ap_owned = true,
1062 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1063};
1064
1065static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1066 .name = "slv_a2noc_smmu_cfg",
1067 .id = SDM660_SLAVE_A2NOC_SMMU_CFG,
1068 .buswidth = 8,
1069 .mas_rpm_id = -1,
1070 .slv_rpm_id = 152,
1071 .qos.ap_owned = true,
1072 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1073};
1074
1075static struct qcom_icc_node slv_gpuss_cfg = {
1076 .name = "slv_gpuss_cfg",
1077 .id = SDM660_SLAVE_GPUSS_CFG,
1078 .buswidth = 8,
1079 .mas_rpm_id = -1,
1080 .slv_rpm_id = 11,
1081 .qos.ap_owned = true,
1082 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1083};
1084
1085static struct qcom_icc_node slv_ahb2phy = {
1086 .name = "slv_ahb2phy",
1087 .id = SDM660_SLAVE_AHB2PHY,
1088 .buswidth = 4,
1089 .mas_rpm_id = -1,
1090 .slv_rpm_id = 163,
1091 .qos.ap_owned = true,
1092 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1093};
1094
1095static struct qcom_icc_node slv_blsp_1 = {
1096 .name = "slv_blsp_1",
1097 .id = SDM660_SLAVE_BLSP_1,
1098 .buswidth = 4,
1099 .mas_rpm_id = -1,
1100 .slv_rpm_id = 39,
1101 .qos.ap_owned = true,
1102 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1103};
1104
1105static struct qcom_icc_node slv_sdcc_1 = {
1106 .name = "slv_sdcc_1",
1107 .id = SDM660_SLAVE_SDCC_1,
1108 .buswidth = 4,
1109 .mas_rpm_id = -1,
1110 .slv_rpm_id = 31,
1111 .qos.ap_owned = true,
1112 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1113};
1114
1115static struct qcom_icc_node slv_sdcc_2 = {
1116 .name = "slv_sdcc_2",
1117 .id = SDM660_SLAVE_SDCC_2,
1118 .buswidth = 4,
1119 .mas_rpm_id = -1,
1120 .slv_rpm_id = 33,
1121 .qos.ap_owned = true,
1122 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1123};
1124
1125static struct qcom_icc_node slv_tlmm_center = {
1126 .name = "slv_tlmm_center",
1127 .id = SDM660_SLAVE_TLMM_CENTER,
1128 .buswidth = 4,
1129 .mas_rpm_id = -1,
1130 .slv_rpm_id = 218,
1131 .qos.ap_owned = true,
1132 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1133};
1134
1135static struct qcom_icc_node slv_blsp_2 = {
1136 .name = "slv_blsp_2",
1137 .id = SDM660_SLAVE_BLSP_2,
1138 .buswidth = 4,
1139 .mas_rpm_id = -1,
1140 .slv_rpm_id = 37,
1141 .qos.ap_owned = true,
1142 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1143};
1144
1145static struct qcom_icc_node slv_pdm = {
1146 .name = "slv_pdm",
1147 .id = SDM660_SLAVE_PDM,
1148 .buswidth = 4,
1149 .mas_rpm_id = -1,
1150 .slv_rpm_id = 41,
1151 .qos.ap_owned = true,
1152 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1153};
1154
1155static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1156 SDM660_MASTER_CNOC_MNOC_MMSS_CFG
1157};
1158
1159static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1160 .name = "slv_cnoc_mnoc_mmss_cfg",
1161 .id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
1162 .buswidth = 8,
1163 .mas_rpm_id = -1,
1164 .slv_rpm_id = 58,
1165 .qos.ap_owned = true,
1166 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1167 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1168 .links = slv_cnoc_mnoc_mmss_cfg_links,
1169};
1170
1171static struct qcom_icc_node slv_usb_hs = {
1172 .name = "slv_usb_hs",
1173 .id = SDM660_SLAVE_USB_HS,
1174 .buswidth = 4,
1175 .mas_rpm_id = -1,
1176 .slv_rpm_id = 40,
1177 .qos.ap_owned = true,
1178 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1179};
1180
1181static struct qcom_icc_node slv_usb3_0 = {
1182 .name = "slv_usb3_0",
1183 .id = SDM660_SLAVE_USB3_0,
1184 .buswidth = 4,
1185 .mas_rpm_id = -1,
1186 .slv_rpm_id = 22,
1187 .qos.ap_owned = true,
1188 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1189};
1190
1191static struct qcom_icc_node slv_srvc_cnoc = {
1192 .name = "slv_srvc_cnoc",
1193 .id = SDM660_SLAVE_SRVC_CNOC,
1194 .buswidth = 4,
1195 .mas_rpm_id = -1,
1196 .slv_rpm_id = 76,
1197 .qos.ap_owned = true,
1198 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1199};
1200
1201static const u16 slv_gnoc_bimc_links[] = {
1202 SDM660_MASTER_GNOC_BIMC
1203};
1204
1205static struct qcom_icc_node slv_gnoc_bimc = {
1206 .name = "slv_gnoc_bimc",
1207 .id = SDM660_SLAVE_GNOC_BIMC,
1208 .buswidth = 16,
1209 .mas_rpm_id = -1,
1210 .slv_rpm_id = 210,
1211 .qos.ap_owned = true,
1212 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1213 .num_links = ARRAY_SIZE(slv_gnoc_bimc_links),
1214 .links = slv_gnoc_bimc_links,
1215};
1216
1217static const u16 slv_gnoc_snoc_links[] = {
1218 SDM660_MASTER_GNOC_SNOC
1219};
1220
1221static struct qcom_icc_node slv_gnoc_snoc = {
1222 .name = "slv_gnoc_snoc",
1223 .id = SDM660_SLAVE_GNOC_SNOC,
1224 .buswidth = 8,
1225 .mas_rpm_id = -1,
1226 .slv_rpm_id = 211,
1227 .qos.ap_owned = true,
1228 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1229 .num_links = ARRAY_SIZE(slv_gnoc_snoc_links),
1230 .links = slv_gnoc_snoc_links,
1231};
1232
1233static struct qcom_icc_node slv_camera_cfg = {
1234 .name = "slv_camera_cfg",
1235 .id = SDM660_SLAVE_CAMERA_CFG,
1236 .buswidth = 4,
1237 .mas_rpm_id = -1,
1238 .slv_rpm_id = 3,
1239 .qos.ap_owned = true,
1240 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1241};
1242
1243static struct qcom_icc_node slv_camera_throttle_cfg = {
1244 .name = "slv_camera_throttle_cfg",
1245 .id = SDM660_SLAVE_CAMERA_THROTTLE_CFG,
1246 .buswidth = 4,
1247 .mas_rpm_id = -1,
1248 .slv_rpm_id = 154,
1249 .qos.ap_owned = true,
1250 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1251};
1252
1253static struct qcom_icc_node slv_misc_cfg = {
1254 .name = "slv_misc_cfg",
1255 .id = SDM660_SLAVE_MISC_CFG,
1256 .buswidth = 4,
1257 .mas_rpm_id = -1,
1258 .slv_rpm_id = 8,
1259 .qos.ap_owned = true,
1260 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1261};
1262
1263static struct qcom_icc_node slv_venus_throttle_cfg = {
1264 .name = "slv_venus_throttle_cfg",
1265 .id = SDM660_SLAVE_VENUS_THROTTLE_CFG,
1266 .buswidth = 4,
1267 .mas_rpm_id = -1,
1268 .slv_rpm_id = 178,
1269 .qos.ap_owned = true,
1270 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1271};
1272
1273static struct qcom_icc_node slv_venus_cfg = {
1274 .name = "slv_venus_cfg",
1275 .id = SDM660_SLAVE_VENUS_CFG,
1276 .buswidth = 4,
1277 .mas_rpm_id = -1,
1278 .slv_rpm_id = 10,
1279 .qos.ap_owned = true,
1280 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1281};
1282
1283static struct qcom_icc_node slv_mmss_clk_xpu_cfg = {
1284 .name = "slv_mmss_clk_xpu_cfg",
1285 .id = SDM660_SLAVE_MMSS_CLK_XPU_CFG,
1286 .buswidth = 4,
1287 .mas_rpm_id = -1,
1288 .slv_rpm_id = 13,
1289 .qos.ap_owned = true,
1290 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1291};
1292
1293static struct qcom_icc_node slv_mmss_clk_cfg = {
1294 .name = "slv_mmss_clk_cfg",
1295 .id = SDM660_SLAVE_MMSS_CLK_CFG,
1296 .buswidth = 4,
1297 .mas_rpm_id = -1,
1298 .slv_rpm_id = 12,
1299 .qos.ap_owned = true,
1300 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1301};
1302
1303static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1304 .name = "slv_mnoc_mpu_cfg",
1305 .id = SDM660_SLAVE_MNOC_MPU_CFG,
1306 .buswidth = 4,
1307 .mas_rpm_id = -1,
1308 .slv_rpm_id = 14,
1309 .qos.ap_owned = true,
1310 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1311};
1312
1313static struct qcom_icc_node slv_display_cfg = {
1314 .name = "slv_display_cfg",
1315 .id = SDM660_SLAVE_DISPLAY_CFG,
1316 .buswidth = 4,
1317 .mas_rpm_id = -1,
1318 .slv_rpm_id = 4,
1319 .qos.ap_owned = true,
1320 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1321};
1322
1323static struct qcom_icc_node slv_csi_phy_cfg = {
1324 .name = "slv_csi_phy_cfg",
1325 .id = SDM660_SLAVE_CSI_PHY_CFG,
1326 .buswidth = 4,
1327 .mas_rpm_id = -1,
1328 .slv_rpm_id = 224,
1329 .qos.ap_owned = true,
1330 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1331};
1332
1333static struct qcom_icc_node slv_display_throttle_cfg = {
1334 .name = "slv_display_throttle_cfg",
1335 .id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
1336 .buswidth = 4,
1337 .mas_rpm_id = -1,
1338 .slv_rpm_id = 156,
1339 .qos.ap_owned = true,
1340 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1341};
1342
1343static struct qcom_icc_node slv_smmu_cfg = {
1344 .name = "slv_smmu_cfg",
1345 .id = SDM660_SLAVE_SMMU_CFG,
1346 .buswidth = 8,
1347 .mas_rpm_id = -1,
1348 .slv_rpm_id = 205,
1349 .qos.ap_owned = true,
1350 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1351};
1352
1353static const u16 slv_mnoc_bimc_links[] = {
1354 SDM660_MASTER_MNOC_BIMC
1355};
1356
1357static struct qcom_icc_node slv_mnoc_bimc = {
1358 .name = "slv_mnoc_bimc",
1359 .id = SDM660_SLAVE_MNOC_BIMC,
1360 .buswidth = 16,
1361 .mas_rpm_id = -1,
1362 .slv_rpm_id = 16,
1363 .qos.ap_owned = true,
1364 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1365 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1366 .links = slv_mnoc_bimc_links,
1367};
1368
1369static struct qcom_icc_node slv_srvc_mnoc = {
1370 .name = "slv_srvc_mnoc",
1371 .id = SDM660_SLAVE_SRVC_MNOC,
1372 .buswidth = 8,
1373 .mas_rpm_id = -1,
1374 .slv_rpm_id = 17,
1375 .qos.ap_owned = true,
1376 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1377};
1378
1379static struct qcom_icc_node slv_hmss = {
1380 .name = "slv_hmss",
1381 .id = SDM660_SLAVE_HMSS,
1382 .buswidth = 8,
1383 .mas_rpm_id = -1,
1384 .slv_rpm_id = 20,
1385 .qos.ap_owned = true,
1386 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1387};
1388
1389static struct qcom_icc_node slv_lpass = {
1390 .name = "slv_lpass",
1391 .id = SDM660_SLAVE_LPASS,
1392 .buswidth = 4,
1393 .mas_rpm_id = -1,
1394 .slv_rpm_id = 21,
1395 .qos.ap_owned = true,
1396 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1397};
1398
1399static struct qcom_icc_node slv_wlan = {
1400 .name = "slv_wlan",
1401 .id = SDM660_SLAVE_WLAN,
1402 .buswidth = 4,
1403 .mas_rpm_id = -1,
1404 .slv_rpm_id = 206,
1405};
1406
1407static struct qcom_icc_node slv_cdsp = {
1408 .name = "slv_cdsp",
1409 .id = SDM660_SLAVE_CDSP,
1410 .buswidth = 4,
1411 .mas_rpm_id = -1,
1412 .slv_rpm_id = 221,
1413 .qos.ap_owned = true,
1414 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1415};
1416
1417static struct qcom_icc_node slv_ipa = {
1418 .name = "slv_ipa",
1419 .id = SDM660_SLAVE_IPA,
1420 .buswidth = 4,
1421 .mas_rpm_id = -1,
1422 .slv_rpm_id = 183,
1423 .qos.ap_owned = true,
1424 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1425};
1426
1427static const u16 slv_snoc_bimc_links[] = {
1428 SDM660_MASTER_SNOC_BIMC
1429};
1430
1431static struct qcom_icc_node slv_snoc_bimc = {
1432 .name = "slv_snoc_bimc",
1433 .id = SDM660_SLAVE_SNOC_BIMC,
1434 .buswidth = 16,
1435 .mas_rpm_id = -1,
1436 .slv_rpm_id = 24,
1437 .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1438 .links = slv_snoc_bimc_links,
1439};
1440
1441static const u16 slv_snoc_cnoc_links[] = {
1442 SDM660_MASTER_SNOC_CNOC
1443};
1444
1445static struct qcom_icc_node slv_snoc_cnoc = {
1446 .name = "slv_snoc_cnoc",
1447 .id = SDM660_SLAVE_SNOC_CNOC,
1448 .buswidth = 8,
1449 .mas_rpm_id = -1,
1450 .slv_rpm_id = 25,
1451 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1452 .links = slv_snoc_cnoc_links,
1453};
1454
1455static struct qcom_icc_node slv_imem = {
1456 .name = "slv_imem",
1457 .id = SDM660_SLAVE_IMEM,
1458 .buswidth = 8,
1459 .mas_rpm_id = -1,
1460 .slv_rpm_id = 26,
1461};
1462
1463static struct qcom_icc_node slv_pimem = {
1464 .name = "slv_pimem",
1465 .id = SDM660_SLAVE_PIMEM,
1466 .buswidth = 8,
1467 .mas_rpm_id = -1,
1468 .slv_rpm_id = 166,
1469};
1470
1471static struct qcom_icc_node slv_qdss_stm = {
1472 .name = "slv_qdss_stm",
1473 .id = SDM660_SLAVE_QDSS_STM,
1474 .buswidth = 4,
1475 .mas_rpm_id = -1,
1476 .slv_rpm_id = 30,
1477};
1478
1479static struct qcom_icc_node slv_srvc_snoc = {
1480 .name = "slv_srvc_snoc",
1481 .id = SDM660_SLAVE_SRVC_SNOC,
1482 .buswidth = 16,
1483 .mas_rpm_id = -1,
1484 .slv_rpm_id = 29,
1485};
1486
1487static struct qcom_icc_node * const sdm660_a2noc_nodes[] = {
1488 [MASTER_IPA] = &mas_ipa,
1489 [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
1490 [MASTER_SDCC_1] = &mas_sdcc_1,
1491 [MASTER_SDCC_2] = &mas_sdcc_2,
1492 [MASTER_BLSP_1] = &mas_blsp_1,
1493 [MASTER_BLSP_2] = &mas_blsp_2,
1494 [MASTER_UFS] = &mas_ufs,
1495 [MASTER_USB_HS] = &mas_usb_hs,
1496 [MASTER_USB3] = &mas_usb3,
1497 [MASTER_CRYPTO_C0] = &mas_crypto,
1498 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
1499};
1500
1501static const struct regmap_config sdm660_a2noc_regmap_config = {
1502 .reg_bits = 32,
1503 .reg_stride = 4,
1504 .val_bits = 32,
1505 .max_register = 0x20000,
1506 .fast_io = true,
1507};
1508
1509static const struct qcom_icc_desc sdm660_a2noc = {
1510 .type = QCOM_ICC_NOC,
1511 .nodes = sdm660_a2noc_nodes,
1512 .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
1513 .bus_clk_desc = &aggre2_clk,
1514 .intf_clocks = a2noc_intf_clocks,
1515 .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
1516 .regmap_cfg = &sdm660_a2noc_regmap_config,
1517};
1518
1519static struct qcom_icc_node * const sdm660_bimc_nodes[] = {
1520 [MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
1521 [MASTER_OXILI] = &mas_oxili,
1522 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1523 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1524 [MASTER_PIMEM] = &mas_pimem,
1525 [SLAVE_EBI] = &slv_ebi,
1526 [SLAVE_HMSS_L3] = &slv_hmss_l3,
1527 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
1528};
1529
1530static const struct regmap_config sdm660_bimc_regmap_config = {
1531 .reg_bits = 32,
1532 .reg_stride = 4,
1533 .val_bits = 32,
1534 .max_register = 0x80000,
1535 .fast_io = true,
1536};
1537
1538static const struct qcom_icc_desc sdm660_bimc = {
1539 .type = QCOM_ICC_BIMC,
1540 .nodes = sdm660_bimc_nodes,
1541 .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
1542 .bus_clk_desc = &bimc_clk,
1543 .regmap_cfg = &sdm660_bimc_regmap_config,
1544 .ab_coeff = 153,
1545};
1546
1547static struct qcom_icc_node * const sdm660_cnoc_nodes[] = {
1548 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1549 [MASTER_QDSS_DAP] = &mas_qdss_dap,
1550 [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
1551 [SLAVE_MPM] = &slv_mpm,
1552 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1553 [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1554 [SLAVE_TCSR] = &slv_tcsr,
1555 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1556 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1557 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1558 [SLAVE_GLM] = &slv_glm,
1559 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1560 [SLAVE_PRNG] = &slv_prng,
1561 [SLAVE_SPDM] = &slv_spdm,
1562 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1563 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1564 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1565 [SLAVE_QM_CFG] = &slv_qm_cfg,
1566 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1567 [SLAVE_MSS_CFG] = &slv_mss_cfg,
1568 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1569 [SLAVE_UFS_CFG] = &slv_ufs_cfg,
1570 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1571 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1572 [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
1573 [SLAVE_AHB2PHY] = &slv_ahb2phy,
1574 [SLAVE_BLSP_1] = &slv_blsp_1,
1575 [SLAVE_SDCC_1] = &slv_sdcc_1,
1576 [SLAVE_SDCC_2] = &slv_sdcc_2,
1577 [SLAVE_TLMM_CENTER] = &slv_tlmm_center,
1578 [SLAVE_BLSP_2] = &slv_blsp_2,
1579 [SLAVE_PDM] = &slv_pdm,
1580 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
1581 [SLAVE_USB_HS] = &slv_usb_hs,
1582 [SLAVE_USB3_0] = &slv_usb3_0,
1583 [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
1584};
1585
1586static const struct regmap_config sdm660_cnoc_regmap_config = {
1587 .reg_bits = 32,
1588 .reg_stride = 4,
1589 .val_bits = 32,
1590 .max_register = 0x10000,
1591 .fast_io = true,
1592};
1593
1594static const struct qcom_icc_desc sdm660_cnoc = {
1595 .type = QCOM_ICC_NOC,
1596 .nodes = sdm660_cnoc_nodes,
1597 .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
1598 .bus_clk_desc = &bus_2_clk,
1599 .regmap_cfg = &sdm660_cnoc_regmap_config,
1600};
1601
1602static struct qcom_icc_node * const sdm660_gnoc_nodes[] = {
1603 [MASTER_APSS_PROC] = &mas_apss_proc,
1604 [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
1605 [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
1606};
1607
1608static const struct regmap_config sdm660_gnoc_regmap_config = {
1609 .reg_bits = 32,
1610 .reg_stride = 4,
1611 .val_bits = 32,
1612 .max_register = 0xe000,
1613 .fast_io = true,
1614};
1615
1616static const struct qcom_icc_desc sdm660_gnoc = {
1617 .type = QCOM_ICC_NOC,
1618 .nodes = sdm660_gnoc_nodes,
1619 .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
1620 .regmap_cfg = &sdm660_gnoc_regmap_config,
1621};
1622
1623static struct qcom_icc_node * const sdm660_mnoc_nodes[] = {
1624 [MASTER_CPP] = &mas_cpp,
1625 [MASTER_JPEG] = &mas_jpeg,
1626 [MASTER_MDP_P0] = &mas_mdp_p0,
1627 [MASTER_MDP_P1] = &mas_mdp_p1,
1628 [MASTER_VENUS] = &mas_venus,
1629 [MASTER_VFE] = &mas_vfe,
1630 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1631 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1632 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1633 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1634 [SLAVE_MISC_CFG] = &slv_misc_cfg,
1635 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1636 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1637 [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
1638 [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
1639 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1640 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1641 [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
1642 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1643 [SLAVE_SMMU_CFG] = &slv_smmu_cfg,
1644 [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
1645 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1646};
1647
1648static const struct regmap_config sdm660_mnoc_regmap_config = {
1649 .reg_bits = 32,
1650 .reg_stride = 4,
1651 .val_bits = 32,
1652 .max_register = 0x10000,
1653 .fast_io = true,
1654};
1655
1656static const struct qcom_icc_desc sdm660_mnoc = {
1657 .type = QCOM_ICC_NOC,
1658 .nodes = sdm660_mnoc_nodes,
1659 .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
1660 .bus_clk_desc = &mmaxi_0_clk,
1661 .intf_clocks = mm_intf_clocks,
1662 .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
1663 .regmap_cfg = &sdm660_mnoc_regmap_config,
1664 .ab_coeff = 153,
1665};
1666
1667static struct qcom_icc_node * const sdm660_snoc_nodes[] = {
1668 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1669 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1670 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1671 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1672 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
1673 [MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
1674 [SLAVE_HMSS] = &slv_hmss,
1675 [SLAVE_LPASS] = &slv_lpass,
1676 [SLAVE_WLAN] = &slv_wlan,
1677 [SLAVE_CDSP] = &slv_cdsp,
1678 [SLAVE_IPA] = &slv_ipa,
1679 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
1680 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
1681 [SLAVE_IMEM] = &slv_imem,
1682 [SLAVE_PIMEM] = &slv_pimem,
1683 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1684 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1685};
1686
1687static const struct regmap_config sdm660_snoc_regmap_config = {
1688 .reg_bits = 32,
1689 .reg_stride = 4,
1690 .val_bits = 32,
1691 .max_register = 0x20000,
1692 .fast_io = true,
1693};
1694
1695static const struct qcom_icc_desc sdm660_snoc = {
1696 .type = QCOM_ICC_NOC,
1697 .nodes = sdm660_snoc_nodes,
1698 .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
1699 .bus_clk_desc = &bus_1_clk,
1700 .regmap_cfg = &sdm660_snoc_regmap_config,
1701};
1702
1703static const struct of_device_id sdm660_noc_of_match[] = {
1704 { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
1705 { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
1706 { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
1707 { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
1708 { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
1709 { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
1710 { },
1711};
1712MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
1713
1714static struct platform_driver sdm660_noc_driver = {
1715 .probe = qnoc_probe,
1716 .remove = qnoc_remove,
1717 .driver = {
1718 .name = "qnoc-sdm660",
1719 .of_match_table = sdm660_noc_of_match,
1720 },
1721};
1722module_platform_driver(sdm660_noc_driver);
1723MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
1724MODULE_LICENSE("GPL v2");