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| 2 | |
| 3 | * Aspeed 24XX/25XX I2C Interrupt Controller.
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| 4 | *
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| 5 | * Copyright (C) 2012-2017 ASPEED Technology Inc.
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| 6 | * Copyright 2017 IBM Corporation
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| 7 | * Copyright 2017 Google, Inc.
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| 8 |
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| 9 |
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| 10 | #include <linux/irq.h>
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| 11 | #include <linux/irqchip.h>
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| 12 | #include <linux/irqchip/chained_irq.h>
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| 13 | #include <linux/irqdomain.h>
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| 14 | #include <linux/of_address.h>
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| 15 | #include <linux/of_irq.h>
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| 16 | #include <linux/io.h>
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| 17 |
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| 18 |
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| 19 | #define ASPEED_I2C_IC_NUM_BUS 14
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| 20 |
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| 21 | struct aspeed_i2c_ic {
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| 22 | void __iomem *base;
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| 23 | int parent_irq;
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| 24 | struct irq_domain *irq_domain;
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| 25 | };
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| 26 |
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| 27 | |
| 28 | * The aspeed chip provides a single hardware interrupt for all of the I2C
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| 29 | * busses, so we use a dummy interrupt chip to translate this single interrupt
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| 30 | * into multiple interrupts, each associated with a single I2C bus.
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| 31 |
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| 32 | static void aspeed_i2c_ic_irq_handler(struct irq_desc *desc)
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| 33 | {
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| 34 | struct aspeed_i2c_ic *i2c_ic = irq_desc_get_handler_data(desc);
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| 35 | struct irq_chip *chip = irq_desc_get_chip(desc);
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| 36 | unsigned long bit, status;
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| 37 |
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| 38 | chained_irq_enter(chip, desc);
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| 39 | status = readl(i2c_ic->base);
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| 40 | for_each_set_bit(bit, &status, ASPEED_I2C_IC_NUM_BUS)
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| 41 | generic_handle_domain_irq(i2c_ic->irq_domain, bit);
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| 42 |
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| 43 | chained_irq_exit(chip, desc);
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| 44 | }
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| 45 |
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| 46 | |
| 47 | * Set simple handler and mark IRQ as valid. Nothing interesting to do here
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| 48 | * since we are using a dummy interrupt chip.
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| 49 |
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| 50 | static int aspeed_i2c_ic_map_irq_domain(struct irq_domain *domain,
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| 51 | unsigned int irq, irq_hw_number_t hwirq)
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| 52 | {
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| 53 | irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
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| 54 | irq_set_chip_data(irq, domain->host_data);
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| 55 |
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| 56 | return 0;
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| 57 | }
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| 58 |
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| 59 | static const struct irq_domain_ops aspeed_i2c_ic_irq_domain_ops = {
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| 60 | .map = aspeed_i2c_ic_map_irq_domain,
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| 61 | };
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| 62 |
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| 63 | static int __init aspeed_i2c_ic_of_init(struct device_node *node,
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| 64 | struct device_node *parent)
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| 65 | {
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| 66 | struct aspeed_i2c_ic *i2c_ic;
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| 67 | int ret = 0;
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| 68 |
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| 69 | i2c_ic = kzalloc_obj(*i2c_ic);
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| 70 | if (!i2c_ic)
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| 71 | return -ENOMEM;
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| 72 |
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| 73 | i2c_ic->base = of_iomap(node, 0);
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| 74 | if (!i2c_ic->base) {
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| 75 | ret = -ENOMEM;
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| 76 | goto err_free_ic;
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| 77 | }
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| 78 |
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| 79 | i2c_ic->parent_irq = irq_of_parse_and_map(node, 0);
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| 80 | if (!i2c_ic->parent_irq) {
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| 81 | ret = -EINVAL;
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| 82 | goto err_iounmap;
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| 83 | }
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| 84 |
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| 85 | i2c_ic->irq_domain = irq_domain_create_linear(of_fwnode_handle(node), ASPEED_I2C_IC_NUM_BUS,
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| 86 | &aspeed_i2c_ic_irq_domain_ops,
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| 87 | NULL);
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| 88 | if (!i2c_ic->irq_domain) {
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| 89 | ret = -ENOMEM;
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| 90 | goto err_iounmap;
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| 91 | }
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| 92 |
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| 93 | i2c_ic->irq_domain->name = "aspeed-i2c-domain";
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| 94 |
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| 95 | irq_set_chained_handler_and_data(i2c_ic->parent_irq,
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| 96 | aspeed_i2c_ic_irq_handler, i2c_ic);
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| 97 |
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| 98 | pr_info("i2c controller registered, irq %d\n", i2c_ic->parent_irq);
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| 99 |
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| 100 | return 0;
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| 101 |
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| 102 | err_iounmap:
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| 103 | iounmap(i2c_ic->base);
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| 104 | err_free_ic:
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| 105 | kfree(i2c_ic);
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| 106 | return ret;
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| 107 | }
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| 108 |
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| 109 | IRQCHIP_DECLARE(ast2400_i2c_ic, "aspeed,ast2400-i2c-ic", aspeed_i2c_ic_of_init);
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| 110 | IRQCHIP_DECLARE(ast2500_i2c_ic, "aspeed,ast2500-i2c-ic", aspeed_i2c_ic_of_init);
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