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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Atheros AR71xx/AR724x/AR913x MISC interrupt controller
4 *
5 * Copyright (C) 2015 Alban Bedel <[email protected]>
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
7 * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
8 * Copyright (C) 2008 Imre Kaloz <[email protected]>
9 *
10 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
11 */
12
13#include <linux/irqchip.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17
18#include <asm/time.h>
19
20#define AR71XX_RESET_REG_MISC_INT_STATUS 0
21#define AR71XX_RESET_REG_MISC_INT_ENABLE 4
22
23#define ATH79_MISC_IRQ_COUNT 32
24#define ATH79_MISC_PERF_IRQ 5
25
26static int ath79_perfcount_irq;
27
28int get_c0_perfcount_int(void)
29{
30 return ath79_perfcount_irq;
31}
32EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
33
34static void ath79_misc_irq_handler(struct irq_desc *desc)
35{
36 struct irq_domain *domain = irq_desc_get_handler_data(desc);
37 struct irq_chip *chip = irq_desc_get_chip(desc);
38 void __iomem *base = domain->host_data;
39 u32 pending;
40
41 chained_irq_enter(chip, desc);
42
43 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
44 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
45
46 if (!pending) {
47 spurious_interrupt();
48 chained_irq_exit(chip, desc);
49 return;
50 }
51
52 while (pending) {
53 int bit = __ffs(pending);
54
55 generic_handle_domain_irq(domain, bit);
56 pending &= ~BIT(bit);
57 }
58
59 chained_irq_exit(chip, desc);
60}
61
62static void ar71xx_misc_irq_unmask(struct irq_data *d)
63{
64 void __iomem *base = irq_data_get_irq_chip_data(d);
65 unsigned int irq = d->hwirq;
66 u32 t;
67
68 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
69 __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
70
71 /* flush write */
72 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
73}
74
75static void ar71xx_misc_irq_mask(struct irq_data *d)
76{
77 void __iomem *base = irq_data_get_irq_chip_data(d);
78 unsigned int irq = d->hwirq;
79 u32 t;
80
81 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
82 __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
83
84 /* flush write */
85 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
86}
87
88static void ar724x_misc_irq_ack(struct irq_data *d)
89{
90 void __iomem *base = irq_data_get_irq_chip_data(d);
91 unsigned int irq = d->hwirq;
92 u32 t;
93
94 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
95 __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
96
97 /* flush write */
98 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
99}
100
101static struct irq_chip ath79_misc_irq_chip = {
102 .name = "MISC",
103 .irq_unmask = ar71xx_misc_irq_unmask,
104 .irq_mask = ar71xx_misc_irq_mask,
105};
106
107static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
108{
109 irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
110 irq_set_chip_data(irq, d->host_data);
111 return 0;
112}
113
114static const struct irq_domain_ops misc_irq_domain_ops = {
115 .xlate = irq_domain_xlate_onecell,
116 .map = misc_map,
117};
118
119static void __init ath79_misc_intc_domain_init(
120 struct irq_domain *domain, int irq)
121{
122 void __iomem *base = domain->host_data;
123
124 ath79_perfcount_irq = irq_create_mapping(domain, ATH79_MISC_PERF_IRQ);
125
126 /* Disable and clear all interrupts */
127 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
128 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
129
130 irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);
131}
132
133static int __init ath79_misc_intc_of_init(
134 struct device_node *node, struct device_node *parent)
135{
136 struct irq_domain *domain;
137 void __iomem *base;
138 int irq;
139
140 irq = irq_of_parse_and_map(node, 0);
141 if (!irq) {
142 pr_err("Failed to get MISC IRQ\n");
143 return -EINVAL;
144 }
145
146 base = of_iomap(node, 0);
147 if (!base) {
148 pr_err("Failed to get MISC IRQ registers\n");
149 return -ENOMEM;
150 }
151
152 domain = irq_domain_create_linear(of_fwnode_handle(node), ATH79_MISC_IRQ_COUNT,
153 &misc_irq_domain_ops, base);
154 if (!domain) {
155 pr_err("Failed to add MISC irqdomain\n");
156 return -EINVAL;
157 }
158
159 ath79_misc_intc_domain_init(domain, irq);
160 return 0;
161}
162
163static int __init ar7100_misc_intc_of_init(
164 struct device_node *node, struct device_node *parent)
165{
166 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
167 return ath79_misc_intc_of_init(node, parent);
168}
169
170IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
171 ar7100_misc_intc_of_init);
172
173static int __init ar7240_misc_intc_of_init(
174 struct device_node *node, struct device_node *parent)
175{
176 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
177 return ath79_misc_intc_of_init(node, parent);
178}
179
180IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
181 ar7240_misc_intc_of_init);