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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Broadcom BCM7038 style Level 1 interrupt controller driver
4 *
5 * Copyright (C) 2014 Broadcom Corporation
6 * Author: Kevin Cernekee
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/bitops.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_irq.h>
22#include <linux/of_address.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25#include <linux/smp.h>
26#include <linux/types.h>
27#include <linux/irqchip.h>
28#include <linux/irqchip/chained_irq.h>
29#include <linux/syscore_ops.h>
30
31#define IRQS_PER_WORD 32
32#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
33#define MAX_WORDS 8
34
35struct bcm7038_l1_cpu;
36
37struct bcm7038_l1_chip {
38 raw_spinlock_t lock;
39 unsigned int n_words;
40 struct irq_domain *domain;
41 struct bcm7038_l1_cpu *cpus[NR_CPUS];
42#ifdef CONFIG_PM_SLEEP
43 struct list_head list;
44 u32 wake_mask[MAX_WORDS];
45#endif
46 u32 irq_fwd_mask[MAX_WORDS];
47 u8 affinity[MAX_WORDS * IRQS_PER_WORD];
48};
49
50struct bcm7038_l1_cpu {
51 void __iomem *map_base;
52 u32 mask_cache[];
53};
54
55/*
56 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
57 *
58 * 7038:
59 * 0x1000_1400: W0_STATUS
60 * 0x1000_1404: W1_STATUS
61 * 0x1000_1408: W0_MASK_STATUS
62 * 0x1000_140c: W1_MASK_STATUS
63 * 0x1000_1410: W0_MASK_SET
64 * 0x1000_1414: W1_MASK_SET
65 * 0x1000_1418: W0_MASK_CLEAR
66 * 0x1000_141c: W1_MASK_CLEAR
67 *
68 * 7445:
69 * 0xf03e_1500: W0_STATUS
70 * 0xf03e_1504: W1_STATUS
71 * 0xf03e_1508: W2_STATUS
72 * 0xf03e_150c: W3_STATUS
73 * 0xf03e_1510: W4_STATUS
74 * 0xf03e_1514: W0_MASK_STATUS
75 * 0xf03e_1518: W1_MASK_STATUS
76 * [...]
77 */
78
79static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
80 unsigned int word)
81{
82 return (0 * intc->n_words + word) * sizeof(u32);
83}
84
85static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
86 unsigned int word)
87{
88 return (2 * intc->n_words + word) * sizeof(u32);
89}
90
91static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
92 unsigned int word)
93{
94 return (3 * intc->n_words + word) * sizeof(u32);
95}
96
97static inline u32 l1_readl(void __iomem *reg)
98{
99 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
100 return ioread32be(reg);
101 else
102 return readl(reg);
103}
104
105static inline void l1_writel(u32 val, void __iomem *reg)
106{
107 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
108 iowrite32be(val, reg);
109 else
110 writel(val, reg);
111}
112
113static void bcm7038_l1_irq_handle(struct irq_desc *desc)
114{
115 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
116 struct bcm7038_l1_cpu *cpu;
117 struct irq_chip *chip = irq_desc_get_chip(desc);
118 unsigned int idx;
119
120#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
121 cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
122#else
123 cpu = intc->cpus[0];
124#endif
125
126 chained_irq_enter(chip, desc);
127
128 for (idx = 0; idx < intc->n_words; idx++) {
129 int base = idx * IRQS_PER_WORD;
130 unsigned long pending, flags;
131 int hwirq;
132
133 raw_spin_lock_irqsave(&intc->lock, flags);
134 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
135 ~cpu->mask_cache[idx];
136 raw_spin_unlock_irqrestore(&intc->lock, flags);
137
138 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
139 generic_handle_domain_irq(intc->domain, base + hwirq);
140 }
141
142 chained_irq_exit(chip, desc);
143}
144
145static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
146{
147 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
148 u32 word = d->hwirq / IRQS_PER_WORD;
149 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
150
151 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
152 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
153 reg_mask_clr(intc, word));
154}
155
156static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
157{
158 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
159 u32 word = d->hwirq / IRQS_PER_WORD;
160 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
161
162 intc->cpus[cpu_idx]->mask_cache[word] |= mask;
163 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
164 reg_mask_set(intc, word));
165}
166
167static void bcm7038_l1_unmask(struct irq_data *d)
168{
169 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
170 unsigned long flags;
171
172 raw_spin_lock_irqsave(&intc->lock, flags);
173 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
174 raw_spin_unlock_irqrestore(&intc->lock, flags);
175}
176
177static void bcm7038_l1_mask(struct irq_data *d)
178{
179 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
180 unsigned long flags;
181
182 raw_spin_lock_irqsave(&intc->lock, flags);
183 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
184 raw_spin_unlock_irqrestore(&intc->lock, flags);
185}
186
187#if defined(CONFIG_MIPS) && defined(CONFIG_SMP)
188static int bcm7038_l1_set_affinity(struct irq_data *d,
189 const struct cpumask *dest,
190 bool force)
191{
192 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
193 unsigned long flags;
194 irq_hw_number_t hw = d->hwirq;
195 u32 word = hw / IRQS_PER_WORD;
196 u32 mask = BIT(hw % IRQS_PER_WORD);
197 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
198 bool was_disabled;
199
200 raw_spin_lock_irqsave(&intc->lock, flags);
201
202 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
203 mask);
204 __bcm7038_l1_mask(d, intc->affinity[hw]);
205 intc->affinity[hw] = first_cpu;
206 if (!was_disabled)
207 __bcm7038_l1_unmask(d, first_cpu);
208
209 raw_spin_unlock_irqrestore(&intc->lock, flags);
210 irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
211
212 return 0;
213}
214#endif
215
216static int bcm7038_l1_init_one(struct device_node *dn, unsigned int idx,
217 struct bcm7038_l1_chip *intc)
218{
219 struct resource res;
220 resource_size_t sz;
221 struct bcm7038_l1_cpu *cpu;
222 unsigned int i, n_words, parent_irq;
223 int ret;
224
225 if (of_address_to_resource(dn, idx, &res))
226 return -EINVAL;
227 sz = resource_size(&res);
228 n_words = sz / REG_BYTES_PER_IRQ_WORD;
229
230 if (n_words > MAX_WORDS)
231 return -EINVAL;
232 else if (!intc->n_words)
233 intc->n_words = n_words;
234 else if (intc->n_words != n_words)
235 return -EINVAL;
236
237 ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
238 intc->irq_fwd_mask, n_words);
239 if (ret != 0 && ret != -EINVAL) {
240 /* property exists but has the wrong number of words */
241 pr_err("invalid brcm,int-fwd-mask property\n");
242 return -EINVAL;
243 }
244
245 cpu = intc->cpus[idx] = kzalloc_flex(*cpu, mask_cache, n_words);
246 if (!cpu)
247 return -ENOMEM;
248
249 cpu->map_base = ioremap(res.start, sz);
250 if (!cpu->map_base)
251 return -ENOMEM;
252
253 for (i = 0; i < n_words; i++) {
254 l1_writel(~intc->irq_fwd_mask[i],
255 cpu->map_base + reg_mask_set(intc, i));
256 l1_writel(intc->irq_fwd_mask[i],
257 cpu->map_base + reg_mask_clr(intc, i));
258 cpu->mask_cache[i] = ~intc->irq_fwd_mask[i];
259 }
260
261 parent_irq = irq_of_parse_and_map(dn, idx);
262 if (!parent_irq) {
263 pr_err("failed to map parent interrupt %d\n", parent_irq);
264 return -EINVAL;
265 }
266
267 if (of_property_read_bool(dn, "brcm,irq-can-wake"))
268 enable_irq_wake(parent_irq);
269
270 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
271 intc);
272
273 return 0;
274}
275
276#ifdef CONFIG_PM_SLEEP
277/*
278 * We keep a list of bcm7038_l1_chip used for suspend/resume. This hack is
279 * used because the struct chip_type suspend/resume hooks are not called
280 * unless chip_type is hooked onto a generic_chip. Since this driver does
281 * not use generic_chip, we need to manually hook our resume/suspend to
282 * syscore_ops.
283 */
284static LIST_HEAD(bcm7038_l1_intcs_list);
285static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock);
286
287static int bcm7038_l1_suspend(void *data)
288{
289 struct bcm7038_l1_chip *intc;
290 int boot_cpu, word;
291 u32 val;
292
293 /* Wakeup interrupt should only come from the boot cpu */
294#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
295 boot_cpu = cpu_logical_map(0);
296#else
297 boot_cpu = 0;
298#endif
299
300 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
301 for (word = 0; word < intc->n_words; word++) {
302 val = intc->wake_mask[word] | intc->irq_fwd_mask[word];
303 l1_writel(~val,
304 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
305 l1_writel(val,
306 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
307 }
308 }
309
310 return 0;
311}
312
313static void bcm7038_l1_resume(void *data)
314{
315 struct bcm7038_l1_chip *intc;
316 int boot_cpu, word;
317
318#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
319 boot_cpu = cpu_logical_map(0);
320#else
321 boot_cpu = 0;
322#endif
323
324 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
325 for (word = 0; word < intc->n_words; word++) {
326 l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
327 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
328 l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
329 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
330 }
331 }
332}
333
334static const struct syscore_ops bcm7038_l1_syscore_ops = {
335 .suspend = bcm7038_l1_suspend,
336 .resume = bcm7038_l1_resume,
337};
338
339static struct syscore bcm7038_l1_syscore = {
340 .ops = &bcm7038_l1_syscore_ops,
341};
342
343static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
344{
345 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
346 unsigned long flags;
347 u32 word = d->hwirq / IRQS_PER_WORD;
348 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
349
350 raw_spin_lock_irqsave(&intc->lock, flags);
351 if (on)
352 intc->wake_mask[word] |= mask;
353 else
354 intc->wake_mask[word] &= ~mask;
355 raw_spin_unlock_irqrestore(&intc->lock, flags);
356
357 return 0;
358}
359#endif
360
361static struct irq_chip bcm7038_l1_irq_chip = {
362 .name = "bcm7038-l1",
363 .irq_mask = bcm7038_l1_mask,
364 .irq_unmask = bcm7038_l1_unmask,
365#if defined(CONFIG_SMP) && defined(CONFIG_MIPS)
366 .irq_set_affinity = bcm7038_l1_set_affinity,
367#endif
368#ifdef CONFIG_PM_SLEEP
369 .irq_set_wake = bcm7038_l1_set_wake,
370#endif
371};
372
373static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
374 irq_hw_number_t hw_irq)
375{
376 struct bcm7038_l1_chip *intc = d->host_data;
377 u32 mask = BIT(hw_irq % IRQS_PER_WORD);
378 u32 word = hw_irq / IRQS_PER_WORD;
379
380 if (intc->irq_fwd_mask[word] & mask)
381 return -EPERM;
382
383 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
384 irq_set_chip_data(virq, d->host_data);
385 irqd_set_single_target(irq_get_irq_data(virq));
386 return 0;
387}
388
389static const struct irq_domain_ops bcm7038_l1_domain_ops = {
390 .xlate = irq_domain_xlate_onecell,
391 .map = bcm7038_l1_map,
392};
393
394static int bcm7038_l1_probe(struct platform_device *pdev, struct device_node *parent)
395{
396 struct device_node *dn = pdev->dev.of_node;
397 struct bcm7038_l1_chip *intc;
398 int idx, ret;
399
400 intc = kzalloc_obj(*intc);
401 if (!intc)
402 return -ENOMEM;
403
404 raw_spin_lock_init(&intc->lock);
405 for_each_possible_cpu(idx) {
406 ret = bcm7038_l1_init_one(dn, idx, intc);
407 if (ret < 0) {
408 if (idx)
409 break;
410 pr_err("failed to remap intc L1 registers\n");
411 goto out_free;
412 }
413 }
414
415 intc->domain = irq_domain_create_linear(of_fwnode_handle(dn), IRQS_PER_WORD * intc->n_words,
416 &bcm7038_l1_domain_ops,
417 intc);
418 if (!intc->domain) {
419 ret = -ENOMEM;
420 goto out_unmap;
421 }
422
423#ifdef CONFIG_PM_SLEEP
424 /* Add bcm7038_l1_chip into a list */
425 raw_spin_lock(&bcm7038_l1_intcs_lock);
426 list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
427 raw_spin_unlock(&bcm7038_l1_intcs_lock);
428
429 if (list_is_singular(&bcm7038_l1_intcs_list))
430 register_syscore(&bcm7038_l1_syscore);
431#endif
432
433 pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
434 dn, IRQS_PER_WORD * intc->n_words);
435
436 return 0;
437
438out_unmap:
439 for_each_possible_cpu(idx) {
440 struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
441
442 if (cpu) {
443 if (cpu->map_base)
444 iounmap(cpu->map_base);
445 kfree(cpu);
446 }
447 }
448out_free:
449 kfree(intc);
450 return ret;
451}
452
453IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7038_l1)
454IRQCHIP_MATCH("brcm,bcm7038-l1-intc", bcm7038_l1_probe)
455IRQCHIP_PLATFORM_DRIVER_END(bcm7038_l1)
456MODULE_DESCRIPTION("Broadcom STB 7038-style L1/L2 interrupt controller");
457MODULE_LICENSE("GPL v2");