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291 lines · 7.1 KiB

1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <[email protected]>
5 */
6
7#define pr_fmt(fmt) "GICv3: " fmt
8
9#include <linux/iommu.h>
10#include <linux/irq.h>
11#include <linux/irqdomain.h>
12#include <linux/kernel.h>
13#include <linux/msi.h>
14#include <linux/of_address.h>
15#include <linux/of_pci.h>
16#include <linux/slab.h>
17#include <linux/spinlock.h>
18
19#include <linux/irqchip/arm-gic-v3.h>
20
21#include <linux/irqchip/irq-msi-lib.h>
22
23struct mbi_range {
24 u32 spi_start;
25 u32 nr_spis;
26 unsigned long *bm;
27};
28
29static DEFINE_MUTEX(mbi_lock);
30static phys_addr_t mbi_phys_base;
31static struct mbi_range *mbi_ranges;
32static unsigned int mbi_range_nr;
33
34static struct irq_chip mbi_irq_chip = {
35 .name = "MBI",
36 .irq_mask = irq_chip_mask_parent,
37 .irq_unmask = irq_chip_unmask_parent,
38 .irq_eoi = irq_chip_eoi_parent,
39 .irq_set_type = irq_chip_set_type_parent,
40 .irq_set_affinity = irq_chip_set_affinity_parent,
41};
42
43static int mbi_irq_gic_domain_alloc(struct irq_domain *domain,
44 unsigned int virq,
45 irq_hw_number_t hwirq)
46{
47 struct irq_fwspec fwspec;
48 struct irq_data *d;
49 int err;
50
51 /*
52 * Using ACPI? There is no MBI support in the spec, you
53 * shouldn't even be here.
54 */
55 if (!is_of_node(domain->parent->fwnode))
56 return -EINVAL;
57
58 /*
59 * Let's default to edge. This is consistent with traditional
60 * MSIs, and systems requiring level signaling will just
61 * enforce the trigger on their own.
62 */
63 fwspec.fwnode = domain->parent->fwnode;
64 fwspec.param_count = 3;
65 fwspec.param[0] = 0;
66 fwspec.param[1] = hwirq - 32;
67 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
68
69 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
70 if (err)
71 return err;
72
73 d = irq_domain_get_irq_data(domain->parent, virq);
74 return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
75}
76
77static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq,
78 int nr_irqs)
79{
80 mutex_lock(&mbi_lock);
81 bitmap_release_region(mbi->bm, hwirq - mbi->spi_start,
82 get_count_order(nr_irqs));
83 mutex_unlock(&mbi_lock);
84}
85
86static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
87 unsigned int nr_irqs, void *args)
88{
89 msi_alloc_info_t *info = args;
90 struct mbi_range *mbi = NULL;
91 int hwirq, offset, i, err = 0;
92
93 mutex_lock(&mbi_lock);
94 for (i = 0; i < mbi_range_nr; i++) {
95 offset = bitmap_find_free_region(mbi_ranges[i].bm,
96 mbi_ranges[i].nr_spis,
97 get_count_order(nr_irqs));
98 if (offset >= 0) {
99 mbi = &mbi_ranges[i];
100 break;
101 }
102 }
103 mutex_unlock(&mbi_lock);
104
105 if (!mbi)
106 return -ENOSPC;
107
108 hwirq = mbi->spi_start + offset;
109
110 err = iommu_dma_prepare_msi(info->desc,
111 mbi_phys_base + GICD_SETSPI_NSR);
112 if (err)
113 return err;
114
115 for (i = 0; i < nr_irqs; i++) {
116 err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
117 if (err)
118 goto fail;
119
120 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
121 &mbi_irq_chip, mbi);
122 }
123
124 return 0;
125
126fail:
127 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
128 mbi_free_msi(mbi, hwirq, nr_irqs);
129 return err;
130}
131
132static void mbi_irq_domain_free(struct irq_domain *domain,
133 unsigned int virq, unsigned int nr_irqs)
134{
135 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
136 struct mbi_range *mbi = irq_data_get_irq_chip_data(d);
137
138 mbi_free_msi(mbi, d->hwirq, nr_irqs);
139 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
140}
141
142static const struct irq_domain_ops mbi_domain_ops = {
143 .select = msi_lib_irq_domain_select,
144 .alloc = mbi_irq_domain_alloc,
145 .free = mbi_irq_domain_free,
146};
147
148static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
149{
150 msg[0].data = data->parent_data->hwirq;
151 msi_msg_set_addr(irq_data_get_msi_desc(data), &msg[0],
152 mbi_phys_base + GICD_SETSPI_NSR);
153}
154
155static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg)
156{
157 mbi_compose_msi_msg(data, msg);
158
159 msg[1].data = data->parent_data->hwirq;
160 msi_msg_set_addr(irq_data_get_msi_desc(data), &msg[1],
161 mbi_phys_base + GICD_CLRSPI_NSR);
162}
163
164static bool mbi_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
165 struct irq_domain *real_parent, struct msi_domain_info *info)
166{
167 if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
168 return false;
169
170 switch (info->bus_token) {
171 case DOMAIN_BUS_PCI_DEVICE_MSI:
172 case DOMAIN_BUS_PCI_DEVICE_MSIX:
173 info->chip->irq_compose_msi_msg = mbi_compose_msi_msg;
174 return true;
175
176 case DOMAIN_BUS_DEVICE_MSI:
177 info->chip->irq_compose_msi_msg = mbi_compose_mbi_msg;
178 info->chip->irq_set_type = irq_chip_set_type_parent;
179 info->chip->flags |= IRQCHIP_SUPPORTS_LEVEL_MSI;
180 info->flags |= MSI_FLAG_LEVEL_CAPABLE;
181 return true;
182
183 default:
184 WARN_ON_ONCE(1);
185 return false;
186 }
187}
188
189#define MBI_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
190 MSI_FLAG_USE_DEF_CHIP_OPS | \
191 MSI_FLAG_PCI_MSI_MASK_PARENT)
192
193#define MBI_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \
194 MSI_FLAG_PCI_MSIX | \
195 MSI_FLAG_MULTI_PCI_MSI)
196
197static const struct msi_parent_ops gic_v3_mbi_msi_parent_ops = {
198 .supported_flags = MBI_MSI_FLAGS_SUPPORTED,
199 .required_flags = MBI_MSI_FLAGS_REQUIRED,
200 .chip_flags = MSI_CHIP_FLAG_SET_EOI,
201 .bus_select_token = DOMAIN_BUS_NEXUS,
202 .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI,
203 .prefix = "MBI-",
204 .init_dev_msi_info = mbi_init_dev_msi_info,
205};
206
207static int mbi_allocate_domain(struct irq_domain *parent)
208{
209 struct irq_domain_info info = {
210 .fwnode = parent->fwnode,
211 .ops = &mbi_domain_ops,
212 .parent = parent,
213 };
214
215 return msi_create_parent_irq_domain(&info, &gic_v3_mbi_msi_parent_ops) ? 0 : -ENOMEM;
216}
217
218int __init mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent)
219{
220 struct device_node *np;
221 const __be32 *reg;
222 int ret, n;
223
224 np = to_of_node(fwnode);
225
226 if (!of_property_read_bool(np, "msi-controller"))
227 return 0;
228
229 n = of_property_count_elems_of_size(np, "mbi-ranges", sizeof(u32));
230 if (n <= 0 || n % 2)
231 return -EINVAL;
232
233 mbi_range_nr = n / 2;
234 mbi_ranges = kzalloc_objs(*mbi_ranges, mbi_range_nr);
235 if (!mbi_ranges)
236 return -ENOMEM;
237
238 for (n = 0; n < mbi_range_nr; n++) {
239 ret = of_property_read_u32_index(np, "mbi-ranges", n * 2,
240 &mbi_ranges[n].spi_start);
241 if (ret)
242 goto err_free_mbi;
243 ret = of_property_read_u32_index(np, "mbi-ranges", n * 2 + 1,
244 &mbi_ranges[n].nr_spis);
245 if (ret)
246 goto err_free_mbi;
247
248 mbi_ranges[n].bm = bitmap_zalloc(mbi_ranges[n].nr_spis, GFP_KERNEL);
249 if (!mbi_ranges[n].bm) {
250 ret = -ENOMEM;
251 goto err_free_mbi;
252 }
253 pr_info("MBI range [%d:%d]\n", mbi_ranges[n].spi_start,
254 mbi_ranges[n].spi_start + mbi_ranges[n].nr_spis - 1);
255 }
256
257 reg = of_get_property(np, "mbi-alias", NULL);
258 if (reg) {
259 mbi_phys_base = of_translate_address(np, reg);
260 if (mbi_phys_base == (phys_addr_t)OF_BAD_ADDR) {
261 ret = -ENXIO;
262 goto err_free_mbi;
263 }
264 } else {
265 struct resource res;
266
267 if (of_address_to_resource(np, 0, &res)) {
268 ret = -ENXIO;
269 goto err_free_mbi;
270 }
271
272 mbi_phys_base = res.start;
273 }
274
275 pr_info("Using MBI frame %pa\n", &mbi_phys_base);
276
277 ret = mbi_allocate_domain(parent);
278 if (ret)
279 goto err_free_mbi;
280
281 return 0;
282
283err_free_mbi:
284 if (mbi_ranges) {
285 for (n = 0; n < mbi_range_nr; n++)
286 bitmap_free(mbi_ranges[n].bm);
287 kfree(mbi_ranges);
288 }
289
290 return ret;
291}