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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved.
4 */
5
6#define pr_fmt(fmt) "GICv5: " fmt
7
8#include <linux/acpi_iort.h>
9#include <linux/cpuhotplug.h>
10#include <linux/idr.h>
11#include <linux/irqdomain.h>
12#include <linux/slab.h>
13#include <linux/wordpart.h>
14
15#include <linux/irqchip.h>
16#include <linux/irqchip/arm-gic-v5.h>
17#include <linux/irqchip/arm-vgic-info.h>
18
19#include <asm/cpufeature.h>
20#include <asm/exception.h>
21
22static u8 pri_bits __ro_after_init = 5;
23
24#define GICV5_IRQ_PRI_MASK 0x1f
25#define GICV5_IRQ_PRI_MI (GICV5_IRQ_PRI_MASK & GENMASK(4, 5 - pri_bits))
26
27#define PPI_NR 128
28
29static bool gicv5_cpuif_has_gcie(void)
30{
31 return this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF);
32}
33
34struct gicv5_chip_data gicv5_global_data __read_mostly;
35
36static DEFINE_IDA(lpi_ida);
37static u32 num_lpis __ro_after_init;
38
39void __init gicv5_init_lpis(u32 lpis)
40{
41 num_lpis = lpis;
42}
43
44void __init gicv5_deinit_lpis(void)
45{
46 num_lpis = 0;
47}
48
49static int alloc_lpi(void)
50{
51 if (!num_lpis)
52 return -ENOSPC;
53
54 return ida_alloc_max(&lpi_ida, num_lpis - 1, GFP_KERNEL);
55}
56
57static void release_lpi(u32 lpi)
58{
59 ida_free(&lpi_ida, lpi);
60}
61
62static void gicv5_ppi_priority_init(void)
63{
64 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR0_EL1);
65 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR1_EL1);
66 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR2_EL1);
67 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR3_EL1);
68 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR4_EL1);
69 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR5_EL1);
70 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR6_EL1);
71 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR7_EL1);
72 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR8_EL1);
73 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR9_EL1);
74 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR10_EL1);
75 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR11_EL1);
76 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR12_EL1);
77 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR13_EL1);
78 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR14_EL1);
79 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR15_EL1);
80
81 /*
82 * Context syncronization required to make sure system register writes
83 * effects are synchronised.
84 */
85 isb();
86}
87
88static void gicv5_hwirq_init(irq_hw_number_t hwirq, u8 priority, u8 hwirq_type)
89{
90 u64 cdpri;
91
92 if (hwirq_type == GICV5_HWIRQ_TYPE_LPI || hwirq_type == GICV5_HWIRQ_TYPE_SPI) {
93 cdpri = FIELD_PREP(GICV5_GIC_CDPRI_PRIORITY_MASK, priority) |
94 FIELD_PREP(GICV5_GIC_CDPRI_TYPE_MASK, hwirq_type) |
95 FIELD_PREP(GICV5_GIC_CDPRI_ID_MASK, hwirq);
96 gic_insn(cdpri, CDPRI);
97 }
98}
99
100static void gicv5_ppi_irq_mask(struct irq_data *d)
101{
102 u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64);
103
104 if (d->hwirq < 64)
105 sysreg_clear_set_s(SYS_ICC_PPI_ENABLER0_EL1, hwirq_id_bit, 0);
106 else
107 sysreg_clear_set_s(SYS_ICC_PPI_ENABLER1_EL1, hwirq_id_bit, 0);
108
109 /*
110 * We must ensure that the disable takes effect immediately to
111 * guarantee that the lazy-disabled IRQ mechanism works.
112 * A context synchronization event is required to guarantee it.
113 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1.
114 */
115 isb();
116}
117
118static void gicv5_iri_irq_mask(struct irq_data *d, u8 hwirq_type)
119{
120 u64 cddis;
121
122 cddis = FIELD_PREP(GICV5_GIC_CDDIS_ID_MASK, d->hwirq) |
123 FIELD_PREP(GICV5_GIC_CDDIS_TYPE_MASK, hwirq_type);
124
125 gic_insn(cddis, CDDIS);
126 /*
127 * We must make sure that GIC CDDIS write effects are propagated
128 * immediately to make sure the disable takes effect to guarantee
129 * that the lazy-disabled IRQ mechanism works.
130 * Rule R_XCLJC states that the effects of a GIC system instruction
131 * complete in finite time.
132 * The GSB ensures completion of the GIC instruction and prevents
133 * loads, stores and GIC instructions from executing part of their
134 * functionality before the GSB SYS.
135 */
136 gsb_sys();
137}
138
139static void gicv5_spi_irq_mask(struct irq_data *d)
140{
141 gicv5_iri_irq_mask(d, GICV5_HWIRQ_TYPE_SPI);
142}
143
144static void gicv5_lpi_irq_mask(struct irq_data *d)
145{
146 gicv5_iri_irq_mask(d, GICV5_HWIRQ_TYPE_LPI);
147}
148
149static void gicv5_ppi_irq_unmask(struct irq_data *d)
150{
151 u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64);
152
153 if (d->hwirq < 64)
154 sysreg_clear_set_s(SYS_ICC_PPI_ENABLER0_EL1, 0, hwirq_id_bit);
155 else
156 sysreg_clear_set_s(SYS_ICC_PPI_ENABLER1_EL1, 0, hwirq_id_bit);
157 /*
158 * We must ensure that the enable takes effect in finite time - a
159 * context synchronization event is required to guarantee it, we
160 * can not take for granted that would happen (eg a core going straight
161 * into idle after enabling a PPI).
162 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1.
163 */
164 isb();
165}
166
167static void gicv5_iri_irq_unmask(struct irq_data *d, u8 hwirq_type)
168{
169 u64 cden;
170
171 cden = FIELD_PREP(GICV5_GIC_CDEN_ID_MASK, d->hwirq) |
172 FIELD_PREP(GICV5_GIC_CDEN_TYPE_MASK, hwirq_type);
173 /*
174 * Rule R_XCLJC states that the effects of a GIC system instruction
175 * complete in finite time and that's the only requirement when
176 * unmasking an SPI/LPI IRQ.
177 */
178 gic_insn(cden, CDEN);
179}
180
181static void gicv5_spi_irq_unmask(struct irq_data *d)
182{
183 gicv5_iri_irq_unmask(d, GICV5_HWIRQ_TYPE_SPI);
184}
185
186static void gicv5_lpi_irq_unmask(struct irq_data *d)
187{
188 gicv5_iri_irq_unmask(d, GICV5_HWIRQ_TYPE_LPI);
189}
190
191static void gicv5_hwirq_eoi(u32 hwirq_id, u8 hwirq_type)
192{
193 u64 cddi;
194
195 cddi = FIELD_PREP(GICV5_GIC_CDDI_ID_MASK, hwirq_id) |
196 FIELD_PREP(GICV5_GIC_CDDI_TYPE_MASK, hwirq_type);
197
198 gic_insn(cddi, CDDI);
199}
200
201static void gicv5_ppi_irq_eoi(struct irq_data *d)
202{
203 /* Skip deactivate for forwarded PPI interrupts */
204 if (irqd_is_forwarded_to_vcpu(d))
205 return;
206
207 gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_PPI);
208}
209
210static void gicv5_spi_irq_eoi(struct irq_data *d)
211{
212 gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_SPI);
213}
214
215static void gicv5_lpi_irq_eoi(struct irq_data *d)
216{
217 gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_LPI);
218}
219
220static int gicv5_iri_irq_set_affinity(struct irq_data *d,
221 const struct cpumask *mask_val,
222 bool force, u8 hwirq_type)
223{
224 int ret, cpuid;
225 u16 iaffid;
226 u64 cdaff;
227
228 if (force)
229 cpuid = cpumask_first(mask_val);
230 else
231 cpuid = cpumask_any_and(mask_val, cpu_online_mask);
232
233 ret = gicv5_irs_cpu_to_iaffid(cpuid, &iaffid);
234 if (ret)
235 return ret;
236
237 cdaff = FIELD_PREP(GICV5_GIC_CDAFF_IAFFID_MASK, iaffid) |
238 FIELD_PREP(GICV5_GIC_CDAFF_TYPE_MASK, hwirq_type) |
239 FIELD_PREP(GICV5_GIC_CDAFF_ID_MASK, d->hwirq);
240 gic_insn(cdaff, CDAFF);
241
242 irq_data_update_effective_affinity(d, cpumask_of(cpuid));
243
244 return IRQ_SET_MASK_OK_DONE;
245}
246
247static int gicv5_spi_irq_set_affinity(struct irq_data *d,
248 const struct cpumask *mask_val,
249 bool force)
250{
251 return gicv5_iri_irq_set_affinity(d, mask_val, force,
252 GICV5_HWIRQ_TYPE_SPI);
253}
254
255static int gicv5_lpi_irq_set_affinity(struct irq_data *d,
256 const struct cpumask *mask_val,
257 bool force)
258{
259 return gicv5_iri_irq_set_affinity(d, mask_val, force,
260 GICV5_HWIRQ_TYPE_LPI);
261}
262
263enum ppi_reg {
264 PPI_PENDING,
265 PPI_ACTIVE,
266 PPI_HM
267};
268
269static __always_inline u64 read_ppi_sysreg_s(unsigned int irq,
270 const enum ppi_reg which)
271{
272 switch (which) {
273 case PPI_PENDING:
274 return irq < 64 ? read_sysreg_s(SYS_ICC_PPI_SPENDR0_EL1) :
275 read_sysreg_s(SYS_ICC_PPI_SPENDR1_EL1);
276 case PPI_ACTIVE:
277 return irq < 64 ? read_sysreg_s(SYS_ICC_PPI_SACTIVER0_EL1) :
278 read_sysreg_s(SYS_ICC_PPI_SACTIVER1_EL1);
279 case PPI_HM:
280 return irq < 64 ? read_sysreg_s(SYS_ICC_PPI_HMR0_EL1) :
281 read_sysreg_s(SYS_ICC_PPI_HMR1_EL1);
282 default:
283 BUILD_BUG_ON(1);
284 }
285}
286
287static __always_inline void write_ppi_sysreg_s(unsigned int irq, bool set,
288 const enum ppi_reg which)
289{
290 u64 bit = BIT_ULL(irq % 64);
291
292 switch (which) {
293 case PPI_PENDING:
294 if (set) {
295 if (irq < 64)
296 write_sysreg_s(bit, SYS_ICC_PPI_SPENDR0_EL1);
297 else
298 write_sysreg_s(bit, SYS_ICC_PPI_SPENDR1_EL1);
299 } else {
300 if (irq < 64)
301 write_sysreg_s(bit, SYS_ICC_PPI_CPENDR0_EL1);
302 else
303 write_sysreg_s(bit, SYS_ICC_PPI_CPENDR1_EL1);
304 }
305 return;
306 case PPI_ACTIVE:
307 if (set) {
308 if (irq < 64)
309 write_sysreg_s(bit, SYS_ICC_PPI_SACTIVER0_EL1);
310 else
311 write_sysreg_s(bit, SYS_ICC_PPI_SACTIVER1_EL1);
312 } else {
313 if (irq < 64)
314 write_sysreg_s(bit, SYS_ICC_PPI_CACTIVER0_EL1);
315 else
316 write_sysreg_s(bit, SYS_ICC_PPI_CACTIVER1_EL1);
317 }
318 return;
319 default:
320 BUILD_BUG_ON(1);
321 }
322}
323
324static int gicv5_ppi_irq_get_irqchip_state(struct irq_data *d,
325 enum irqchip_irq_state which,
326 bool *state)
327{
328 u64 hwirq_id_bit = BIT_ULL(d->hwirq % 64);
329
330 switch (which) {
331 case IRQCHIP_STATE_PENDING:
332 *state = !!(read_ppi_sysreg_s(d->hwirq, PPI_PENDING) & hwirq_id_bit);
333 return 0;
334 case IRQCHIP_STATE_ACTIVE:
335 *state = !!(read_ppi_sysreg_s(d->hwirq, PPI_ACTIVE) & hwirq_id_bit);
336 return 0;
337 default:
338 pr_debug("Unexpected PPI irqchip state\n");
339 return -EINVAL;
340 }
341}
342
343static int gicv5_iri_irq_get_irqchip_state(struct irq_data *d,
344 enum irqchip_irq_state which,
345 bool *state, u8 hwirq_type)
346{
347 u64 icsr, cdrcfg;
348
349 cdrcfg = d->hwirq | FIELD_PREP(GICV5_GIC_CDRCFG_TYPE_MASK, hwirq_type);
350
351 gic_insn(cdrcfg, CDRCFG);
352 isb();
353 icsr = read_sysreg_s(SYS_ICC_ICSR_EL1);
354
355 if (FIELD_GET(ICC_ICSR_EL1_F, icsr)) {
356 pr_err("ICSR_EL1 is invalid\n");
357 return -EINVAL;
358 }
359
360 switch (which) {
361 case IRQCHIP_STATE_PENDING:
362 *state = !!(FIELD_GET(ICC_ICSR_EL1_Pending, icsr));
363 return 0;
364
365 case IRQCHIP_STATE_ACTIVE:
366 *state = !!(FIELD_GET(ICC_ICSR_EL1_Active, icsr));
367 return 0;
368
369 default:
370 pr_debug("Unexpected irqchip_irq_state\n");
371 return -EINVAL;
372 }
373}
374
375static int gicv5_spi_irq_get_irqchip_state(struct irq_data *d,
376 enum irqchip_irq_state which,
377 bool *state)
378{
379 return gicv5_iri_irq_get_irqchip_state(d, which, state,
380 GICV5_HWIRQ_TYPE_SPI);
381}
382
383static int gicv5_lpi_irq_get_irqchip_state(struct irq_data *d,
384 enum irqchip_irq_state which,
385 bool *state)
386{
387 return gicv5_iri_irq_get_irqchip_state(d, which, state,
388 GICV5_HWIRQ_TYPE_LPI);
389}
390
391static int gicv5_ppi_irq_set_irqchip_state(struct irq_data *d,
392 enum irqchip_irq_state which,
393 bool state)
394{
395 switch (which) {
396 case IRQCHIP_STATE_PENDING:
397 write_ppi_sysreg_s(d->hwirq, state, PPI_PENDING);
398 return 0;
399 case IRQCHIP_STATE_ACTIVE:
400 write_ppi_sysreg_s(d->hwirq, state, PPI_ACTIVE);
401 return 0;
402 default:
403 pr_debug("Unexpected PPI irqchip state\n");
404 return -EINVAL;
405 }
406}
407
408static void gicv5_iri_irq_write_pending_state(struct irq_data *d, bool state,
409 u8 hwirq_type)
410{
411 u64 cdpend;
412
413 cdpend = FIELD_PREP(GICV5_GIC_CDPEND_TYPE_MASK, hwirq_type) |
414 FIELD_PREP(GICV5_GIC_CDPEND_ID_MASK, d->hwirq) |
415 FIELD_PREP(GICV5_GIC_CDPEND_PENDING_MASK, state);
416
417 gic_insn(cdpend, CDPEND);
418}
419
420static void gicv5_spi_irq_write_pending_state(struct irq_data *d, bool state)
421{
422 gicv5_iri_irq_write_pending_state(d, state, GICV5_HWIRQ_TYPE_SPI);
423}
424
425static void gicv5_lpi_irq_write_pending_state(struct irq_data *d, bool state)
426{
427 gicv5_iri_irq_write_pending_state(d, state, GICV5_HWIRQ_TYPE_LPI);
428}
429
430static int gicv5_spi_irq_set_irqchip_state(struct irq_data *d,
431 enum irqchip_irq_state which,
432 bool state)
433{
434 switch (which) {
435 case IRQCHIP_STATE_PENDING:
436 gicv5_spi_irq_write_pending_state(d, state);
437 break;
438 default:
439 pr_debug("Unexpected irqchip_irq_state\n");
440 return -EINVAL;
441 }
442
443 return 0;
444}
445
446static int gicv5_lpi_irq_set_irqchip_state(struct irq_data *d,
447 enum irqchip_irq_state which,
448 bool state)
449{
450 switch (which) {
451 case IRQCHIP_STATE_PENDING:
452 gicv5_lpi_irq_write_pending_state(d, state);
453 break;
454
455 default:
456 pr_debug("Unexpected irqchip_irq_state\n");
457 return -EINVAL;
458 }
459
460 return 0;
461}
462
463static int gicv5_spi_irq_retrigger(struct irq_data *data)
464{
465 return !gicv5_spi_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING,
466 true);
467}
468
469static int gicv5_lpi_irq_retrigger(struct irq_data *data)
470{
471 return !gicv5_lpi_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING,
472 true);
473}
474
475static void gicv5_ipi_send_single(struct irq_data *d, unsigned int cpu)
476{
477 /* Mark the LPI pending */
478 irq_chip_retrigger_hierarchy(d);
479}
480
481static bool gicv5_ppi_irq_is_level(irq_hw_number_t hwirq)
482{
483 u64 bit = BIT_ULL(hwirq % 64);
484
485 return !!(read_ppi_sysreg_s(hwirq, PPI_HM) & bit);
486}
487
488static int gicv5_ppi_irq_set_type(struct irq_data *d, unsigned int type)
489{
490 /*
491 * GICv5's PPIs do not have a configurable trigger or handling
492 * mode. Check that the attempt to set a type matches what the
493 * hardware reports in the HMR, and error on a mismatch.
494 */
495
496 if (type & IRQ_TYPE_EDGE_BOTH && gicv5_ppi_irq_is_level(d->hwirq))
497 return -EINVAL;
498
499 if (type & IRQ_TYPE_LEVEL_MASK && !gicv5_ppi_irq_is_level(d->hwirq))
500 return -EINVAL;
501
502 return 0;
503}
504
505static int gicv5_ppi_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
506{
507 if (vcpu)
508 irqd_set_forwarded_to_vcpu(d);
509 else
510 irqd_clr_forwarded_to_vcpu(d);
511
512 return 0;
513}
514
515static const struct irq_chip gicv5_ppi_irq_chip = {
516 .name = "GICv5-PPI",
517 .irq_mask = gicv5_ppi_irq_mask,
518 .irq_unmask = gicv5_ppi_irq_unmask,
519 .irq_eoi = gicv5_ppi_irq_eoi,
520 .irq_set_type = gicv5_ppi_irq_set_type,
521 .irq_get_irqchip_state = gicv5_ppi_irq_get_irqchip_state,
522 .irq_set_irqchip_state = gicv5_ppi_irq_set_irqchip_state,
523 .irq_set_vcpu_affinity = gicv5_ppi_irq_set_vcpu_affinity,
524 .flags = IRQCHIP_SKIP_SET_WAKE |
525 IRQCHIP_MASK_ON_SUSPEND,
526};
527
528static const struct irq_chip gicv5_spi_irq_chip = {
529 .name = "GICv5-SPI",
530 .irq_mask = gicv5_spi_irq_mask,
531 .irq_unmask = gicv5_spi_irq_unmask,
532 .irq_eoi = gicv5_spi_irq_eoi,
533 .irq_set_type = gicv5_spi_irq_set_type,
534 .irq_set_affinity = gicv5_spi_irq_set_affinity,
535 .irq_retrigger = gicv5_spi_irq_retrigger,
536 .irq_get_irqchip_state = gicv5_spi_irq_get_irqchip_state,
537 .irq_set_irqchip_state = gicv5_spi_irq_set_irqchip_state,
538 .flags = IRQCHIP_SET_TYPE_MASKED |
539 IRQCHIP_AFFINITY_PRE_STARTUP |
540 IRQCHIP_SKIP_SET_WAKE |
541 IRQCHIP_MASK_ON_SUSPEND,
542};
543
544static const struct irq_chip gicv5_lpi_irq_chip = {
545 .name = "GICv5-LPI",
546 .irq_mask = gicv5_lpi_irq_mask,
547 .irq_unmask = gicv5_lpi_irq_unmask,
548 .irq_eoi = gicv5_lpi_irq_eoi,
549 .irq_set_affinity = gicv5_lpi_irq_set_affinity,
550 .irq_retrigger = gicv5_lpi_irq_retrigger,
551 .irq_get_irqchip_state = gicv5_lpi_irq_get_irqchip_state,
552 .irq_set_irqchip_state = gicv5_lpi_irq_set_irqchip_state,
553 .flags = IRQCHIP_AFFINITY_PRE_STARTUP |
554 IRQCHIP_SKIP_SET_WAKE |
555 IRQCHIP_MASK_ON_SUSPEND,
556};
557
558static const struct irq_chip gicv5_ipi_irq_chip = {
559 .name = "GICv5-IPI",
560 .irq_mask = irq_chip_mask_parent,
561 .irq_unmask = irq_chip_unmask_parent,
562 .irq_eoi = irq_chip_eoi_parent,
563 .irq_set_affinity = irq_chip_set_affinity_parent,
564 .irq_get_irqchip_state = irq_chip_get_parent_state,
565 .irq_set_irqchip_state = irq_chip_set_parent_state,
566 .ipi_send_single = gicv5_ipi_send_single,
567 .flags = IRQCHIP_SKIP_SET_WAKE |
568 IRQCHIP_MASK_ON_SUSPEND,
569};
570
571static __always_inline int gicv5_irq_domain_translate(struct irq_domain *d,
572 struct irq_fwspec *fwspec,
573 irq_hw_number_t *hwirq,
574 unsigned int *type,
575 const u8 hwirq_type)
576{
577 unsigned int hwirq_trigger;
578 u8 fwspec_irq_type;
579
580 if (is_of_node(fwspec->fwnode)) {
581
582 if (fwspec->param_count < 3)
583 return -EINVAL;
584
585 fwspec_irq_type = fwspec->param[0];
586
587 if (fwspec->param[0] != hwirq_type)
588 return -EINVAL;
589
590 *hwirq = fwspec->param[1];
591 hwirq_trigger = fwspec->param[2];
592 }
593
594 if (is_fwnode_irqchip(fwspec->fwnode)) {
595
596 if (fwspec->param_count != 2)
597 return -EINVAL;
598
599 fwspec_irq_type = FIELD_GET(GICV5_HWIRQ_TYPE, fwspec->param[0]);
600
601 if (fwspec_irq_type != hwirq_type)
602 return -EINVAL;
603
604 *hwirq = FIELD_GET(GICV5_HWIRQ_ID, fwspec->param[0]);
605 hwirq_trigger = fwspec->param[1];
606 }
607
608 switch (hwirq_type) {
609 case GICV5_HWIRQ_TYPE_PPI:
610 /*
611 * Handling mode is hardcoded for PPIs, set the type using
612 * HW reported value.
613 */
614 *type = gicv5_ppi_irq_is_level(*hwirq) ? IRQ_TYPE_LEVEL_LOW :
615 IRQ_TYPE_EDGE_RISING;
616 break;
617 case GICV5_HWIRQ_TYPE_SPI:
618 *type = hwirq_trigger & IRQ_TYPE_SENSE_MASK;
619 break;
620 default:
621 BUILD_BUG_ON(1);
622 }
623
624 return 0;
625}
626
627static int gicv5_irq_ppi_domain_translate(struct irq_domain *d,
628 struct irq_fwspec *fwspec,
629 irq_hw_number_t *hwirq,
630 unsigned int *type)
631{
632 return gicv5_irq_domain_translate(d, fwspec, hwirq, type,
633 GICV5_HWIRQ_TYPE_PPI);
634}
635
636static int gicv5_irq_ppi_domain_alloc(struct irq_domain *domain, unsigned int virq,
637 unsigned int nr_irqs, void *arg)
638{
639 unsigned int type = IRQ_TYPE_NONE;
640 struct irq_fwspec *fwspec = arg;
641 irq_hw_number_t hwirq;
642 int ret;
643
644 if (WARN_ON_ONCE(nr_irqs != 1))
645 return -EINVAL;
646
647 ret = gicv5_irq_ppi_domain_translate(domain, fwspec, &hwirq, &type);
648 if (ret)
649 return ret;
650
651 if (type & IRQ_TYPE_LEVEL_MASK)
652 irq_set_status_flags(virq, IRQ_LEVEL);
653
654 irq_set_percpu_devid(virq);
655 irq_domain_set_info(domain, virq, hwirq, &gicv5_ppi_irq_chip, NULL,
656 handle_percpu_devid_irq, NULL, NULL);
657
658 return 0;
659}
660
661static void gicv5_irq_domain_free(struct irq_domain *domain, unsigned int virq,
662 unsigned int nr_irqs)
663{
664 struct irq_data *d;
665
666 if (WARN_ON_ONCE(nr_irqs != 1))
667 return;
668
669 d = irq_domain_get_irq_data(domain, virq);
670
671 irq_set_handler(virq, NULL);
672 irq_domain_reset_irq_data(d);
673}
674
675static int gicv5_irq_ppi_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec,
676 enum irq_domain_bus_token bus_token)
677{
678 u32 hwirq_type;
679
680 if (fwspec->fwnode != d->fwnode)
681 return 0;
682
683 if (is_of_node(fwspec->fwnode))
684 hwirq_type = fwspec->param[0];
685
686 if (is_fwnode_irqchip(fwspec->fwnode))
687 hwirq_type = FIELD_GET(GICV5_HWIRQ_TYPE, fwspec->param[0]);
688
689 if (hwirq_type != GICV5_HWIRQ_TYPE_PPI)
690 return 0;
691
692 return (d == gicv5_global_data.ppi_domain);
693}
694
695static const struct irq_domain_ops gicv5_irq_ppi_domain_ops = {
696 .translate = gicv5_irq_ppi_domain_translate,
697 .alloc = gicv5_irq_ppi_domain_alloc,
698 .free = gicv5_irq_domain_free,
699 .select = gicv5_irq_ppi_domain_select
700};
701
702static int gicv5_irq_spi_domain_translate(struct irq_domain *d,
703 struct irq_fwspec *fwspec,
704 irq_hw_number_t *hwirq,
705 unsigned int *type)
706{
707 return gicv5_irq_domain_translate(d, fwspec, hwirq, type,
708 GICV5_HWIRQ_TYPE_SPI);
709}
710
711static int gicv5_irq_spi_domain_alloc(struct irq_domain *domain, unsigned int virq,
712 unsigned int nr_irqs, void *arg)
713{
714 struct gicv5_irs_chip_data *chip_data;
715 unsigned int type = IRQ_TYPE_NONE;
716 struct irq_fwspec *fwspec = arg;
717 struct irq_data *irqd;
718 irq_hw_number_t hwirq;
719 int ret;
720
721 if (WARN_ON_ONCE(nr_irqs != 1))
722 return -EINVAL;
723
724 ret = gicv5_irq_spi_domain_translate(domain, fwspec, &hwirq, &type);
725 if (ret)
726 return ret;
727
728 irqd = irq_desc_get_irq_data(irq_to_desc(virq));
729 chip_data = gicv5_irs_lookup_by_spi_id(hwirq);
730
731 irq_domain_set_info(domain, virq, hwirq, &gicv5_spi_irq_chip, chip_data,
732 handle_fasteoi_irq, NULL, NULL);
733 irq_set_probe(virq);
734 irqd_set_single_target(irqd);
735
736 gicv5_hwirq_init(hwirq, GICV5_IRQ_PRI_MI, GICV5_HWIRQ_TYPE_SPI);
737
738 return 0;
739}
740
741static int gicv5_irq_spi_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec,
742 enum irq_domain_bus_token bus_token)
743{
744 u32 hwirq_type;
745
746 if (fwspec->fwnode != d->fwnode)
747 return 0;
748
749 if (is_of_node(fwspec->fwnode))
750 hwirq_type = fwspec->param[0];
751
752 if (is_fwnode_irqchip(fwspec->fwnode))
753 hwirq_type = FIELD_GET(GICV5_HWIRQ_TYPE, fwspec->param[0]);
754
755 if (hwirq_type != GICV5_HWIRQ_TYPE_SPI)
756 return 0;
757
758 return (d == gicv5_global_data.spi_domain);
759}
760
761static const struct irq_domain_ops gicv5_irq_spi_domain_ops = {
762 .translate = gicv5_irq_spi_domain_translate,
763 .alloc = gicv5_irq_spi_domain_alloc,
764 .free = gicv5_irq_domain_free,
765 .select = gicv5_irq_spi_domain_select
766};
767
768static void gicv5_lpi_config_reset(struct irq_data *d)
769{
770 u64 cdhm;
771
772 /*
773 * Reset LPIs handling mode to edge by default and clear pending
774 * state to make sure we start the LPI with a clean state from
775 * previous incarnations.
776 */
777 cdhm = FIELD_PREP(GICV5_GIC_CDHM_HM_MASK, 0) |
778 FIELD_PREP(GICV5_GIC_CDHM_TYPE_MASK, GICV5_HWIRQ_TYPE_LPI) |
779 FIELD_PREP(GICV5_GIC_CDHM_ID_MASK, d->hwirq);
780 gic_insn(cdhm, CDHM);
781
782 gicv5_lpi_irq_write_pending_state(d, false);
783}
784
785static void gicv5_irq_lpi_domain_free(struct irq_domain *domain, unsigned int virq,
786 unsigned int nr_irqs)
787{
788 struct irq_data *d;
789
790 for (unsigned int i = 0; i < nr_irqs; i++, virq++) {
791 d = irq_domain_get_irq_data(domain, virq);
792
793 release_lpi(d->hwirq);
794
795 irq_set_handler(virq, NULL);
796 irq_domain_reset_irq_data(d);
797 }
798}
799
800static int gicv5_irq_lpi_domain_alloc(struct irq_domain *domain, unsigned int virq,
801 unsigned int nr_irqs, void *arg)
802{
803 irq_hw_number_t hwirq;
804 struct irq_data *irqd;
805 unsigned int i;
806 int ret;
807
808 for (i = 0; i < nr_irqs; i++) {
809 ret = alloc_lpi();
810 if (ret < 0)
811 goto out_free_lpis;
812 hwirq = ret;
813
814 ret = gicv5_irs_iste_alloc(hwirq);
815 if (ret < 0) {
816 /* Undo partial state first, then clean up the rest */
817 release_lpi(hwirq);
818 goto out_free_lpis;
819 }
820
821 irqd = irq_domain_get_irq_data(domain, virq + i);
822
823 irq_domain_set_info(domain, virq + i, hwirq, &gicv5_lpi_irq_chip,
824 NULL, handle_fasteoi_irq, NULL, NULL);
825 irqd_set_single_target(irqd);
826
827 gicv5_hwirq_init(hwirq, GICV5_IRQ_PRI_MI, GICV5_HWIRQ_TYPE_LPI);
828 gicv5_lpi_config_reset(irqd);
829 }
830
831 return 0;
832
833out_free_lpis:
834 if (i)
835 gicv5_irq_lpi_domain_free(domain, virq, i);
836
837 return ret;
838}
839
840static const struct irq_domain_ops gicv5_irq_lpi_domain_ops = {
841 .alloc = gicv5_irq_lpi_domain_alloc,
842 .free = gicv5_irq_lpi_domain_free,
843};
844
845void __init gicv5_init_lpi_domain(void)
846{
847 struct irq_domain *d;
848
849 d = irq_domain_create_tree(NULL, &gicv5_irq_lpi_domain_ops, NULL);
850 gicv5_global_data.lpi_domain = d;
851}
852
853void __init gicv5_free_lpi_domain(void)
854{
855 if (!gicv5_global_data.lpi_domain)
856 return;
857
858 irq_domain_remove(gicv5_global_data.lpi_domain);
859 gicv5_global_data.lpi_domain = NULL;
860}
861
862static int gicv5_irq_ipi_domain_alloc(struct irq_domain *domain, unsigned int virq,
863 unsigned int nr_irqs, void *arg)
864{
865 struct irq_data *irqd;
866 int ret;
867
868 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
869 if (ret)
870 return ret;
871
872 for (unsigned int i = 0; i < nr_irqs; i++, virq++) {
873 irqd = irq_domain_get_irq_data(domain, virq);
874
875 irq_domain_set_hwirq_and_chip(domain, virq, i,
876 &gicv5_ipi_irq_chip, NULL);
877
878 irqd_set_single_target(irqd);
879
880 irq_set_handler(virq, handle_percpu_irq);
881 }
882
883 return 0;
884}
885
886static void gicv5_irq_ipi_domain_free(struct irq_domain *domain, unsigned int virq,
887 unsigned int nr_irqs)
888{
889 struct irq_data *d;
890 unsigned int i;
891
892 for (i = 0; i < nr_irqs; i++) {
893 d = irq_domain_get_irq_data(domain, virq + i);
894
895 if (!d)
896 return;
897
898 irq_set_handler(virq + i, NULL);
899 irq_domain_reset_irq_data(d);
900 }
901
902 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
903}
904
905static const struct irq_domain_ops gicv5_irq_ipi_domain_ops = {
906 .alloc = gicv5_irq_ipi_domain_alloc,
907 .free = gicv5_irq_ipi_domain_free,
908};
909
910static void handle_irq_per_domain(u32 hwirq)
911{
912 u8 hwirq_type = FIELD_GET(GICV5_HWIRQ_TYPE, hwirq);
913 u32 hwirq_id = FIELD_GET(GICV5_HWIRQ_ID, hwirq);
914 struct irq_domain *domain;
915
916 switch (hwirq_type) {
917 case GICV5_HWIRQ_TYPE_PPI:
918 domain = gicv5_global_data.ppi_domain;
919 break;
920 case GICV5_HWIRQ_TYPE_SPI:
921 domain = gicv5_global_data.spi_domain;
922 break;
923 case GICV5_HWIRQ_TYPE_LPI:
924 domain = gicv5_global_data.lpi_domain;
925 break;
926 default:
927 pr_err_once("Unknown IRQ type, bail out\n");
928 return;
929 }
930
931 if (generic_handle_domain_irq(domain, hwirq_id)) {
932 pr_err_once("Could not handle, hwirq = 0x%x", hwirq_id);
933 gicv5_hwirq_eoi(hwirq_id, hwirq_type);
934 }
935}
936
937static void __exception_irq_entry gicv5_handle_irq(struct pt_regs *regs)
938{
939 bool valid;
940 u32 hwirq;
941 u64 ia;
942
943 ia = gicr_insn(CDIA);
944 valid = GICV5_GICR_CDIA_VALID(ia);
945
946 if (!valid)
947 return;
948
949 /*
950 * Ensure that the CDIA instruction effects (ie IRQ activation) are
951 * completed before handling the interrupt.
952 */
953 gsb_ack();
954
955 /*
956 * Ensure instruction ordering between an acknowledgment and subsequent
957 * instructions in the IRQ handler using an ISB.
958 */
959 isb();
960
961 /*
962 * Ensure that we can receive the next interrupts in the event that we
963 * have a long running handler or directly enter a guest by doing the
964 * priority drop immediately.
965 */
966 gic_insn(0, CDEOI);
967
968 hwirq = FIELD_GET(GICV5_HWIRQ_INTID, ia);
969
970 handle_irq_per_domain(hwirq);
971}
972
973static void gicv5_cpu_disable_interrupts(void)
974{
975 u64 cr0;
976
977 cr0 = read_sysreg_s(SYS_ICC_CR0_EL1);
978 cr0 &= ~ICC_CR0_EL1_EN_MASK;
979 write_sysreg_s(cr0, SYS_ICC_CR0_EL1);
980 isb();
981}
982
983static void gicv5_cpu_enable_interrupts(void)
984{
985 u64 cr0, pcr;
986
987 write_sysreg_s(0, SYS_ICC_PPI_ENABLER0_EL1);
988 write_sysreg_s(0, SYS_ICC_PPI_ENABLER1_EL1);
989
990 gicv5_ppi_priority_init();
991
992 pcr = FIELD_PREP(ICC_PCR_EL1_PRIORITY, GICV5_IRQ_PRI_MI);
993 write_sysreg_s(pcr, SYS_ICC_PCR_EL1);
994
995 cr0 = read_sysreg_s(SYS_ICC_CR0_EL1);
996 cr0 |= ICC_CR0_EL1_EN_MASK;
997 write_sysreg_s(cr0, SYS_ICC_CR0_EL1);
998}
999
1000static int base_ipi_virq;
1001
1002static int gicv5_starting_cpu(unsigned int cpu)
1003{
1004 if (WARN(!gicv5_cpuif_has_gcie(),
1005 "GICv5 system components present but CPU does not have FEAT_GCIE"))
1006 return -ENODEV;
1007
1008 gicv5_cpu_enable_interrupts();
1009
1010 return gicv5_irs_register_cpu(cpu);
1011}
1012
1013static void __init gicv5_smp_init(void)
1014{
1015 unsigned int num_ipis = GICV5_IPIS_PER_CPU * nr_cpu_ids;
1016
1017 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1018 "irqchip/arm/gicv5:starting",
1019 gicv5_starting_cpu, NULL);
1020
1021 base_ipi_virq = irq_domain_alloc_irqs(gicv5_global_data.ipi_domain,
1022 num_ipis, NUMA_NO_NODE, NULL);
1023 if (WARN(base_ipi_virq <= 0, "IPI IRQ allocation was not successful"))
1024 return;
1025
1026 set_smp_ipi_range_percpu(base_ipi_virq, GICV5_IPIS_PER_CPU, nr_cpu_ids);
1027}
1028
1029static void __init gicv5_free_domains(void)
1030{
1031 if (gicv5_global_data.ppi_domain)
1032 irq_domain_remove(gicv5_global_data.ppi_domain);
1033 if (gicv5_global_data.spi_domain)
1034 irq_domain_remove(gicv5_global_data.spi_domain);
1035 if (gicv5_global_data.ipi_domain)
1036 irq_domain_remove(gicv5_global_data.ipi_domain);
1037
1038 gicv5_global_data.ppi_domain = NULL;
1039 gicv5_global_data.spi_domain = NULL;
1040 gicv5_global_data.ipi_domain = NULL;
1041}
1042
1043static int __init gicv5_init_domains(struct fwnode_handle *handle)
1044{
1045 u32 spi_count = gicv5_global_data.global_spi_count;
1046 struct irq_domain *d;
1047
1048 d = irq_domain_create_linear(handle, PPI_NR, &gicv5_irq_ppi_domain_ops, NULL);
1049 if (!d)
1050 return -ENOMEM;
1051
1052 irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED);
1053 gicv5_global_data.ppi_domain = d;
1054
1055 if (spi_count) {
1056 d = irq_domain_create_linear(handle, spi_count,
1057 &gicv5_irq_spi_domain_ops, NULL);
1058
1059 if (!d) {
1060 gicv5_free_domains();
1061 return -ENOMEM;
1062 }
1063
1064 gicv5_global_data.spi_domain = d;
1065 irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED);
1066 }
1067
1068 if (!WARN(!gicv5_global_data.lpi_domain,
1069 "LPI domain uninitialized, can't set up IPIs")) {
1070 d = irq_domain_create_hierarchy(gicv5_global_data.lpi_domain,
1071 0, GICV5_IPIS_PER_CPU * nr_cpu_ids,
1072 NULL, &gicv5_irq_ipi_domain_ops,
1073 NULL);
1074
1075 if (!d) {
1076 gicv5_free_domains();
1077 return -ENOMEM;
1078 }
1079 gicv5_global_data.ipi_domain = d;
1080 }
1081 gicv5_global_data.fwnode = handle;
1082
1083 return 0;
1084}
1085
1086static void gicv5_set_cpuif_pribits(void)
1087{
1088 u64 icc_idr0 = read_sysreg_s(SYS_ICC_IDR0_EL1);
1089
1090 switch (FIELD_GET(ICC_IDR0_EL1_PRI_BITS, icc_idr0)) {
1091 case ICC_IDR0_EL1_PRI_BITS_4BITS:
1092 gicv5_global_data.cpuif_pri_bits = 4;
1093 break;
1094 case ICC_IDR0_EL1_PRI_BITS_5BITS:
1095 gicv5_global_data.cpuif_pri_bits = 5;
1096 break;
1097 default:
1098 pr_err("Unexpected ICC_IDR0_EL1_PRI_BITS value, default to 4");
1099 gicv5_global_data.cpuif_pri_bits = 4;
1100 break;
1101 }
1102}
1103
1104static void gicv5_set_cpuif_idbits(void)
1105{
1106 u32 icc_idr0 = read_sysreg_s(SYS_ICC_IDR0_EL1);
1107
1108 switch (FIELD_GET(ICC_IDR0_EL1_ID_BITS, icc_idr0)) {
1109 case ICC_IDR0_EL1_ID_BITS_16BITS:
1110 gicv5_global_data.cpuif_id_bits = 16;
1111 break;
1112 case ICC_IDR0_EL1_ID_BITS_24BITS:
1113 gicv5_global_data.cpuif_id_bits = 24;
1114 break;
1115 default:
1116 pr_err("Unexpected ICC_IDR0_EL1_ID_BITS value, default to 16");
1117 gicv5_global_data.cpuif_id_bits = 16;
1118 break;
1119 }
1120}
1121
1122#ifdef CONFIG_KVM
1123static struct gic_kvm_info gic_v5_kvm_info __initdata;
1124
1125static void __init gic_of_setup_kvm_info(struct device_node *node)
1126{
1127 /*
1128 * If we don't have native GICv5 virtualisation support, then
1129 * we also don't have FEAT_GCIE_LEGACY - the architecture
1130 * forbids this combination.
1131 */
1132 if (!gicv5_global_data.virt_capable) {
1133 pr_info("GIC implementation is not virtualization capable\n");
1134 return;
1135 }
1136
1137 gic_v5_kvm_info.type = GIC_V5;
1138
1139 /* GIC Virtual CPU interface maintenance interrupt */
1140 gic_v5_kvm_info.no_maint_irq_mask = false;
1141 gic_v5_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1142 if (!gic_v5_kvm_info.maint_irq) {
1143 pr_warn("cannot find GICv5 virtual CPU interface maintenance interrupt\n");
1144 return;
1145 }
1146
1147 vgic_set_kvm_info(&gic_v5_kvm_info);
1148}
1149#else
1150static inline void __init gic_of_setup_kvm_info(struct device_node *node)
1151{
1152}
1153#endif // CONFIG_KVM
1154
1155static int __init gicv5_init_common(struct fwnode_handle *parent_domain)
1156{
1157 int ret = gicv5_init_domains(parent_domain);
1158 if (ret)
1159 return ret;
1160
1161 gicv5_set_cpuif_pribits();
1162 gicv5_set_cpuif_idbits();
1163
1164 pri_bits = min_not_zero(gicv5_global_data.cpuif_pri_bits,
1165 gicv5_global_data.irs_pri_bits);
1166
1167 ret = gicv5_starting_cpu(smp_processor_id());
1168 if (ret)
1169 goto out_int;
1170
1171 ret = set_handle_irq(gicv5_handle_irq);
1172 if (ret)
1173 goto out_int;
1174
1175 ret = gicv5_irs_enable();
1176 if (ret)
1177 goto out_handle;
1178
1179 gicv5_smp_init();
1180
1181 gicv5_irs_its_probe();
1182 return 0;
1183
1184out_handle:
1185 set_handle_irq(NULL);
1186out_int:
1187 gicv5_cpu_disable_interrupts();
1188 gicv5_free_domains();
1189 return ret;
1190}
1191
1192static int __init gicv5_of_init(struct device_node *node, struct device_node *parent)
1193{
1194 int ret = gicv5_irs_of_probe(node);
1195 if (ret)
1196 return ret;
1197
1198 ret = gicv5_init_common(of_fwnode_handle(node));
1199 if (ret)
1200 goto out_irs;
1201
1202 gic_of_setup_kvm_info(node);
1203
1204 return 0;
1205out_irs:
1206 gicv5_irs_remove();
1207
1208 return ret;
1209}
1210IRQCHIP_DECLARE(gic_v5, "arm,gic-v5", gicv5_of_init);
1211
1212#ifdef CONFIG_ACPI
1213static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
1214 struct acpi_probe_entry *ape)
1215{
1216 struct acpi_madt_gicv5_irs *irs = (struct acpi_madt_gicv5_irs *)header;
1217
1218 return (irs->version == ape->driver_data);
1219}
1220
1221static struct fwnode_handle *gsi_domain_handle;
1222
1223static struct fwnode_handle *gic_v5_get_gsi_domain_id(u32 gsi)
1224{
1225 if (FIELD_GET(GICV5_GSI_IC_TYPE, gsi) == GICV5_GSI_IWB_TYPE)
1226 return iort_iwb_handle_fwnode(FIELD_GET(GICV5_GSI_IWB_FRAME_ID, gsi));
1227
1228 return gsi_domain_handle;
1229}
1230
1231static acpi_handle gic_v5_get_gsi_handle(u32 gsi)
1232{
1233 if (FIELD_GET(GICV5_GSI_IC_TYPE, gsi) == GICV5_GSI_IWB_TYPE)
1234 return iort_iwb_handle(FIELD_GET(GICV5_GSI_IWB_FRAME_ID, gsi));
1235
1236 return NULL;
1237}
1238
1239static int __init gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
1240{
1241 struct acpi_madt_gicv5_irs *irs = (struct acpi_madt_gicv5_irs *)header;
1242 int ret;
1243
1244 if (gsi_domain_handle)
1245 return 0;
1246
1247 gsi_domain_handle = irq_domain_alloc_fwnode(&irs->config_base_address);
1248 if (!gsi_domain_handle)
1249 return -ENOMEM;
1250
1251 ret = gicv5_irs_acpi_probe();
1252 if (ret)
1253 goto out_fwnode;
1254
1255 ret = gicv5_init_common(gsi_domain_handle);
1256 if (ret)
1257 goto out_irs;
1258
1259 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC_V5, gic_v5_get_gsi_domain_id,
1260 gic_v5_get_gsi_handle);
1261
1262 return 0;
1263
1264out_irs:
1265 gicv5_irs_remove();
1266out_fwnode:
1267 irq_domain_free_fwnode(gsi_domain_handle);
1268 return ret;
1269}
1270IRQCHIP_ACPI_DECLARE(gic_v5, ACPI_MADT_TYPE_GICV5_IRS,
1271 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V5,
1272 gic_acpi_init);
1273#endif