| 1 | |
| 2 | * Xtensa built-in interrupt controller
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| 3 | *
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| 4 | * Copyright (C) 2002 - 2013 Tensilica, Inc.
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| 5 | * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
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| 6 | *
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| 7 | * This file is subject to the terms and conditions of the GNU General Public
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| 8 | * License. See the file "COPYING" in the main directory of this archive
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| 9 | * for more details.
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| 10 | *
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| 11 | * Chris Zankel <[email protected]>
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| 12 | * Kevin Chea
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| 13 |
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| 14 |
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| 15 | #include <linux/bits.h>
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| 16 | #include <linux/interrupt.h>
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| 17 | #include <linux/irqdomain.h>
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| 18 | #include <linux/irq.h>
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| 19 | #include <linux/irqchip.h>
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| 20 | #include <linux/irqchip/xtensa-pic.h>
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| 21 | #include <linux/of.h>
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| 22 |
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| 23 | |
| 24 | * Device Tree IRQ specifier translation function which works with one or
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| 25 | * two cell bindings. First cell value maps directly to the hwirq number.
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| 26 | * Second cell if present specifies whether hwirq number is external (1) or
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| 27 | * internal (0).
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| 28 |
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| 29 | static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
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| 30 | struct device_node *ctrlr,
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| 31 | const u32 *intspec, unsigned int intsize,
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| 32 | unsigned long *out_hwirq, unsigned int *out_type)
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| 33 | {
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| 34 | return xtensa_irq_domain_xlate(intspec, intsize,
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| 35 | intspec[0], intspec[0],
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| 36 | out_hwirq, out_type);
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| 37 | }
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| 38 |
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| 39 | static const struct irq_domain_ops xtensa_irq_domain_ops = {
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| 40 | .xlate = xtensa_pic_irq_domain_xlate,
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| 41 | .map = xtensa_irq_map,
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| 42 | };
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| 43 |
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| 44 | static void xtensa_irq_mask(struct irq_data *d)
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| 45 | {
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| 46 | u32 irq_mask;
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| 47 |
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| 48 | irq_mask = xtensa_get_sr(intenable);
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| 49 | irq_mask &= ~BIT(d->hwirq);
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| 50 | xtensa_set_sr(irq_mask, intenable);
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| 51 | }
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| 52 |
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| 53 | static void xtensa_irq_unmask(struct irq_data *d)
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| 54 | {
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| 55 | u32 irq_mask;
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| 56 |
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| 57 | irq_mask = xtensa_get_sr(intenable);
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| 58 | irq_mask |= BIT(d->hwirq);
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| 59 | xtensa_set_sr(irq_mask, intenable);
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| 60 | }
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| 61 |
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| 62 | static void xtensa_irq_ack(struct irq_data *d)
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| 63 | {
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| 64 | xtensa_set_sr(BIT(d->hwirq), intclear);
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| 65 | }
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| 66 |
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| 67 | static int xtensa_irq_retrigger(struct irq_data *d)
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| 68 | {
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| 69 | unsigned int mask = BIT(d->hwirq);
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| 70 |
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| 71 | if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
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| 72 | return 0;
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| 73 | xtensa_set_sr(mask, intset);
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| 74 | return 1;
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| 75 | }
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| 76 |
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| 77 | static struct irq_chip xtensa_irq_chip = {
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| 78 | .name = "xtensa",
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| 79 | .irq_mask = xtensa_irq_mask,
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| 80 | .irq_unmask = xtensa_irq_unmask,
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| 81 | .irq_ack = xtensa_irq_ack,
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| 82 | .irq_retrigger = xtensa_irq_retrigger,
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| 83 | };
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| 84 |
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| 85 | int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
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| 86 | {
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| 87 | struct irq_domain *root_domain =
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| 88 | irq_domain_create_legacy(NULL, NR_IRQS - 1, 1, 0,
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| 89 | &xtensa_irq_domain_ops, &xtensa_irq_chip);
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| 90 | irq_set_default_domain(root_domain);
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| 91 | return 0;
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| 92 | }
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| 93 |
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| 94 | static int __init xtensa_pic_init(struct device_node *np,
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| 95 | struct device_node *interrupt_parent)
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| 96 | {
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| 97 | struct irq_domain *root_domain =
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| 98 | irq_domain_create_linear(of_fwnode_handle(np), NR_IRQS, &xtensa_irq_domain_ops,
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| 99 | &xtensa_irq_chip);
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| 100 | irq_set_default_domain(root_domain);
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| 101 | return 0;
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| 102 | }
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| 103 | IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);
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