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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
4 *
5 * Copyright (C) 2009 Devin Heitmueller <[email protected]>
6 * Copyright (C) 2005-2008 Auvitek International, Ltd.
7 */
8
9/* Developer notes:
10 *
11 * Enough is implemented here for CVBS and S-Video inputs, but the actual
12 * analog demodulator code isn't implemented (not needed for xc5000 since it
13 * has its own demodulator and outputs CVBS)
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/videodev2.h>
20#include <linux/i2c.h>
21#include <linux/delay.h>
22#include <media/v4l2-common.h>
23#include <media/v4l2-device.h>
24#include "au8522.h"
25#include "au8522_priv.h"
26
27MODULE_AUTHOR("Devin Heitmueller");
28MODULE_DESCRIPTION("Auvitek AU8522 QAM/8VSB demodulator driver and video decoder");
29MODULE_LICENSE("GPL");
30
31static int au8522_analog_debug;
32
33
34module_param_named(analog_debug, au8522_analog_debug, int, 0644);
35
36MODULE_PARM_DESC(analog_debug,
37 "Analog debugging messages [0=Off (default) 1=On]");
38
39struct au8522_register_config {
40 u16 reg_name;
41 u8 reg_val[8];
42};
43
44
45/* Video Decoder Filter Coefficients
46 The values are as follows from left to right
47 0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
48*/
49static const struct au8522_register_config filter_coef[] = {
50 {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
51 {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
52 {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
53 {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
54 {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
55 {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
56 {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
57 {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
58 {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
59 {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
60 {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
61 {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
62 {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
63 {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
64 {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
65 {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
66 {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
67 {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
68 {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
69 {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
70 {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
71 {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
72 {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
73 {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
74 {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
75 {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
76 {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
77 {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
78 {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
79 {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
80
81};
82#define NUM_FILTER_COEF (sizeof(filter_coef)\
83 / sizeof(struct au8522_register_config))
84
85
86/* Registers 0x060b through 0x0652 are the LP Filter coefficients
87 The values are as follows from left to right
88 0="SIF" 1="ATVRF/ATVRF13"
89 Note: the "ATVRF/ATVRF13" mode has never been tested
90*/
91static const struct au8522_register_config lpfilter_coef[] = {
92 {0x060b, {0x21, 0x0b} },
93 {0x060c, {0xad, 0xad} },
94 {0x060d, {0x70, 0xf0} },
95 {0x060e, {0xea, 0xe9} },
96 {0x060f, {0xdd, 0xdd} },
97 {0x0610, {0x08, 0x64} },
98 {0x0611, {0x60, 0x60} },
99 {0x0612, {0xf8, 0xb2} },
100 {0x0613, {0x01, 0x02} },
101 {0x0614, {0xe4, 0xb4} },
102 {0x0615, {0x19, 0x02} },
103 {0x0616, {0xae, 0x2e} },
104 {0x0617, {0xee, 0xc5} },
105 {0x0618, {0x56, 0x56} },
106 {0x0619, {0x30, 0x58} },
107 {0x061a, {0xf9, 0xf8} },
108 {0x061b, {0x24, 0x64} },
109 {0x061c, {0x07, 0x07} },
110 {0x061d, {0x30, 0x30} },
111 {0x061e, {0xa9, 0xed} },
112 {0x061f, {0x09, 0x0b} },
113 {0x0620, {0x42, 0xc2} },
114 {0x0621, {0x1d, 0x2a} },
115 {0x0622, {0xd6, 0x56} },
116 {0x0623, {0x95, 0x8b} },
117 {0x0624, {0x2b, 0x2b} },
118 {0x0625, {0x30, 0x24} },
119 {0x0626, {0x3e, 0x3e} },
120 {0x0627, {0x62, 0xe2} },
121 {0x0628, {0xe9, 0xf5} },
122 {0x0629, {0x99, 0x19} },
123 {0x062a, {0xd4, 0x11} },
124 {0x062b, {0x03, 0x04} },
125 {0x062c, {0xb5, 0x85} },
126 {0x062d, {0x1e, 0x20} },
127 {0x062e, {0x2a, 0xea} },
128 {0x062f, {0xd7, 0xd2} },
129 {0x0630, {0x15, 0x15} },
130 {0x0631, {0xa3, 0xa9} },
131 {0x0632, {0x1f, 0x1f} },
132 {0x0633, {0xf9, 0xd1} },
133 {0x0634, {0xc0, 0xc3} },
134 {0x0635, {0x4d, 0x8d} },
135 {0x0636, {0x21, 0x31} },
136 {0x0637, {0x83, 0x83} },
137 {0x0638, {0x08, 0x8c} },
138 {0x0639, {0x19, 0x19} },
139 {0x063a, {0x45, 0xa5} },
140 {0x063b, {0xef, 0xec} },
141 {0x063c, {0x8a, 0x8a} },
142 {0x063d, {0xf4, 0xf6} },
143 {0x063e, {0x8f, 0x8f} },
144 {0x063f, {0x44, 0x0c} },
145 {0x0640, {0xef, 0xf0} },
146 {0x0641, {0x66, 0x66} },
147 {0x0642, {0xcc, 0xd2} },
148 {0x0643, {0x41, 0x41} },
149 {0x0644, {0x63, 0x93} },
150 {0x0645, {0x8e, 0x8e} },
151 {0x0646, {0xa2, 0x42} },
152 {0x0647, {0x7b, 0x7b} },
153 {0x0648, {0x04, 0x04} },
154 {0x0649, {0x00, 0x00} },
155 {0x064a, {0x40, 0x40} },
156 {0x064b, {0x8c, 0x98} },
157 {0x064c, {0x00, 0x00} },
158 {0x064d, {0x63, 0xc3} },
159 {0x064e, {0x04, 0x04} },
160 {0x064f, {0x20, 0x20} },
161 {0x0650, {0x00, 0x00} },
162 {0x0651, {0x40, 0x40} },
163 {0x0652, {0x01, 0x01} },
164};
165#define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
166 / sizeof(struct au8522_register_config))
167
168static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
169{
170 return container_of(sd, struct au8522_state, sd);
171}
172
173static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo)
174{
175 int i;
176 int filter_coef_type;
177
178 /* Provide reasonable defaults for picture tuning values */
179 au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
180 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
181 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
182 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
183 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
184 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
185 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
186
187 /* Other decoder registers */
188 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
189
190 if (is_svideo)
191 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
192 else
193 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
194
195 au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
196 AU8522_TVDEC_PGA_REG012H_CVBS);
197 au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
198 AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
199 au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
200 AU8522_TVDED_DBG_MODE_REG060H_CVBS);
201
202 if (state->std == V4L2_STD_PAL_M) {
203 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
204 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
205 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
206 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO);
207 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
208 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M);
209 } else {
210 /* NTSC */
211 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
212 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
213 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
214 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
215 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
216 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
217 }
218 au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
219 AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
220 au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
221 AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
222 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
223 AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
224 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
225 AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
226 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
227 AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
228 au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
229 AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
230 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
231 AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
232 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
233 AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
234 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
235 AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
236 if (is_svideo) {
237 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
238 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
239 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
240 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
241 } else {
242 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
243 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
244 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
245 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
246 }
247 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
248 AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
249 au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
250 AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
251 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
252 AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
253 au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
254 au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
255 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
256 AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
257 au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
258 au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
259 au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
260 AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
261 au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
262 AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
263 au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
264 AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
265 au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
266 AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
267 au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
268 AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
269 au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
270 AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
271 au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
272 AU8522_TOREGAAGC_REG0E5H_CVBS);
273 au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
274
275 /*
276 * Despite what the table says, for the HVR-950q we still need
277 * to be in CVBS mode for the S-Video input (reason unknown).
278 */
279 /* filter_coef_type = 3; */
280 filter_coef_type = 5;
281
282 /* Load the Video Decoder Filter Coefficients */
283 for (i = 0; i < NUM_FILTER_COEF; i++) {
284 au8522_writereg(state, filter_coef[i].reg_name,
285 filter_coef[i].reg_val[filter_coef_type]);
286 }
287
288 /* It's not clear what these registers are for, but they are always
289 set to the same value regardless of what mode we're in */
290 au8522_writereg(state, AU8522_REG42EH, 0x87);
291 au8522_writereg(state, AU8522_REG42FH, 0xa2);
292 au8522_writereg(state, AU8522_REG430H, 0xbf);
293 au8522_writereg(state, AU8522_REG431H, 0xcb);
294 au8522_writereg(state, AU8522_REG432H, 0xa1);
295 au8522_writereg(state, AU8522_REG433H, 0x41);
296 au8522_writereg(state, AU8522_REG434H, 0x88);
297 au8522_writereg(state, AU8522_REG435H, 0xc2);
298 au8522_writereg(state, AU8522_REG436H, 0x3c);
299}
300
301static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode)
302{
303 /* here we're going to try the pre-programmed route */
304 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
305 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
306
307 /* PGA in automatic mode */
308 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
309
310 /* Enable clamping control */
311 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
312
313 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
314
315 setup_decoder_defaults(state, false);
316
317 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
318 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
319}
320
321static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state,
322 u8 input_mode)
323{
324 /* here we're going to try the pre-programmed route */
325 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
326 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
327
328 /* It's not clear why we have to have the PGA in automatic mode while
329 enabling clamp control, but it's what Windows does */
330 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
331
332 /* Enable clamping control */
333 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
334
335 /* Disable automatic PGA (since the CVBS is coming from the tuner) */
336 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
337
338 /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
339 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
340
341 setup_decoder_defaults(state, false);
342
343 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
344 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
345}
346
347static void au8522_setup_svideo_mode(struct au8522_state *state,
348 u8 input_mode)
349{
350 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
351 AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
352
353 /* Set input to Y on Channe1, C on Channel 3 */
354 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
355
356 /* PGA in automatic mode */
357 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
358
359 /* Enable clamping control */
360 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
361
362 setup_decoder_defaults(state, true);
363
364 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
365 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
366}
367
368/* ----------------------------------------------------------------------- */
369
370static void disable_audio_input(struct au8522_state *state)
371{
372 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
373 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
374 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
375
376 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
377 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
378
379 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
380 AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
381}
382
383/* 0=disable, 1=SIF */
384static void set_audio_input(struct au8522_state *state)
385{
386 int aud_input = state->aud_input;
387 int i;
388
389 /* Note that this function needs to be used in conjunction with setting
390 the input routing via register 0x81 */
391
392 if (aud_input == AU8522_AUDIO_NONE) {
393 disable_audio_input(state);
394 return;
395 }
396
397 if (aud_input != AU8522_AUDIO_SIF) {
398 /* The caller asked for a mode we don't currently support */
399 printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
400 aud_input);
401 return;
402 }
403
404 /* Load the Audio Decoder Filter Coefficients */
405 for (i = 0; i < NUM_LPFILTER_COEF; i++) {
406 au8522_writereg(state, lpfilter_coef[i].reg_name,
407 lpfilter_coef[i].reg_val[0]);
408 }
409
410 /* Set the volume */
411 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
412 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
413 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
414
415 /* Not sure what this does */
416 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
417
418 /* Setup the audio mode to stereo DBX */
419 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
420 msleep(70);
421
422 /* Start the audio processing module */
423 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
424
425 /* Set the audio frequency to 48 KHz */
426 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
427
428 /* Set the I2S parameters (WS, LSB, mode, sample rate */
429 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
430
431 /* Enable the I2S output */
432 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
433}
434
435/* ----------------------------------------------------------------------- */
436
437static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
438{
439 struct au8522_state *state =
440 container_of(ctrl->handler, struct au8522_state, hdl);
441
442 switch (ctrl->id) {
443 case V4L2_CID_BRIGHTNESS:
444 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
445 ctrl->val - 128);
446 break;
447 case V4L2_CID_CONTRAST:
448 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
449 ctrl->val);
450 break;
451 case V4L2_CID_SATURATION:
452 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
453 ctrl->val);
454 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
455 ctrl->val);
456 break;
457 case V4L2_CID_HUE:
458 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
459 ctrl->val >> 8);
460 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
461 ctrl->val & 0xFF);
462 break;
463 default:
464 return -EINVAL;
465 }
466
467 return 0;
468}
469
470/* ----------------------------------------------------------------------- */
471
472#ifdef CONFIG_VIDEO_ADV_DEBUG
473static int au8522_g_register(struct v4l2_subdev *sd,
474 struct v4l2_dbg_register *reg)
475{
476 struct au8522_state *state = to_state(sd);
477
478 reg->val = au8522_readreg(state, reg->reg & 0xffff);
479 return 0;
480}
481
482static int au8522_s_register(struct v4l2_subdev *sd,
483 const struct v4l2_dbg_register *reg)
484{
485 struct au8522_state *state = to_state(sd);
486
487 au8522_writereg(state, reg->reg, reg->val & 0xff);
488 return 0;
489}
490#endif
491
492static void au8522_video_set(struct au8522_state *state)
493{
494 u8 input_mode;
495
496 au8522_writereg(state, 0xa4, 1 << 5);
497
498 switch (state->vid_input) {
499 case AU8522_COMPOSITE_CH1:
500 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH1;
501 au8522_setup_cvbs_mode(state, input_mode);
502 break;
503 case AU8522_COMPOSITE_CH2:
504 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH2;
505 au8522_setup_cvbs_mode(state, input_mode);
506 break;
507 case AU8522_COMPOSITE_CH3:
508 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH3;
509 au8522_setup_cvbs_mode(state, input_mode);
510 break;
511 case AU8522_COMPOSITE_CH4:
512 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4;
513 au8522_setup_cvbs_mode(state, input_mode);
514 break;
515 case AU8522_SVIDEO_CH13:
516 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13;
517 au8522_setup_svideo_mode(state, input_mode);
518 break;
519 case AU8522_SVIDEO_CH24:
520 input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24;
521 au8522_setup_svideo_mode(state, input_mode);
522 break;
523 default:
524 case AU8522_COMPOSITE_CH4_SIF:
525 input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF;
526 au8522_setup_cvbs_tuner_mode(state, input_mode);
527 break;
528 }
529}
530
531static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
532{
533 struct au8522_state *state = to_state(sd);
534
535 if (enable) {
536 /*
537 * Clear out any state associated with the digital side of the
538 * chip, so that when it gets powered back up it won't think
539 * that it is already tuned
540 */
541 state->current_frequency = 0;
542
543 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
544 0x01);
545 msleep(10);
546
547 au8522_video_set(state);
548 set_audio_input(state);
549
550 state->operational_mode = AU8522_ANALOG_MODE;
551 } else {
552 /* This does not completely power down the device
553 (it only reduces it from around 140ma to 80ma) */
554 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
555 1 << 5);
556 state->operational_mode = AU8522_SUSPEND_MODE;
557 }
558 return 0;
559}
560
561static int au8522_s_video_routing(struct v4l2_subdev *sd,
562 u32 input, u32 output, u32 config)
563{
564 struct au8522_state *state = to_state(sd);
565
566 switch (input) {
567 case AU8522_COMPOSITE_CH1:
568 case AU8522_SVIDEO_CH13:
569 case AU8522_COMPOSITE_CH4_SIF:
570 case AU8522_COMPOSITE_CH4:
571 state->vid_input = input;
572 break;
573 default:
574 printk(KERN_ERR "au8522 mode not currently supported\n");
575 return -EINVAL;
576 }
577
578 if (state->operational_mode == AU8522_ANALOG_MODE)
579 au8522_video_set(state);
580
581 return 0;
582}
583
584static int au8522_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
585{
586 struct au8522_state *state = to_state(sd);
587
588 if ((std & (V4L2_STD_PAL_M | V4L2_STD_NTSC_M)) == 0)
589 return -EINVAL;
590
591 state->std = std;
592
593 if (state->operational_mode == AU8522_ANALOG_MODE)
594 au8522_video_set(state);
595
596 return 0;
597}
598
599static int au8522_s_audio_routing(struct v4l2_subdev *sd,
600 u32 input, u32 output, u32 config)
601{
602 struct au8522_state *state = to_state(sd);
603
604 state->aud_input = input;
605
606 if (state->operational_mode == AU8522_ANALOG_MODE)
607 set_audio_input(state);
608
609 return 0;
610}
611
612static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
613{
614 int val = 0;
615 struct au8522_state *state = to_state(sd);
616 u8 lock_status;
617 u8 pll_status;
618
619 /* Interrogate the decoder to see if we are getting a real signal */
620 lock_status = au8522_readreg(state, 0x00);
621 pll_status = au8522_readreg(state, 0x7e);
622 if ((lock_status == 0xa2) && (pll_status & 0x10))
623 vt->signal = 0xffff;
624 else
625 vt->signal = 0x00;
626
627 vt->capability |=
628 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
629 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
630
631 val = V4L2_TUNER_SUB_MONO;
632 vt->rxsubchans = val;
633 vt->audmode = V4L2_TUNER_MODE_STEREO;
634 return 0;
635}
636
637/* ----------------------------------------------------------------------- */
638
639static const struct v4l2_subdev_core_ops au8522_core_ops = {
640 .log_status = v4l2_ctrl_subdev_log_status,
641#ifdef CONFIG_VIDEO_ADV_DEBUG
642 .g_register = au8522_g_register,
643 .s_register = au8522_s_register,
644#endif
645};
646
647static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
648 .g_tuner = au8522_g_tuner,
649};
650
651static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
652 .s_routing = au8522_s_audio_routing,
653};
654
655static const struct v4l2_subdev_video_ops au8522_video_ops = {
656 .s_routing = au8522_s_video_routing,
657 .s_stream = au8522_s_stream,
658 .s_std = au8522_s_std,
659};
660
661static const struct v4l2_subdev_ops au8522_ops = {
662 .core = &au8522_core_ops,
663 .tuner = &au8522_tuner_ops,
664 .audio = &au8522_audio_ops,
665 .video = &au8522_video_ops,
666};
667
668static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
669 .s_ctrl = au8522_s_ctrl,
670};
671
672/* ----------------------------------------------------------------------- */
673
674static int au8522_probe(struct i2c_client *client)
675{
676 struct au8522_state *state;
677 struct v4l2_ctrl_handler *hdl;
678 struct v4l2_subdev *sd;
679 int instance;
680#ifdef CONFIG_MEDIA_CONTROLLER
681 int ret;
682#endif
683
684 /* Check if the adapter supports the needed features */
685 if (!i2c_check_functionality(client->adapter,
686 I2C_FUNC_SMBUS_BYTE_DATA)) {
687 return -EIO;
688 }
689
690 /* allocate memory for the internal state */
691 instance = au8522_get_state(&state, client->adapter, client->addr);
692 switch (instance) {
693 case 0:
694 printk(KERN_ERR "au8522_decoder allocation failed\n");
695 return -EIO;
696 case 1:
697 /* new demod instance */
698 printk(KERN_INFO "au8522_decoder creating new instance...\n");
699 break;
700 default:
701 /* existing demod instance */
702 printk(KERN_INFO "au8522_decoder attach existing instance.\n");
703 break;
704 }
705
706 state->config.demod_address = 0x8e >> 1;
707 state->i2c = client->adapter;
708
709 sd = &state->sd;
710 v4l2_i2c_subdev_init(sd, client, &au8522_ops);
711#if defined(CONFIG_MEDIA_CONTROLLER)
712
713 state->pads[AU8522_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
714 state->pads[AU8522_PAD_IF_INPUT].sig_type = PAD_SIGNAL_ANALOG;
715 state->pads[AU8522_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
716 state->pads[AU8522_PAD_VID_OUT].sig_type = PAD_SIGNAL_DV;
717 state->pads[AU8522_PAD_AUDIO_OUT].flags = MEDIA_PAD_FL_SOURCE;
718 state->pads[AU8522_PAD_AUDIO_OUT].sig_type = PAD_SIGNAL_AUDIO;
719 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
720
721 ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(state->pads),
722 state->pads);
723 if (ret < 0) {
724 v4l_info(client, "failed to initialize media entity!\n");
725 return ret;
726 }
727#endif
728
729 hdl = &state->hdl;
730 v4l2_ctrl_handler_init(hdl, 4);
731 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
732 V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
733 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
734 V4L2_CID_CONTRAST, 0, 255, 1,
735 AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
736 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
737 V4L2_CID_SATURATION, 0, 255, 1, 128);
738 v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
739 V4L2_CID_HUE, -32768, 32767, 1, 0);
740 sd->ctrl_handler = hdl;
741 if (hdl->error) {
742 int err = hdl->error;
743
744 v4l2_ctrl_handler_free(hdl);
745 au8522_release_state(state);
746 return err;
747 }
748
749 state->c = client;
750 state->std = V4L2_STD_NTSC_M;
751 state->vid_input = AU8522_COMPOSITE_CH1;
752 state->aud_input = AU8522_AUDIO_NONE;
753 state->id = 8522;
754 state->rev = 0;
755
756 /* Jam open the i2c gate to the tuner */
757 au8522_writereg(state, 0x106, 1);
758
759 return 0;
760}
761
762static void au8522_remove(struct i2c_client *client)
763{
764 struct v4l2_subdev *sd = i2c_get_clientdata(client);
765 v4l2_device_unregister_subdev(sd);
766 v4l2_ctrl_handler_free(sd->ctrl_handler);
767 au8522_release_state(to_state(sd));
768}
769
770static const struct i2c_device_id au8522_id[] = {
771 { .name = "au8522" },
772 { }
773};
774
775MODULE_DEVICE_TABLE(i2c, au8522_id);
776
777static struct i2c_driver au8522_driver = {
778 .driver = {
779 .name = "au8522",
780 },
781 .probe = au8522_probe,
782 .remove = au8522_remove,
783 .id_table = au8522_id,
784};
785
786module_i2c_driver(au8522_driver);