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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#include "iris_instance.h"
7#include "iris_vpu_buffer.h"
8#include "iris_hfi_gen1_defines.h"
9#include "iris_hfi_gen2_defines.h"
10
11#define HFI_MAX_COL_FRAME 6
12#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_HEIGHT (8)
13#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH (32)
14#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_HEIGHT (8)
15#define HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_WIDTH (16)
16#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_HEIGHT (4)
17#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH (48)
18#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_HEIGHT (4)
19#define HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_WIDTH (24)
20#define AV1D_SIZE_BSE_COL_MV_64x64 512
21#define AV1D_SIZE_BSE_COL_MV_128x128 2816
22#define UBWC_TILE_SIZE 256
23
24#ifndef SYSTEM_LAL_TILE10
25#define SYSTEM_LAL_TILE10 192
26#endif
27
28static u32 size_h264d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
29{
30 u32 size_yuv, size_bin_hdr, size_bin_res;
31
32 size_yuv = ((frame_width * frame_height) <= BIN_BUFFER_THRESHOLD) ?
33 ((BIN_BUFFER_THRESHOLD * 3) >> 1) :
34 ((frame_width * frame_height * 3) >> 1);
35 size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT;
36 size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT;
37 size_bin_hdr = ALIGN(size_bin_hdr / num_vpp_pipes,
38 DMA_ALIGNMENT) * num_vpp_pipes;
39 size_bin_res = ALIGN(size_bin_res / num_vpp_pipes,
40 DMA_ALIGNMENT) * num_vpp_pipes;
41
42 return size_bin_hdr + size_bin_res;
43}
44
45static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
46{
47 u32 n_aligned_h = ALIGN(frame_height, 16);
48 u32 n_aligned_w = ALIGN(frame_width, 16);
49
50 return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes);
51}
52
53static u32 size_av1d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
54{
55 u32 size_yuv, size_bin_hdr, size_bin_res;
56
57 size_yuv = ((frame_width * frame_height) <= BIN_BUFFER_THRESHOLD) ?
58 ((BIN_BUFFER_THRESHOLD * 3) >> 1) :
59 ((frame_width * frame_height * 3) >> 1);
60 size_bin_hdr = size_yuv * AV1_CABAC_HDR_RATIO_HD_TOT;
61 size_bin_res = size_yuv * AV1_CABAC_RES_RATIO_HD_TOT;
62 size_bin_hdr = ALIGN(size_bin_hdr / num_vpp_pipes,
63 DMA_ALIGNMENT) * num_vpp_pipes;
64 size_bin_res = ALIGN(size_bin_res / num_vpp_pipes,
65 DMA_ALIGNMENT) * num_vpp_pipes;
66
67 return size_bin_hdr + size_bin_res;
68}
69
70static u32 hfi_buffer_bin_av1d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
71{
72 u32 n_aligned_h = ALIGN(frame_height, 16);
73 u32 n_aligned_w = ALIGN(frame_width, 16);
74
75 return size_av1d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes);
76}
77
78static u32 size_h265d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
79{
80 u32 product = frame_width * frame_height;
81 u32 size_yuv, size_bin_hdr, size_bin_res;
82
83 size_yuv = (product <= BIN_BUFFER_THRESHOLD) ?
84 ((BIN_BUFFER_THRESHOLD * 3) >> 1) : ((product * 3) >> 1);
85 size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT;
86 size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT;
87 size_bin_hdr = ALIGN(size_bin_hdr / num_vpp_pipes, DMA_ALIGNMENT) * num_vpp_pipes;
88 size_bin_res = ALIGN(size_bin_res / num_vpp_pipes, DMA_ALIGNMENT) * num_vpp_pipes;
89
90 return size_bin_hdr + size_bin_res;
91}
92
93static u32 hfi_buffer_bin_vp9d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
94{
95 u32 _size_yuv = ALIGN(frame_width, 16) * ALIGN(frame_height, 16) * 3 / 2;
96 u32 _size = ALIGN(((max_t(u32, _size_yuv, ((BIN_BUFFER_THRESHOLD * 3) >> 1)) *
97 VPX_DECODER_FRAME_BIN_HDR_BUDGET / VPX_DECODER_FRAME_BIN_DENOMINATOR *
98 VPX_DECODER_FRAME_CONCURENCY_LVL) / num_vpp_pipes), DMA_ALIGNMENT) +
99 ALIGN(((max_t(u32, _size_yuv, ((BIN_BUFFER_THRESHOLD * 3) >> 1)) *
100 VPX_DECODER_FRAME_BIN_RES_BUDGET / VPX_DECODER_FRAME_BIN_DENOMINATOR *
101 VPX_DECODER_FRAME_CONCURENCY_LVL) / num_vpp_pipes), DMA_ALIGNMENT);
102
103 return _size * num_vpp_pipes;
104}
105
106static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
107{
108 u32 n_aligned_w = ALIGN(frame_width, 16);
109 u32 n_aligned_h = ALIGN(frame_height, 16);
110
111 return size_h265d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes);
112}
113
114static u32 hfi_buffer_comv_h264d(u32 frame_width, u32 frame_height, u32 _comv_bufcount)
115{
116 u32 frame_height_in_mbs = DIV_ROUND_UP(frame_height, 16);
117 u32 frame_width_in_mbs = DIV_ROUND_UP(frame_width, 16);
118 u32 col_zero_aligned_width = (frame_width_in_mbs << 2);
119 u32 col_mv_aligned_width = (frame_width_in_mbs << 7);
120 u32 col_zero_size, size_colloc;
121
122 col_mv_aligned_width = ALIGN(col_mv_aligned_width, 16);
123 col_zero_aligned_width = ALIGN(col_zero_aligned_width, 16);
124 col_zero_size = col_zero_aligned_width *
125 ((frame_height_in_mbs + 1) >> 1);
126 col_zero_size = ALIGN(col_zero_size, 64);
127 col_zero_size <<= 1;
128 col_zero_size = ALIGN(col_zero_size, 512);
129 size_colloc = col_mv_aligned_width * ((frame_height_in_mbs + 1) >> 1);
130 size_colloc = ALIGN(size_colloc, 64);
131 size_colloc <<= 1;
132 size_colloc = ALIGN(size_colloc, 512);
133 size_colloc += (col_zero_size + SIZE_H264D_BUFTAB_T * 2);
134
135 return (size_colloc * (_comv_bufcount)) + 512;
136}
137
138static u32 hfi_buffer_comv_h265d(u32 frame_width, u32 frame_height, u32 _comv_bufcount)
139{
140 u32 frame_height_in_mbs = (frame_height + 15) >> 4;
141 u32 frame_width_in_mbs = (frame_width + 15) >> 4;
142 u32 _size;
143
144 _size = ALIGN(((frame_width_in_mbs * frame_height_in_mbs) << 8), 512);
145
146 return (_size * (_comv_bufcount)) + 512;
147}
148
149static u32 num_lcu(u32 frame_width, u32 frame_height, u32 lcu_size)
150{
151 return ((frame_width + lcu_size - 1) / lcu_size) *
152 ((frame_height + lcu_size - 1) / lcu_size);
153}
154
155static u32 hfi_buffer_comv_av1d(u32 frame_width, u32 frame_height, u32 comv_bufcount)
156{
157 u32 size;
158
159 size = 2 * ALIGN(max(num_lcu(frame_width, frame_height, 64) *
160 AV1D_SIZE_BSE_COL_MV_64x64,
161 num_lcu(frame_width, frame_height, 128) *
162 AV1D_SIZE_BSE_COL_MV_128x128),
163 DMA_ALIGNMENT);
164 size *= comv_bufcount;
165
166 return size;
167}
168
169static u32 size_h264d_bse_cmd_buf(u32 frame_height)
170{
171 u32 height = ALIGN(frame_height, 32);
172
173 return min_t(u32, (DIV_ROUND_UP(height, 16) * 48), H264D_MAX_SLICE) *
174 SIZE_H264D_BSE_CMD_PER_BUF;
175}
176
177static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height)
178{
179 u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
180 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) *
181 NUM_HW_PIC_BUF, DMA_ALIGNMENT);
182 _size = min_t(u32, _size, H265D_MAX_SLICE + 1);
183 _size = 2 * _size * SIZE_H265D_BSE_CMD_PER_BUF;
184
185 return _size;
186}
187
188static u32 hfi_buffer_persist_h265d(u32 rpu_enabled)
189{
190 return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 +
191 H265_NUM_FRM_INFO * H265_DISPLAY_BUF_SIZE +
192 H265_NUM_TILE * sizeof(u32) +
193 NUM_HW_PIC_BUF * SIZE_SEI_USERDATA +
194 rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA),
195 DMA_ALIGNMENT);
196}
197
198static inline
199u32 hfi_iris3_vp9d_comv_size(void)
200{
201 return (((8192 + 63) >> 6) * ((4320 + 63) >> 6) * 8 * 8 * 2 * 8);
202}
203
204static u32 hfi_buffer_persist_vp9d(void)
205{
206 return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALIGNMENT) +
207 ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) +
208 ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) +
209 ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) +
210 ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) +
211 ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE, DMA_ALIGNMENT) +
212 HDR10_HIST_EXTRADATA_SIZE;
213}
214
215static u32 size_h264d_vpp_cmd_buf(u32 frame_height)
216{
217 u32 size, height = ALIGN(frame_height, 32);
218
219 size = min_t(u32, (DIV_ROUND_UP(height, 16) * 48), H264D_MAX_SLICE) *
220 SIZE_H264D_VPP_CMD_PER_BUF;
221
222 return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size;
223}
224
225static u32 hfi_buffer_persist_h264d(void)
226{
227 return ALIGN(SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 +
228 H264_DISPLAY_BUF_SIZE * H264_NUM_FRM_INFO +
229 NUM_HW_PIC_BUF * SIZE_SEI_USERDATA,
230 DMA_ALIGNMENT);
231}
232
233static u32 hfi_buffer_persist_av1d(u32 max_width, u32 max_height, u32 total_ref_count)
234{
235 u32 comv_size, size;
236
237 comv_size = hfi_buffer_comv_av1d(max_width, max_height, total_ref_count);
238 size = ALIGN((SIZE_AV1D_SEQUENCE_HEADER * 2 + SIZE_AV1D_METADATA +
239 AV1D_NUM_HW_PIC_BUF * (SIZE_AV1D_TILE_OFFSET + SIZE_AV1D_QM) +
240 AV1D_NUM_FRAME_HEADERS * (SIZE_AV1D_FRAME_HEADER +
241 2 * SIZE_AV1D_PROB_TABLE) + comv_size + HDR10_HIST_EXTRADATA_SIZE +
242 SIZE_AV1D_METADATA * AV1D_NUM_HW_PIC_BUF), DMA_ALIGNMENT);
243
244 return ALIGN(size, DMA_ALIGNMENT);
245}
246
247static u32 hfi_buffer_non_comv_h264d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
248{
249 u32 size_bse = size_h264d_bse_cmd_buf(frame_height);
250 u32 size_vpp = size_h264d_vpp_cmd_buf(frame_height);
251 u32 size = ALIGN(size_bse, DMA_ALIGNMENT) +
252 ALIGN(size_vpp, DMA_ALIGNMENT) +
253 ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), DMA_ALIGNMENT);
254
255 return ALIGN(size, DMA_ALIGNMENT);
256}
257
258static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height)
259{
260 u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
261 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) *
262 NUM_HW_PIC_BUF, DMA_ALIGNMENT);
263 _size = min_t(u32, _size, H265D_MAX_SLICE + 1);
264 _size = ALIGN(_size, 4);
265 _size = 2 * _size * SIZE_H265D_VPP_CMD_PER_BUF;
266 if (_size > VPP_CMD_MAX_SIZE)
267 _size = VPP_CMD_MAX_SIZE;
268
269 return _size;
270}
271
272static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
273{
274 u32 _size_bse = size_h265d_bse_cmd_buf(frame_width, frame_height);
275 u32 _size_vpp = size_h265d_vpp_cmd_buf(frame_width, frame_height);
276 u32 _size = ALIGN(_size_bse, DMA_ALIGNMENT) +
277 ALIGN(_size_vpp, DMA_ALIGNMENT) +
278 ALIGN(NUM_HW_PIC_BUF * 20 * 22 * 4, DMA_ALIGNMENT) +
279 ALIGN(2 * sizeof(u16) *
280 (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
281 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS), DMA_ALIGNMENT) +
282 ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), DMA_ALIGNMENT) +
283 HDR10_HIST_EXTRADATA_SIZE;
284
285 return ALIGN(_size, DMA_ALIGNMENT);
286}
287
288static u32 size_vpss_lb(u32 frame_width, u32 frame_height)
289{
290 u32 opb_lb_wr_llb_y_buffer_size, opb_lb_wr_llb_uv_buffer_size;
291 u32 opb_wr_top_line_chroma_buffer_size;
292 u32 opb_wr_top_line_luma_buffer_size;
293 u32 macrotiling_size = 32;
294
295 opb_wr_top_line_luma_buffer_size =
296 ALIGN(frame_width, macrotiling_size) / macrotiling_size * 256;
297 opb_wr_top_line_luma_buffer_size =
298 ALIGN(opb_wr_top_line_luma_buffer_size, DMA_ALIGNMENT) +
299 (MAX_TILE_COLUMNS - 1) * 256;
300 opb_wr_top_line_luma_buffer_size =
301 max_t(u32, opb_wr_top_line_luma_buffer_size, (32 * ALIGN(frame_height, 8)));
302 opb_wr_top_line_chroma_buffer_size = opb_wr_top_line_luma_buffer_size;
303 opb_lb_wr_llb_uv_buffer_size =
304 ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64, 32);
305 opb_lb_wr_llb_y_buffer_size =
306 ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64, 32);
307 return opb_wr_top_line_luma_buffer_size +
308 opb_wr_top_line_chroma_buffer_size +
309 opb_lb_wr_llb_uv_buffer_size +
310 opb_lb_wr_llb_y_buffer_size;
311}
312
313static inline
314u32 size_h265d_lb_fe_top_data(u32 frame_width, u32 frame_height)
315{
316 return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE *
317 (ALIGN(frame_width, 64) + 8) * 2;
318}
319
320static inline
321u32 size_h265d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height)
322{
323 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE *
324 (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS);
325}
326
327static inline
328u32 size_h265d_lb_fe_left_ctrl(u32 frame_width, u32 frame_height)
329{
330 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE *
331 (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS);
332}
333
334static inline
335u32 size_h265d_lb_se_top_ctrl(u32 frame_width, u32 frame_height)
336{
337 return (LCU_MAX_SIZE_PELS / 8 * (128 / 8)) * ((frame_width + 15) >> 4);
338}
339
340static inline
341u32 size_h265d_lb_se_left_ctrl(u32 frame_width, u32 frame_height)
342{
343 return max_t(u32, ((frame_height + 16 - 1) / 8) *
344 MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE,
345 max_t(u32, ((frame_height + 32 - 1) / 8) *
346 MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE,
347 ((frame_height + 64 - 1) / 8) *
348 MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE));
349}
350
351static inline
352u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height)
353{
354 return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE *
355 (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS);
356}
357
358static inline
359u32 size_h265d_lb_vsp_top(u32 frame_width, u32 frame_height)
360{
361 return ((frame_width + 63) >> 6) * 128;
362}
363
364static inline
365u32 size_h265d_lb_vsp_left(u32 frame_width, u32 frame_height)
366{
367 return ((frame_height + 63) >> 6) * 128;
368}
369
370static inline
371u32 size_h265d_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height)
372{
373 return size_h264d_lb_recon_dma_metadata_wr(frame_height);
374}
375
376static inline
377u32 size_h265d_qp(u32 frame_width, u32 frame_height)
378{
379 return size_h264d_qp(frame_width, frame_height);
380}
381
382static inline
383u32 hfi_buffer_line_h265d(u32 frame_width, u32 frame_height, bool is_opb, u32 num_vpp_pipes)
384{
385 u32 vpss_lb_size = 0, _size;
386
387 _size = ALIGN(size_h265d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT) +
388 ALIGN(size_h265d_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
389 ALIGN(size_h265d_lb_fe_left_ctrl(frame_width, frame_height),
390 DMA_ALIGNMENT) * num_vpp_pipes +
391 ALIGN(size_h265d_lb_se_left_ctrl(frame_width, frame_height),
392 DMA_ALIGNMENT) * num_vpp_pipes +
393 ALIGN(size_h265d_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
394 ALIGN(size_h265d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT) +
395 ALIGN(size_h265d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) +
396 ALIGN(size_h265d_lb_vsp_left(frame_width, frame_height),
397 DMA_ALIGNMENT) * num_vpp_pipes +
398 ALIGN(size_h265d_lb_recon_dma_metadata_wr(frame_width, frame_height),
399 DMA_ALIGNMENT) * 4 +
400 ALIGN(size_h265d_qp(frame_width, frame_height), DMA_ALIGNMENT);
401 if (is_opb)
402 vpss_lb_size = size_vpss_lb(frame_width, frame_height);
403
404 return ALIGN((_size + vpss_lb_size), DMA_ALIGNMENT);
405}
406
407static inline
408u32 size_vpxd_lb_fe_left_ctrl(u32 frame_width, u32 frame_height)
409{
410 return max_t(u32, ((frame_height + 15) >> 4) *
411 MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE,
412 max_t(u32, ((frame_height + 31) >> 5) *
413 MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE,
414 ((frame_height + 63) >> 6) *
415 MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE));
416}
417
418static inline
419u32 size_vpxd_lb_fe_top_ctrl(u32 frame_width, u32 frame_height)
420{
421 return ((ALIGN(frame_width, 64) + 8) * 10 * 2);
422}
423
424static inline
425u32 size_vpxd_lb_se_top_ctrl(u32 frame_width, u32 frame_height)
426{
427 return ((frame_width + 15) >> 4) * MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE;
428}
429
430static inline
431u32 size_vpxd_lb_se_left_ctrl(u32 frame_width, u32 frame_height)
432{
433 return max_t(u32, ((frame_height + 15) >> 4) *
434 MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE,
435 max_t(u32, ((frame_height + 31) >> 5) *
436 MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE,
437 ((frame_height + 63) >> 6) *
438 MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE));
439}
440
441static inline
442u32 size_vpxd_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height)
443{
444 return ALIGN((ALIGN(frame_height, 8) / (4 / 2)) * 64,
445 BUFFER_ALIGNMENT_32_BYTES);
446}
447
448static inline __maybe_unused
449u32 size_mp2d_lb_fe_top_data(u32 frame_width, u32 frame_height)
450{
451 return ((ALIGN(frame_width, 16) + 8) * 10 * 2);
452}
453
454static inline
455u32 size_vp9d_lb_fe_top_data(u32 frame_width, u32 frame_height)
456{
457 return (ALIGN(ALIGN(frame_width, 8), 64) + 8) * 10 * 2;
458}
459
460static inline
461u32 size_vp9d_lb_pe_top_data(u32 frame_width, u32 frame_height)
462{
463 return ((ALIGN(ALIGN(frame_width, 8), 64) >> 6) * 176);
464}
465
466static inline
467u32 size_vp9d_lb_vsp_top(u32 frame_width, u32 frame_height)
468{
469 return (((ALIGN(ALIGN(frame_width, 8), 64) >> 6) * 64 * 8) + 256);
470}
471
472static inline
473u32 size_vp9d_qp(u32 frame_width, u32 frame_height)
474{
475 return size_h264d_qp(frame_width, frame_height);
476}
477
478static inline
479u32 hfi_iris3_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
480{
481 return ALIGN(size_vpxd_lb_fe_left_ctrl(frame_width, frame_height), DMA_ALIGNMENT) *
482 num_vpp_pipes +
483 ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_height), DMA_ALIGNMENT) *
484 num_vpp_pipes +
485 ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) +
486 ALIGN(size_vpxd_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
487 2 * ALIGN(size_vpxd_lb_recon_dma_metadata_wr(frame_width, frame_height),
488 DMA_ALIGNMENT) +
489 ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
490 ALIGN(size_vp9d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT) +
491 ALIGN(size_vp9d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT) +
492 ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT);
493}
494
495static inline
496u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min, bool is_opb,
497 u32 num_vpp_pipes)
498{
499 u32 vpss_lb_size = 0;
500 u32 _lb_size;
501
502 _lb_size = hfi_iris3_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes);
503
504 if (is_opb)
505 vpss_lb_size = size_vpss_lb(frame_width, frame_height);
506
507 return _lb_size + vpss_lb_size + 4096;
508}
509
510static u32 hfi_buffer_line_h264d(u32 frame_width, u32 frame_height,
511 bool is_opb, u32 num_vpp_pipes)
512{
513 u32 vpss_lb_size = 0;
514 u32 size;
515
516 size = ALIGN(size_h264d_lb_fe_top_data(frame_width), DMA_ALIGNMENT) +
517 ALIGN(size_h264d_lb_fe_top_ctrl(frame_width), DMA_ALIGNMENT) +
518 ALIGN(size_h264d_lb_fe_left_ctrl(frame_height), DMA_ALIGNMENT) * num_vpp_pipes +
519 ALIGN(size_h264d_lb_se_top_ctrl(frame_width), DMA_ALIGNMENT) +
520 ALIGN(size_h264d_lb_se_left_ctrl(frame_height), DMA_ALIGNMENT) * num_vpp_pipes +
521 ALIGN(size_h264d_lb_pe_top_data(frame_width), DMA_ALIGNMENT) +
522 ALIGN(size_h264d_lb_vsp_top(frame_width), DMA_ALIGNMENT) +
523 ALIGN(size_h264d_lb_recon_dma_metadata_wr(frame_height), DMA_ALIGNMENT) * 2 +
524 ALIGN(size_h264d_qp(frame_width, frame_height), DMA_ALIGNMENT);
525 size = ALIGN(size, DMA_ALIGNMENT);
526 if (is_opb)
527 vpss_lb_size = size_vpss_lb(frame_width, frame_height);
528
529 return ALIGN((size + vpss_lb_size), DMA_ALIGNMENT);
530}
531
532static u32 size_av1d_lb_opb_wr1_nv12_ubwc(u32 frame_width, u32 frame_height)
533{
534 u32 size, y_width, y_width_a = 128;
535
536 y_width = ALIGN(frame_width, y_width_a);
537
538 size = ((y_width + HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH - 1) /
539 HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH +
540 (AV1D_MAX_TILE_COLS - 1));
541 return size * UBWC_TILE_SIZE;
542}
543
544static u32 size_av1d_lb_opb_wr1_tp10_ubwc(u32 frame_width, u32 frame_height)
545{
546 u32 size, y_width, y_width_a = 256;
547
548 y_width = ALIGN(frame_width, y_width_a);
549
550 size = ((y_width + HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH - 1) /
551 HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH +
552 (AV1D_MAX_TILE_COLS - 1));
553
554 return size * UBWC_TILE_SIZE;
555}
556
557static u32 hfi_buffer_line_av1d(u32 frame_width, u32 frame_height,
558 bool is_opb, u32 num_vpp_pipes)
559{
560 u32 size, vpss_lb_size, opbwrbufsize, opbwr8, opbwr10;
561
562 size = ALIGN(size_av1d_lb_fe_top_data(frame_width, frame_height),
563 DMA_ALIGNMENT) +
564 ALIGN(size_av1d_lb_fe_top_ctrl(frame_width, frame_height),
565 DMA_ALIGNMENT) +
566 ALIGN(size_av1d_lb_fe_left_data(frame_width, frame_height),
567 DMA_ALIGNMENT) * num_vpp_pipes +
568 ALIGN(size_av1d_lb_fe_left_ctrl(frame_width, frame_height),
569 DMA_ALIGNMENT) * num_vpp_pipes +
570 ALIGN(size_av1d_lb_se_left_ctrl(frame_width, frame_height),
571 DMA_ALIGNMENT) * num_vpp_pipes +
572 ALIGN(size_av1d_lb_se_top_ctrl(frame_width, frame_height),
573 DMA_ALIGNMENT) +
574 ALIGN(size_av1d_lb_pe_top_data(frame_width, frame_height),
575 DMA_ALIGNMENT) +
576 ALIGN(size_av1d_lb_vsp_top(frame_width, frame_height),
577 DMA_ALIGNMENT) +
578 ALIGN(size_av1d_lb_recon_dma_metadata_wr
579 (frame_width, frame_height), DMA_ALIGNMENT) * 2 +
580 ALIGN(size_av1d_qp(frame_width, frame_height), DMA_ALIGNMENT);
581 opbwr8 = size_av1d_lb_opb_wr1_nv12_ubwc(frame_width, frame_height);
582 opbwr10 = size_av1d_lb_opb_wr1_tp10_ubwc(frame_width, frame_height);
583 opbwrbufsize = max(opbwr8, opbwr10);
584 size = ALIGN((size + opbwrbufsize), DMA_ALIGNMENT);
585 if (is_opb) {
586 vpss_lb_size = size_vpss_lb(frame_width, frame_height);
587 size = ALIGN((size + vpss_lb_size) * 2, DMA_ALIGNMENT);
588 }
589
590 return size;
591}
592
593static u32 size_av1d_ibc_nv12_ubwc(u32 frame_width, u32 frame_height)
594{
595 u32 size;
596 u32 y_width_a = 128, y_height_a = 32;
597 u32 uv_width_a = 128, uv_height_a = 32;
598 u32 ybufsize, uvbufsize, y_width, y_height, uv_width, uv_height;
599 u32 y_meta_width_a = 64, y_meta_height_a = 16;
600 u32 uv_meta_width_a = 64, uv_meta_height_a = 16;
601 u32 meta_height, meta_stride, meta_size;
602 u32 tile_width_y = HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_WIDTH;
603 u32 tile_height_y = HFI_COLOR_FORMAT_YUV420_NV12_UBWC_Y_TILE_HEIGHT;
604 u32 tile_width_uv = HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_WIDTH;
605 u32 tile_height_uv = HFI_COLOR_FORMAT_YUV420_NV12_UBWC_UV_TILE_HEIGHT;
606
607 y_width = ALIGN(frame_width, y_width_a);
608 y_height = ALIGN(frame_height, y_height_a);
609 uv_width = ALIGN(frame_width, uv_width_a);
610 uv_height = ALIGN(((frame_height + 1) >> 1), uv_height_a);
611 ybufsize = ALIGN((y_width * y_height), HFI_ALIGNMENT_4096);
612 uvbufsize = ALIGN(uv_width * uv_height, HFI_ALIGNMENT_4096);
613 size = ybufsize + uvbufsize;
614 meta_stride = ALIGN(((frame_width + (tile_width_y - 1)) / tile_width_y),
615 y_meta_width_a);
616 meta_height = ALIGN(((frame_height + (tile_height_y - 1)) / tile_height_y),
617 y_meta_height_a);
618 meta_size = ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096);
619 size += meta_size;
620 meta_stride = ALIGN(((((frame_width + 1) >> 1) + (tile_width_uv - 1)) /
621 tile_width_uv), uv_meta_width_a);
622 meta_height = ALIGN(((((frame_height + 1) >> 1) + (tile_height_uv - 1)) /
623 tile_height_uv), uv_meta_height_a);
624 meta_size = ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096);
625 size += meta_size;
626
627 return size;
628}
629
630static u32 hfi_yuv420_tp10_calc_y_stride(u32 frame_width, u32 stride_multiple)
631{
632 u32 stride;
633
634 stride = ALIGN(frame_width, 192);
635 stride = ALIGN(stride * 4 / 3, stride_multiple);
636
637 return stride;
638}
639
640static u32 hfi_yuv420_tp10_calc_y_bufheight(u32 frame_height, u32 min_buf_height_multiple)
641{
642 return ALIGN(frame_height, min_buf_height_multiple);
643}
644
645static u32 hfi_yuv420_tp10_calc_uv_stride(u32 frame_width, u32 stride_multiple)
646{
647 u32 stride;
648
649 stride = ALIGN(frame_width, 192);
650 stride = ALIGN(stride * 4 / 3, stride_multiple);
651
652 return stride;
653}
654
655static u32 hfi_yuv420_tp10_calc_uv_bufheight(u32 frame_height, u32 min_buf_height_multiple)
656{
657 return ALIGN(((frame_height + 1) >> 1), min_buf_height_multiple);
658}
659
660static u32 size_av1d_ibc_tp10_ubwc(u32 frame_width, u32 frame_height)
661{
662 u32 size;
663 u32 y_width_a = 256, y_height_a = 16,
664 uv_width_a = 256, uv_height_a = 16;
665 u32 ybufsize, uvbufsize, y_width, y_height, uv_width, uv_height;
666 u32 y_meta_width_a = 64, y_meta_height_a = 16,
667 uv_meta_width_a = 64, uv_meta_height_a = 16;
668 u32 meta_height, meta_stride, meta_size;
669 u32 tile_width_y = HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_WIDTH;
670 u32 tile_height_y = HFI_COLOR_FORMAT_YUV420_TP10_UBWC_Y_TILE_HEIGHT;
671 u32 tile_width_uv = HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_WIDTH;
672 u32 tile_height_uv = HFI_COLOR_FORMAT_YUV420_TP10_UBWC_UV_TILE_HEIGHT;
673
674 y_width = hfi_yuv420_tp10_calc_y_stride(frame_width, y_width_a);
675 y_height = hfi_yuv420_tp10_calc_y_bufheight(frame_height, y_height_a);
676 uv_width = hfi_yuv420_tp10_calc_uv_stride(frame_width, uv_width_a);
677 uv_height = hfi_yuv420_tp10_calc_uv_bufheight(frame_height, uv_height_a);
678 ybufsize = ALIGN(y_width * y_height, HFI_ALIGNMENT_4096);
679 uvbufsize = ALIGN(uv_width * uv_height, HFI_ALIGNMENT_4096);
680 size = ybufsize + uvbufsize;
681 meta_stride = ALIGN(((frame_width + (tile_width_y - 1)) / tile_width_y),
682 y_meta_width_a);
683 meta_height = ALIGN(((frame_height + (tile_height_y - 1)) / tile_height_y),
684 y_meta_height_a);
685 meta_size = ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096);
686 size += meta_size;
687 meta_stride = ALIGN(((((frame_width + 1) >> 1) + (tile_width_uv - 1)) /
688 tile_width_uv), uv_meta_width_a);
689 meta_height = ALIGN(((((frame_height + 1) >> 1) + (tile_height_uv - 1)) /
690 tile_height_uv), uv_meta_height_a);
691 meta_size = ALIGN(meta_stride * meta_height, HFI_ALIGNMENT_4096);
692 size += meta_size;
693
694 return size;
695}
696
697static u32 hfi_buffer_ibc_av1d(u32 frame_width, u32 frame_height)
698{
699 u32 size, ibc8, ibc10;
700
701 ibc8 = size_av1d_ibc_nv12_ubwc(frame_width, frame_height);
702 ibc10 = size_av1d_ibc_tp10_ubwc(frame_width, frame_height);
703 size = max(ibc8, ibc10);
704
705 return ALIGN(size, DMA_ALIGNMENT);
706}
707
708static u32 iris_vpu_dec_bin_size(struct iris_inst *inst)
709{
710 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
711 struct v4l2_format *f = inst->fmt_src;
712 u32 height = f->fmt.pix_mp.height;
713 u32 width = f->fmt.pix_mp.width;
714
715 if (inst->codec == V4L2_PIX_FMT_H264)
716 return hfi_buffer_bin_h264d(width, height, num_vpp_pipes);
717 else if (inst->codec == V4L2_PIX_FMT_HEVC)
718 return hfi_buffer_bin_h265d(width, height, num_vpp_pipes);
719 else if (inst->codec == V4L2_PIX_FMT_VP9)
720 return hfi_buffer_bin_vp9d(width, height, num_vpp_pipes);
721 else if (inst->codec == V4L2_PIX_FMT_AV1)
722 return hfi_buffer_bin_av1d(width, height, num_vpp_pipes);
723
724 return 0;
725}
726
727static u32 iris_vpu_dec_comv_size(struct iris_inst *inst)
728{
729 u32 num_comv = VIDEO_MAX_FRAME;
730 struct v4l2_format *f = inst->fmt_src;
731 u32 height = f->fmt.pix_mp.height;
732 u32 width = f->fmt.pix_mp.width;
733
734 if (inst->codec == V4L2_PIX_FMT_H264)
735 return hfi_buffer_comv_h264d(width, height, num_comv);
736 else if (inst->codec == V4L2_PIX_FMT_HEVC)
737 return hfi_buffer_comv_h265d(width, height, num_comv);
738
739 return 0;
740}
741
742static u32 iris_vpu3x_4x_dec_comv_size(struct iris_inst *inst)
743{
744 u32 num_comv = inst->buffers[BUF_OUTPUT].min_count;
745 struct v4l2_format *f = inst->fmt_src;
746 u32 height = f->fmt.pix_mp.height;
747 u32 width = f->fmt.pix_mp.width;
748
749 if (inst->fw_min_count)
750 num_comv = inst->fw_min_count;
751
752 if (inst->codec == V4L2_PIX_FMT_H264)
753 return hfi_buffer_comv_h264d(width, height, num_comv);
754 else if (inst->codec == V4L2_PIX_FMT_HEVC)
755 return hfi_buffer_comv_h265d(width, height, num_comv);
756 else if (inst->codec == V4L2_PIX_FMT_AV1) {
757 if (inst->fw_caps[DRAP].value)
758 return 0;
759 else
760 return hfi_buffer_comv_av1d(width, height, num_comv);
761 }
762
763 return 0;
764}
765
766static u32 iris_vpu_dec_persist_size(struct iris_inst *inst)
767{
768 struct platform_inst_caps *caps;
769
770 if (inst->codec == V4L2_PIX_FMT_H264)
771 return hfi_buffer_persist_h264d();
772 else if (inst->codec == V4L2_PIX_FMT_HEVC)
773 return hfi_buffer_persist_h265d(0);
774 else if (inst->codec == V4L2_PIX_FMT_VP9)
775 return hfi_buffer_persist_vp9d();
776 else if (inst->codec == V4L2_PIX_FMT_AV1) {
777 caps = inst->core->iris_platform_data->inst_caps;
778 if (inst->fw_caps[DRAP].value)
779 return hfi_buffer_persist_av1d(caps->max_frame_width,
780 caps->max_frame_height, 16);
781 else
782 return hfi_buffer_persist_av1d(0, 0, 0);
783 }
784
785 return 0;
786}
787
788static u32 iris_vpu_dec_dpb_size(struct iris_inst *inst)
789{
790 if (iris_split_mode_enabled(inst))
791 return iris_get_buffer_size(inst, BUF_DPB);
792 else
793 return 0;
794}
795
796static u32 iris_vpu_dec_non_comv_size(struct iris_inst *inst)
797{
798 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
799 struct v4l2_format *f = inst->fmt_src;
800 u32 height = f->fmt.pix_mp.height;
801 u32 width = f->fmt.pix_mp.width;
802
803 if (inst->codec == V4L2_PIX_FMT_H264)
804 return hfi_buffer_non_comv_h264d(width, height, num_vpp_pipes);
805 else if (inst->codec == V4L2_PIX_FMT_HEVC)
806 return hfi_buffer_non_comv_h265d(width, height, num_vpp_pipes);
807
808 return 0;
809}
810
811static u32 iris_vpu_dec_line_size(struct iris_inst *inst)
812{
813 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
814 struct v4l2_format *f = inst->fmt_src;
815 u32 height = f->fmt.pix_mp.height;
816 u32 width = f->fmt.pix_mp.width;
817 bool is_opb = false;
818 u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
819
820 if (iris_split_mode_enabled(inst))
821 is_opb = true;
822
823 if (inst->codec == V4L2_PIX_FMT_H264)
824 return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes);
825 else if (inst->codec == V4L2_PIX_FMT_HEVC)
826 return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes);
827 else if (inst->codec == V4L2_PIX_FMT_VP9)
828 return hfi_buffer_line_vp9d(width, height, out_min_count, is_opb,
829 num_vpp_pipes);
830 else if (inst->codec == V4L2_PIX_FMT_AV1)
831 return hfi_buffer_line_av1d(width, height, is_opb, num_vpp_pipes);
832
833 return 0;
834}
835
836static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst)
837{
838 return iris_vpu_dec_comv_size(inst) +
839 iris_vpu_dec_non_comv_size(inst) +
840 iris_vpu_dec_line_size(inst);
841}
842
843static inline u32 iris_vpu_enc_get_bitstream_width(struct iris_inst *inst)
844{
845 if (is_rotation_90_or_270(inst))
846 return inst->fmt_dst->fmt.pix_mp.height;
847 else
848 return inst->fmt_dst->fmt.pix_mp.width;
849}
850
851static inline u32 iris_vpu_enc_get_bitstream_height(struct iris_inst *inst)
852{
853 if (is_rotation_90_or_270(inst))
854 return inst->fmt_dst->fmt.pix_mp.width;
855 else
856 return inst->fmt_dst->fmt.pix_mp.height;
857}
858
859static inline u32 size_bin_bitstream_enc(u32 width, u32 height,
860 u32 rc_type)
861{
862 u32 aligned_height = ALIGN(height, 32);
863 u32 aligned_width = ALIGN(width, 32);
864 u32 frame_size = width * height * 3;
865 u32 mbs_per_frame;
866
867 /*
868 * Encoder output size calculation: 32 Align width/height
869 * For resolution < 720p : YUVsize * 4
870 * For resolution > 720p & <= 4K : YUVsize / 2
871 * For resolution > 4k : YUVsize / 4
872 * Initially frame_size = YUVsize * 2;
873 */
874
875 mbs_per_frame = (ALIGN(aligned_height, 16) * ALIGN(aligned_width, 16)) / 256;
876
877 if (mbs_per_frame < NUM_MBS_720P)
878 frame_size = frame_size << 1;
879 else if (mbs_per_frame <= NUM_MBS_4K)
880 frame_size = frame_size >> 2;
881 else
882 frame_size = frame_size >> 3;
883
884 if (rc_type == HFI_RATE_CONTROL_OFF || rc_type == HFI_RATE_CONTROL_CQ ||
885 rc_type == HFI_RC_OFF || rc_type == HFI_RC_CQ)
886 frame_size = frame_size << 1;
887
888 /*
889 * In case of opaque color format bitdepth will be known
890 * with first ETB, buffers allocated already with 8 bit
891 * won't be sufficient for 10 bit
892 * calculate size considering 10-bit by default
893 * For 10-bit cases size = size * 1.25
894 */
895 frame_size *= 5;
896 frame_size /= 4;
897
898 return ALIGN(frame_size, SZ_4K);
899}
900
901static inline u32 hfi_buffer_bin_enc(u32 width, u32 height,
902 u32 work_mode, u32 lcu_size,
903 u32 num_vpp_pipes, u32 rc_type)
904{
905 u32 sao_bin_buffer_size, padded_bin_size, bitstream_size;
906 u32 total_bitbin_buffers, size_single_pipe, bitbin_size;
907 u32 aligned_height = ALIGN(height, lcu_size);
908 u32 aligned_width = ALIGN(width, lcu_size);
909
910 bitstream_size = size_bin_bitstream_enc(width, height, rc_type);
911 bitstream_size = ALIGN(bitstream_size, 256);
912
913 if (work_mode == STAGE_2) {
914 total_bitbin_buffers = 3;
915 bitbin_size = bitstream_size * 17 / 10;
916 bitbin_size = ALIGN(bitbin_size, 256);
917 } else {
918 total_bitbin_buffers = 1;
919 bitstream_size = aligned_width * aligned_height * 3;
920 bitbin_size = ALIGN(bitstream_size, 256);
921 }
922
923 if (num_vpp_pipes > 2)
924 size_single_pipe = bitbin_size / 2;
925 else
926 size_single_pipe = bitbin_size;
927
928 size_single_pipe = ALIGN(size_single_pipe, 256);
929 sao_bin_buffer_size = (64 * (((width + 32) * (height + 32)) >> 10)) + 384;
930 padded_bin_size = ALIGN(size_single_pipe, 256);
931 size_single_pipe = sao_bin_buffer_size + padded_bin_size;
932 size_single_pipe = ALIGN(size_single_pipe, 256);
933 bitbin_size = size_single_pipe * num_vpp_pipes;
934
935 return ALIGN(bitbin_size, 256) * total_bitbin_buffers + 512;
936}
937
938static u32 iris_vpu_enc_bin_size(struct iris_inst *inst)
939{
940 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
941 u32 height = iris_vpu_enc_get_bitstream_height(inst);
942 u32 width = iris_vpu_enc_get_bitstream_width(inst);
943 u32 stage = inst->fw_caps[STAGE].value;
944 u32 lcu_size;
945
946 if (inst->codec == V4L2_PIX_FMT_HEVC)
947 lcu_size = 32;
948 else
949 lcu_size = 16;
950
951 return hfi_buffer_bin_enc(width, height, stage, lcu_size,
952 num_vpp_pipes, inst->hfi_rc_type);
953}
954
955static inline u32 hfi_buffer_get_recon_count(struct iris_inst *inst)
956{
957 u32 layer_count = inst->hfi_layer_count;
958 u32 layer_type = inst->hfi_layer_type;
959 u32 bframe_count, ltr_count;
960 u32 num_ref = 1;
961
962 bframe_count = inst->fw_caps[B_FRAME].value;
963 ltr_count = inst->fw_caps[LTR_COUNT].value;
964
965 if (bframe_count)
966 num_ref = 2;
967
968 /* The shift operation here is rounding logic, similar to [(x+1)/2]. */
969 if (layer_type == HFI_HIER_P_HYBRID_LTR)
970 num_ref = (layer_count + 1) >> 1;
971
972 if (layer_type == HFI_HIER_P_SLIDING_WINDOW) {
973 if (inst->codec == V4L2_PIX_FMT_HEVC)
974 num_ref = (layer_count + 1) >> 1;
975 else if (inst->codec == V4L2_PIX_FMT_H264 && layer_count < 4)
976 num_ref = (layer_count - 1);
977 else
978 num_ref = layer_count;
979 }
980
981 if (ltr_count)
982 num_ref = num_ref + ltr_count;
983
984 /*
985 * The expression (1 << layers - 2) + 1 accounts for the number of reference
986 * frames in the Adaptive Hierarchical B-frame encoding case. In this scheme,
987 * the number of frames in a sub-GOP is related to (2^(number of layers) - 1),
988 * hence the use of the shift operation.
989 */
990 if (layer_type == HFI_HIER_B) {
991 if (inst->codec == V4L2_PIX_FMT_HEVC)
992 num_ref = layer_count;
993 else
994 num_ref = (1 << (layer_count - 2)) + 1;
995 }
996
997 return num_ref;
998}
999
1000static u32 iris_vpu_dec_partial_size(struct iris_inst *inst)
1001{
1002 struct v4l2_format *f = inst->fmt_src;
1003 u32 height = f->fmt.pix_mp.height;
1004 u32 width = f->fmt.pix_mp.width;
1005
1006 return hfi_buffer_ibc_av1d(width, height);
1007}
1008
1009static inline
1010u32 hfi_buffer_comv_enc(u32 frame_width, u32 frame_height, u32 lcu_size,
1011 u32 num_recon, u32 standard)
1012{
1013 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size);
1014 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size);
1015 u32 num_lcu_in_frame = width_in_lcus * height_in_lcus;
1016 u32 mb_height = ((frame_height) + 15) >> 4;
1017 u32 mb_width = ((frame_width) + 15) >> 4;
1018 u32 size_colloc_mv, size_colloc_rc;
1019
1020 size_colloc_mv = (standard == HFI_CODEC_ENCODE_HEVC) ?
1021 (16 * ((num_lcu_in_frame << 2) + 32)) :
1022 (3 * 16 * (width_in_lcus * height_in_lcus + 32));
1023 size_colloc_mv = ALIGN(size_colloc_mv, 256) * num_recon;
1024 size_colloc_rc = (((mb_width + 7) >> 3) * 16 * 2 * mb_height);
1025 size_colloc_rc = ALIGN(size_colloc_rc, 256) * HFI_MAX_COL_FRAME;
1026
1027 return size_colloc_mv + size_colloc_rc;
1028}
1029
1030static u32 iris_vpu_enc_comv_size(struct iris_inst *inst)
1031{
1032 u32 height = iris_vpu_enc_get_bitstream_height(inst);
1033 u32 width = iris_vpu_enc_get_bitstream_width(inst);
1034 u32 num_recon = hfi_buffer_get_recon_count(inst);
1035 u32 codec, lcu_size;
1036
1037 codec = (inst->codec == V4L2_PIX_FMT_HEVC) ?
1038 HFI_CODEC_ENCODE_HEVC : HFI_CODEC_ENCODE_AVC;
1039 lcu_size = (inst->codec == V4L2_PIX_FMT_HEVC) ? 32 : 16;
1040
1041 return hfi_buffer_comv_enc(width, height, lcu_size, num_recon + 1, codec);
1042}
1043
1044static inline
1045u32 size_frame_rc_buf_size(u32 standard, u32 frame_height_coded,
1046 u32 num_vpp_pipes_enc)
1047{
1048 u32 size = 0;
1049
1050 size = (standard == HFI_CODEC_ENCODE_HEVC) ?
1051 (256 + 16 * (14 + ((((frame_height_coded) >> 5) + 7) >> 3))) :
1052 (256 + 16 * (14 + ((((frame_height_coded) >> 4) + 7) >> 3)));
1053 size *= 11;
1054
1055 if (num_vpp_pipes_enc > 1)
1056 size = ALIGN(size, 256) * num_vpp_pipes_enc;
1057
1058 return ALIGN(size, 512) * HFI_MAX_COL_FRAME;
1059}
1060
1061static inline
1062u32 size_enc_slice_info_buf(u32 num_lcu_in_frame)
1063{
1064 return ALIGN((256 + (num_lcu_in_frame << 4)), 256);
1065}
1066
1067static inline u32 enc_bitcnt_buf_size(u32 num_lcu_in_frame)
1068{
1069 return ALIGN((256 + (4 * (num_lcu_in_frame))), 256);
1070}
1071
1072static inline u32 enc_bitmap_buf_size(u32 num_lcu_in_frame)
1073{
1074 return ALIGN((256 + ((num_lcu_in_frame) >> 3)), 256);
1075}
1076
1077static inline u32 size_override_buf(u32 num_lcumb)
1078{
1079 return ALIGN(((16 * (((num_lcumb) + 7) >> 3))), 256) * 2;
1080}
1081
1082static inline u32 size_ir_buf(u32 num_lcu_in_frame)
1083{
1084 return ALIGN((((((num_lcu_in_frame) << 1) + 7) & (~7)) * 3), 256);
1085}
1086
1087static inline
1088u32 size_linebuff_data(bool is_ten_bit, u32 frame_width_coded)
1089{
1090 return is_ten_bit ?
1091 (((((10 * (frame_width_coded) + 1024) + (256 - 1)) &
1092 (~(256 - 1))) * 1) +
1093 (((((10 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) &
1094 (~(256 - 1))) * 2)) :
1095 (((((8 * (frame_width_coded) + 1024) + (256 - 1)) &
1096 (~(256 - 1))) * 1) +
1097 (((((8 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) &
1098 (~(256 - 1))) * 2));
1099}
1100
1101static inline
1102u32 size_left_linebuff_ctrl(u32 standard, u32 frame_height_coded,
1103 u32 num_vpp_pipes_enc)
1104{
1105 u32 size = 0;
1106
1107 size = standard == HFI_CODEC_ENCODE_HEVC ?
1108 (((frame_height_coded) +
1109 (32)) / 32 * 4 * 16) :
1110 (((frame_height_coded) + 15) / 16 * 5 * 16);
1111
1112 if ((num_vpp_pipes_enc) > 1) {
1113 size += 512;
1114 size = ALIGN(size, 512) *
1115 num_vpp_pipes_enc;
1116 }
1117
1118 return ALIGN(size, 256);
1119}
1120
1121static inline
1122u32 size_left_linebuff_recon_pix(bool is_ten_bit, u32 frame_height_coded,
1123 u32 num_vpp_pipes_enc)
1124{
1125 return (((is_ten_bit + 1) * 2 * (frame_height_coded) + 256) +
1126 (256 << (num_vpp_pipes_enc - 1)) - 1) &
1127 (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1;
1128}
1129
1130static inline
1131u32 size_top_linebuff_ctrl_fe(u32 frame_width_coded, u32 standard)
1132{
1133 return standard == HFI_CODEC_ENCODE_HEVC ?
1134 ALIGN((64 * ((frame_width_coded) >> 5)), 256) :
1135 ALIGN((256 + 16 * ((frame_width_coded) >> 4)), 256);
1136}
1137
1138static inline
1139u32 size_left_linebuff_ctrl_fe(u32 frame_height_coded, u32 num_vpp_pipes_enc)
1140{
1141 return (((256 + 64 * ((frame_height_coded) >> 4)) +
1142 (256 << (num_vpp_pipes_enc - 1)) - 1) &
1143 (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1) *
1144 num_vpp_pipes_enc;
1145}
1146
1147static inline
1148u32 size_left_linebuff_metadata_recon_y(u32 frame_height_coded,
1149 bool is_ten_bit,
1150 u32 num_vpp_pipes_enc)
1151{
1152 return ALIGN(((256 + 64 * ((frame_height_coded) /
1153 (8 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc;
1154}
1155
1156static inline
1157u32 size_left_linebuff_metadata_recon_uv(u32 frame_height_coded,
1158 bool is_ten_bit,
1159 u32 num_vpp_pipes_enc)
1160{
1161 return ALIGN(((256 + 64 * ((frame_height_coded) /
1162 (4 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc;
1163}
1164
1165static inline
1166u32 size_linebuff_recon_pix(bool is_ten_bit, u32 frame_width_coded)
1167{
1168 return ALIGN(((is_ten_bit ? 3 : 2) * (frame_width_coded)), 256);
1169}
1170
1171static inline
1172u32 size_line_buf_ctrl(u32 frame_width_coded)
1173{
1174 return ALIGN(frame_width_coded, 256);
1175}
1176
1177static inline
1178u32 size_line_buf_ctrl_id2(u32 frame_width_coded)
1179{
1180 return ALIGN(frame_width_coded, 256);
1181}
1182
1183static inline u32 size_line_buf_sde(u32 frame_width_coded)
1184{
1185 return ALIGN((256 + (16 * ((frame_width_coded) >> 4))), 256);
1186}
1187
1188static inline
1189u32 size_vpss_line_buf(u32 num_vpp_pipes_enc, u32 frame_height_coded,
1190 u32 frame_width_coded)
1191{
1192 return ALIGN(((((((8192) >> 2) << 5) * (num_vpp_pipes_enc)) + 64) +
1193 (((((max_t(u32, (frame_width_coded),
1194 (frame_height_coded)) + 3) >> 2) << 5) + 256) * 16)), 256);
1195}
1196static inline
1197u32 size_vpss_line_buf_vpu33(u32 num_vpp_pipes_enc, u32 frame_height_coded,
1198 u32 frame_width_coded)
1199{
1200 u32 vpss_4tap_top, vpss_4tap_left, vpss_div2_top;
1201 u32 vpss_div2_left, vpss_top_lb, vpss_left_lb;
1202 u32 size_left, size_top;
1203 u32 max_width_height;
1204
1205 max_width_height = max_t(u32, frame_width_coded, frame_height_coded);
1206 vpss_4tap_top = ((((max_width_height * 2) + 3) >> 2) << 4) + 256;
1207 vpss_4tap_left = (((8192 + 3) >> 2) << 5) + 64;
1208 vpss_div2_top = (((max_width_height + 3) >> 2) << 4) + 256;
1209 vpss_div2_left = ((((max_width_height * 2) + 3) >> 2) << 5) + 64;
1210 vpss_top_lb = (frame_width_coded + 1) << 3;
1211 vpss_left_lb = (frame_height_coded << 3) * num_vpp_pipes_enc;
1212 size_left = (vpss_4tap_left + vpss_div2_left) * 2 * num_vpp_pipes_enc;
1213 size_top = (vpss_4tap_top + vpss_div2_top) * 2;
1214
1215 return ALIGN(size_left + size_top + vpss_top_lb + vpss_left_lb, DMA_ALIGNMENT);
1216}
1217
1218static inline
1219u32 size_top_line_buf_first_stg_sao(u32 frame_width_coded)
1220{
1221 return ALIGN((16 * ((frame_width_coded) >> 5)), 256);
1222}
1223
1224static inline
1225u32 size_enc_ref_buffer(u32 frame_width, u32 frame_height)
1226{
1227 u32 u_chroma_buffer_height = ALIGN(frame_height >> 1, 32);
1228 u32 u_buffer_height = ALIGN(frame_height, 32);
1229 u32 u_buffer_width = ALIGN(frame_width, 32);
1230
1231 return (u_buffer_height + u_chroma_buffer_height) * u_buffer_width;
1232}
1233
1234static inline
1235u32 size_enc_ten_bit_ref_buffer(u32 frame_width, u32 frame_height)
1236{
1237 u32 ref_luma_stride_in_bytes = ((frame_width + SYSTEM_LAL_TILE10 - 1) / SYSTEM_LAL_TILE10) *
1238 SYSTEM_LAL_TILE10;
1239 u32 ref_buf_height = (frame_height + (32 - 1)) & (~(32 - 1));
1240 u32 u_ref_stride, luma_size;
1241 u32 ref_chrm_height_in_bytes;
1242 u32 chroma_size;
1243
1244 u_ref_stride = 4 * (ref_luma_stride_in_bytes / 3);
1245 u_ref_stride = (u_ref_stride + (128 - 1)) & (~(128 - 1));
1246 luma_size = ref_buf_height * u_ref_stride;
1247 luma_size = (luma_size + (4096 - 1)) & (~(4096 - 1));
1248
1249 ref_chrm_height_in_bytes = (((frame_height + 1) >> 1) + (32 - 1)) & (~(32 - 1));
1250 chroma_size = u_ref_stride * ref_chrm_height_in_bytes;
1251 chroma_size = (chroma_size + (4096 - 1)) & (~(4096 - 1));
1252
1253 return luma_size + chroma_size;
1254}
1255
1256static inline
1257u32 hfi_ubwc_calc_metadata_plane_stride(u32 frame_width,
1258 u32 metadata_stride_multiple,
1259 u32 tile_width_in_pels)
1260{
1261 return ALIGN(((frame_width + (tile_width_in_pels - 1)) / tile_width_in_pels),
1262 metadata_stride_multiple);
1263}
1264
1265static inline
1266u32 hfi_ubwc_metadata_plane_bufheight(u32 frame_height,
1267 u32 metadata_height_multiple,
1268 u32 tile_height_in_pels)
1269{
1270 return ALIGN(((frame_height + (tile_height_in_pels - 1)) / tile_height_in_pels),
1271 metadata_height_multiple);
1272}
1273
1274static inline
1275u32 hfi_ubwc_metadata_plane_buffer_size(u32 _metadata_tride, u32 _metadata_buf_height)
1276{
1277 return ALIGN(_metadata_tride * _metadata_buf_height, 4096);
1278}
1279
1280static inline
1281u32 hfi_buffer_non_comv_enc(u32 frame_width, u32 frame_height,
1282 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard)
1283{
1284 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size);
1285 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size);
1286 u32 num_lcu_in_frame = width_in_lcus * height_in_lcus;
1287 u32 frame_height_coded = height_in_lcus * (lcu_size);
1288 u32 frame_width_coded = width_in_lcus * (lcu_size);
1289 u32 num_lcumb, frame_rc_buf_size;
1290
1291 num_lcumb = (frame_height_coded / lcu_size) *
1292 ((frame_width_coded + lcu_size * 8) / lcu_size);
1293 frame_rc_buf_size = size_frame_rc_buf_size(standard, frame_height_coded,
1294 num_vpp_pipes_enc);
1295 return size_enc_slice_info_buf(num_lcu_in_frame) +
1296 SIZE_SLICE_CMD_BUFFER +
1297 SIZE_SPS_PPS_SLICE_HDR +
1298 frame_rc_buf_size +
1299 enc_bitcnt_buf_size(num_lcu_in_frame) +
1300 enc_bitmap_buf_size(num_lcu_in_frame) +
1301 SIZE_BSE_SLICE_CMD_BUF +
1302 SIZE_LAMBDA_LUT +
1303 size_override_buf(num_lcumb) +
1304 size_ir_buf(num_lcu_in_frame);
1305}
1306
1307static u32 iris_vpu_enc_non_comv_size(struct iris_inst *inst)
1308{
1309 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
1310 u32 height = iris_vpu_enc_get_bitstream_height(inst);
1311 u32 width = iris_vpu_enc_get_bitstream_width(inst);
1312 u32 lcu_size = 16;
1313
1314 if (inst->codec == V4L2_PIX_FMT_HEVC) {
1315 lcu_size = 32;
1316 return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes,
1317 lcu_size, HFI_CODEC_ENCODE_HEVC) +
1318 SIZE_ONE_SLICE_BUF;
1319 }
1320
1321 return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes,
1322 lcu_size, HFI_CODEC_ENCODE_AVC);
1323}
1324
1325static inline
1326u32 hfi_buffer_line_enc_base(u32 frame_width, u32 frame_height, bool is_ten_bit,
1327 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard)
1328{
1329 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size);
1330 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size);
1331 u32 frame_height_coded = height_in_lcus * (lcu_size);
1332 u32 frame_width_coded = width_in_lcus * (lcu_size);
1333 u32 line_buff_data_size, left_line_buff_ctrl_size;
1334 u32 left_line_buff_metadata_recon__uv__size;
1335 u32 left_line_buff_metadata_recon__y__size;
1336 u32 left_line_buff_recon_pix_size;
1337 u32 top_line_buff_ctrl_fe_size;
1338 u32 line_buff_recon_pix_size;
1339
1340 line_buff_data_size = size_linebuff_data(is_ten_bit, frame_width_coded);
1341 left_line_buff_ctrl_size =
1342 size_left_linebuff_ctrl(standard, frame_height_coded, num_vpp_pipes_enc);
1343 left_line_buff_recon_pix_size =
1344 size_left_linebuff_recon_pix(is_ten_bit, frame_height_coded,
1345 num_vpp_pipes_enc);
1346 top_line_buff_ctrl_fe_size =
1347 size_top_linebuff_ctrl_fe(frame_width_coded, standard);
1348 left_line_buff_metadata_recon__y__size =
1349 size_left_linebuff_metadata_recon_y(frame_height_coded, is_ten_bit,
1350 num_vpp_pipes_enc);
1351 left_line_buff_metadata_recon__uv__size =
1352 size_left_linebuff_metadata_recon_uv(frame_height_coded, is_ten_bit,
1353 num_vpp_pipes_enc);
1354 line_buff_recon_pix_size = size_linebuff_recon_pix(is_ten_bit, frame_width_coded);
1355
1356 return size_line_buf_ctrl(frame_width_coded) +
1357 size_line_buf_ctrl_id2(frame_width_coded) +
1358 line_buff_data_size +
1359 left_line_buff_ctrl_size +
1360 left_line_buff_recon_pix_size +
1361 top_line_buff_ctrl_fe_size +
1362 left_line_buff_metadata_recon__y__size +
1363 left_line_buff_metadata_recon__uv__size +
1364 line_buff_recon_pix_size +
1365 size_left_linebuff_ctrl_fe(frame_height_coded, num_vpp_pipes_enc) +
1366 size_line_buf_sde(frame_width_coded) +
1367 size_top_line_buf_first_stg_sao(frame_width_coded);
1368}
1369
1370static inline
1371u32 hfi_buffer_line_enc(u32 frame_width, u32 frame_height, bool is_ten_bit,
1372 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard)
1373{
1374 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size);
1375 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size);
1376 u32 frame_height_coded = height_in_lcus * (lcu_size);
1377 u32 frame_width_coded = width_in_lcus * (lcu_size);
1378
1379 return hfi_buffer_line_enc_base(frame_width, frame_height, is_ten_bit,
1380 num_vpp_pipes_enc, lcu_size, standard) +
1381 size_vpss_line_buf(num_vpp_pipes_enc, frame_height_coded, frame_width_coded);
1382}
1383
1384static inline
1385u32 hfi_buffer_line_enc_vpu33(u32 frame_width, u32 frame_height, bool is_ten_bit,
1386 u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard)
1387{
1388 u32 width_in_lcus = ((frame_width) + (lcu_size) - 1) / (lcu_size);
1389 u32 height_in_lcus = ((frame_height) + (lcu_size) - 1) / (lcu_size);
1390 u32 frame_height_coded = height_in_lcus * (lcu_size);
1391 u32 frame_width_coded = width_in_lcus * (lcu_size);
1392
1393 return hfi_buffer_line_enc_base(frame_width, frame_height, is_ten_bit,
1394 num_vpp_pipes_enc, lcu_size, standard) +
1395 size_vpss_line_buf_vpu33(num_vpp_pipes_enc, frame_height_coded,
1396 frame_width_coded);
1397}
1398
1399static u32 iris_vpu_enc_line_size(struct iris_inst *inst)
1400{
1401 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
1402 u32 height = iris_vpu_enc_get_bitstream_height(inst);
1403 u32 width = iris_vpu_enc_get_bitstream_width(inst);
1404 u32 lcu_size = 16;
1405
1406 if (inst->codec == V4L2_PIX_FMT_HEVC) {
1407 lcu_size = 32;
1408 return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes,
1409 lcu_size, HFI_CODEC_ENCODE_HEVC);
1410 }
1411
1412 return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes,
1413 lcu_size, HFI_CODEC_ENCODE_AVC);
1414}
1415
1416static u32 iris_vpu33_enc_line_size(struct iris_inst *inst)
1417{
1418 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
1419 u32 height = iris_vpu_enc_get_bitstream_height(inst);
1420 u32 width = iris_vpu_enc_get_bitstream_width(inst);
1421 u32 lcu_size = 16;
1422
1423 if (inst->codec == V4L2_PIX_FMT_HEVC) {
1424 lcu_size = 32;
1425 return hfi_buffer_line_enc_vpu33(width, height, 0, num_vpp_pipes,
1426 lcu_size, HFI_CODEC_ENCODE_HEVC);
1427 }
1428
1429 return hfi_buffer_line_enc_vpu33(width, height, 0, num_vpp_pipes,
1430 lcu_size, HFI_CODEC_ENCODE_AVC);
1431}
1432
1433static inline
1434u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_height, bool is_ten_bit)
1435{
1436 u32 metadata_stride, metadata_buf_height, meta_size_y, meta_size_c;
1437 u32 ten_bit_ref_buf_size = 0, ref_buf_size = 0;
1438 u32 size;
1439
1440 if (!is_ten_bit) {
1441 ref_buf_size = size_enc_ref_buffer(frame_width, frame_height);
1442 metadata_stride =
1443 hfi_ubwc_calc_metadata_plane_stride(frame_width, 64,
1444 HFI_COL_FMT_NV12C_Y_TILE_WIDTH);
1445 metadata_buf_height =
1446 hfi_ubwc_metadata_plane_bufheight(frame_height, 16,
1447 HFI_COL_FMT_NV12C_Y_TILE_HEIGHT);
1448 meta_size_y =
1449 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height);
1450 meta_size_c =
1451 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height);
1452 size = ref_buf_size + meta_size_y + meta_size_c;
1453 } else {
1454 ten_bit_ref_buf_size = size_enc_ten_bit_ref_buffer(frame_width, frame_height);
1455 metadata_stride =
1456 hfi_ubwc_calc_metadata_plane_stride(frame_width,
1457 IRIS_METADATA_STRIDE_MULTIPLE,
1458 HFI_COL_FMT_TP10C_Y_TILE_WIDTH);
1459 metadata_buf_height =
1460 hfi_ubwc_metadata_plane_bufheight(frame_height,
1461 IRIS_METADATA_HEIGHT_MULTIPLE,
1462 HFI_COL_FMT_TP10C_Y_TILE_HEIGHT);
1463 meta_size_y =
1464 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height);
1465 meta_size_c =
1466 hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_height);
1467 size = ten_bit_ref_buf_size + meta_size_y + meta_size_c;
1468 }
1469
1470 return size;
1471}
1472
1473static u32 iris_vpu_enc_arp_size(struct iris_inst *inst)
1474{
1475 return HFI_BUFFER_ARP_ENC;
1476}
1477
1478inline bool is_scaling_enabled(struct iris_inst *inst)
1479{
1480 struct v4l2_pix_format_mplane *dst_fmt = &inst->fmt_dst->fmt.pix_mp;
1481 struct v4l2_pix_format_mplane *src_fmt = &inst->fmt_src->fmt.pix_mp;
1482
1483 return dst_fmt->width != src_fmt->width ||
1484 dst_fmt->height != src_fmt->height;
1485}
1486
1487static inline
1488u32 hfi_buffer_vpss_enc(u32 dswidth, u32 dsheight, bool ds_enable,
1489 u32 blur, bool is_ten_bit)
1490{
1491 if (ds_enable || blur)
1492 return hfi_buffer_dpb_enc(dswidth, dsheight, is_ten_bit);
1493
1494 return 0;
1495}
1496
1497static inline u32 hfi_buffer_scratch1_enc(u32 frame_width, u32 frame_height,
1498 u32 lcu_size, u32 num_ref,
1499 bool ten_bit, u32 num_vpp_pipes,
1500 bool is_h265)
1501{
1502 u32 line_buf_ctrl_size, line_buf_data_size, leftline_buf_ctrl_size;
1503 u32 line_buf_sde_size, sps_pps_slice_hdr, topline_buf_ctrl_size_FE;
1504 u32 leftline_buf_ctrl_size_FE, line_buf_recon_pix_size;
1505 u32 leftline_buf_recon_pix_size, lambda_lut_size, override_buffer_size;
1506 u32 col_mv_buf_size, vpp_reg_buffer_size, ir_buffer_size;
1507 u32 vpss_line_buf, leftline_buf_meta_recony, h265e_colrcbuf_size;
1508 u32 h265e_framerc_bufsize, h265e_lcubitcnt_bufsize;
1509 u32 h265e_lcubitmap_bufsize, se_stats_bufsize;
1510 u32 bse_reg_buffer_size, bse_slice_cmd_buffer_size, slice_info_bufsize;
1511 u32 line_buf_ctrl_size_buffid2, slice_cmd_buffer_size;
1512 u32 width_lcu_num, height_lcu_num, width_coded, height_coded;
1513 u32 frame_num_lcu, linebuf_meta_recon_uv, topline_bufsize_fe_1stg_sao;
1514 u32 vpss_line_buffer_size_1;
1515 u32 bit_depth, num_lcu_mb;
1516
1517 width_lcu_num = (frame_width + lcu_size - 1) / lcu_size;
1518 height_lcu_num = (frame_height + lcu_size - 1) / lcu_size;
1519 frame_num_lcu = width_lcu_num * height_lcu_num;
1520 width_coded = width_lcu_num * lcu_size;
1521 height_coded = height_lcu_num * lcu_size;
1522 num_lcu_mb = (height_coded / lcu_size) *
1523 ((width_coded + lcu_size * 8) / lcu_size);
1524 slice_info_bufsize = 256 + (frame_num_lcu << 4);
1525 slice_info_bufsize = ALIGN(slice_info_bufsize, 256);
1526 line_buf_ctrl_size = ALIGN(width_coded, 256);
1527 line_buf_ctrl_size_buffid2 = ALIGN(width_coded, 256);
1528
1529 bit_depth = ten_bit ? 10 : 8;
1530 line_buf_data_size =
1531 (((((bit_depth * width_coded + 1024) + (256 - 1)) &
1532 (~(256 - 1))) * 1) +
1533 (((((bit_depth * width_coded + 1024) >> 1) + (256 - 1)) &
1534 (~(256 - 1))) * 2));
1535
1536 leftline_buf_ctrl_size = is_h265 ? ((height_coded + 32) / 32 * 4 * 16) :
1537 ((height_coded + 15) / 16 * 5 * 16);
1538
1539 if (num_vpp_pipes > 1) {
1540 leftline_buf_ctrl_size += 512;
1541 leftline_buf_ctrl_size =
1542 ALIGN(leftline_buf_ctrl_size, 512) * num_vpp_pipes;
1543 }
1544
1545 leftline_buf_ctrl_size = ALIGN(leftline_buf_ctrl_size, 256);
1546 leftline_buf_recon_pix_size =
1547 (((ten_bit + 1) * 2 * (height_coded) + 256) +
1548 (256 << (num_vpp_pipes - 1)) - 1) &
1549 (~((256 << (num_vpp_pipes - 1)) - 1)) * 1;
1550
1551 topline_buf_ctrl_size_FE = is_h265 ? (64 * (width_coded >> 5)) :
1552 (256 + 16 * (width_coded >> 4));
1553 topline_buf_ctrl_size_FE = ALIGN(topline_buf_ctrl_size_FE, 256);
1554 leftline_buf_ctrl_size_FE =
1555 (((256 + 64 * (height_coded >> 4)) +
1556 (256 << (num_vpp_pipes - 1)) - 1) &
1557 (~((256 << (num_vpp_pipes - 1)) - 1)) * 1) *
1558 num_vpp_pipes;
1559 leftline_buf_meta_recony =
1560 (256 + 64 * ((height_coded) / (8 * (ten_bit ? 4 : 8))));
1561 leftline_buf_meta_recony = ALIGN(leftline_buf_meta_recony, 256);
1562 leftline_buf_meta_recony = leftline_buf_meta_recony * num_vpp_pipes;
1563 linebuf_meta_recon_uv =
1564 (256 + 64 * ((height_coded) / (4 * (ten_bit ? 4 : 8))));
1565 linebuf_meta_recon_uv = ALIGN(linebuf_meta_recon_uv, 256);
1566 linebuf_meta_recon_uv = linebuf_meta_recon_uv * num_vpp_pipes;
1567 line_buf_recon_pix_size = ((ten_bit ? 3 : 2) * width_coded);
1568 line_buf_recon_pix_size = ALIGN(line_buf_recon_pix_size, 256);
1569 slice_cmd_buffer_size = ALIGN(20480, 256);
1570 sps_pps_slice_hdr = 2048 + 4096;
1571 col_mv_buf_size =
1572 is_h265 ? (16 * ((frame_num_lcu << 2) + 32)) :
1573 (3 * 16 * (width_lcu_num * height_lcu_num + 32));
1574 col_mv_buf_size = ALIGN(col_mv_buf_size, 256) * (num_ref + 1);
1575 h265e_colrcbuf_size =
1576 (((width_lcu_num + 7) >> 3) * 16 * 2 * height_lcu_num);
1577 if (num_vpp_pipes > 1)
1578 h265e_colrcbuf_size =
1579 ALIGN(h265e_colrcbuf_size, 256) * num_vpp_pipes;
1580
1581 h265e_colrcbuf_size =
1582 ALIGN(h265e_colrcbuf_size, 256) * HFI_MAX_COL_FRAME;
1583 h265e_framerc_bufsize =
1584 (is_h265) ?
1585 (256 + 16 * (14 + (((height_coded >> 5) + 7) >> 3))) :
1586 (256 + 16 * (14 + (((height_coded >> 4) + 7) >> 3)));
1587 h265e_framerc_bufsize *= 6;
1588 if (num_vpp_pipes > 1)
1589 h265e_framerc_bufsize =
1590 ALIGN(h265e_framerc_bufsize, 256) * num_vpp_pipes;
1591
1592 h265e_framerc_bufsize =
1593 ALIGN(h265e_framerc_bufsize, 512) * HFI_MAX_COL_FRAME;
1594 h265e_lcubitcnt_bufsize = 256 + 4 * frame_num_lcu;
1595 h265e_lcubitcnt_bufsize = ALIGN(h265e_lcubitcnt_bufsize, 256);
1596 h265e_lcubitmap_bufsize = 256 + (frame_num_lcu >> 3);
1597 h265e_lcubitmap_bufsize = ALIGN(h265e_lcubitmap_bufsize, 256);
1598 line_buf_sde_size = 256 + 16 * (width_coded >> 4);
1599 line_buf_sde_size = ALIGN(line_buf_sde_size, 256);
1600 if ((width_coded * height_coded) > (4096 * 2160))
1601 se_stats_bufsize = 0;
1602 else if ((width_coded * height_coded) > (1920 * 1088))
1603 se_stats_bufsize = (40 * 4 * frame_num_lcu + 256 + 256);
1604 else
1605 se_stats_bufsize = (1024 * frame_num_lcu + 256 + 256);
1606
1607 se_stats_bufsize = ALIGN(se_stats_bufsize, 256) * 2;
1608 bse_slice_cmd_buffer_size = (((8192 << 2) + 7) & (~7)) * 6;
1609 bse_reg_buffer_size = (((512 << 3) + 7) & (~7)) * 4;
1610 vpp_reg_buffer_size = (((2048 << 3) + 31) & (~31)) * 10;
1611 lambda_lut_size = 256 * 11;
1612 override_buffer_size = 16 * ((num_lcu_mb + 7) >> 3);
1613 override_buffer_size = ALIGN(override_buffer_size, 256) * 2;
1614 ir_buffer_size = (((frame_num_lcu << 1) + 7) & (~7)) * 3;
1615 vpss_line_buffer_size_1 = (((8192 >> 2) << 5) * num_vpp_pipes) + 64;
1616 vpss_line_buf =
1617 (((((max(width_coded, height_coded) + 3) >> 2) << 5) + 256) *
1618 16) +
1619 vpss_line_buffer_size_1;
1620 topline_bufsize_fe_1stg_sao = 16 * (width_coded >> 5);
1621 topline_bufsize_fe_1stg_sao = ALIGN(topline_bufsize_fe_1stg_sao, 256);
1622
1623 return line_buf_ctrl_size + line_buf_data_size +
1624 line_buf_ctrl_size_buffid2 + leftline_buf_ctrl_size +
1625 vpss_line_buf + col_mv_buf_size + topline_buf_ctrl_size_FE +
1626 leftline_buf_ctrl_size_FE + line_buf_recon_pix_size +
1627 leftline_buf_recon_pix_size + leftline_buf_meta_recony +
1628 linebuf_meta_recon_uv + h265e_colrcbuf_size +
1629 h265e_framerc_bufsize + h265e_lcubitcnt_bufsize +
1630 h265e_lcubitmap_bufsize + line_buf_sde_size +
1631 topline_bufsize_fe_1stg_sao + override_buffer_size +
1632 bse_reg_buffer_size + vpp_reg_buffer_size + sps_pps_slice_hdr +
1633 slice_cmd_buffer_size + bse_slice_cmd_buffer_size +
1634 ir_buffer_size + slice_info_bufsize + lambda_lut_size +
1635 se_stats_bufsize + 1024;
1636}
1637
1638static u32 iris_vpu_enc_scratch1_size(struct iris_inst *inst)
1639{
1640 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
1641 u32 frame_height = iris_vpu_enc_get_bitstream_height(inst);
1642 u32 frame_width = iris_vpu_enc_get_bitstream_width(inst);
1643 u32 num_ref = 1;
1644 u32 lcu_size;
1645 bool is_h265;
1646
1647 if (inst->codec == V4L2_PIX_FMT_H264) {
1648 lcu_size = 16;
1649 is_h265 = false;
1650 } else if (inst->codec == V4L2_PIX_FMT_HEVC) {
1651 lcu_size = 32;
1652 is_h265 = true;
1653 } else {
1654 return 0;
1655 }
1656
1657 return hfi_buffer_scratch1_enc(frame_width, frame_height, lcu_size,
1658 num_ref, false, num_vpp_pipes, is_h265);
1659}
1660
1661static inline u32 ubwc_metadata_plane_stride(u32 width,
1662 u32 metadata_stride_multi,
1663 u32 tile_width_pels)
1664{
1665 return ALIGN(((width + (tile_width_pels - 1)) / tile_width_pels),
1666 metadata_stride_multi);
1667}
1668
1669static inline u32 ubwc_metadata_plane_bufheight(u32 height,
1670 u32 metadata_height_multi,
1671 u32 tile_height_pels)
1672{
1673 return ALIGN(((height + (tile_height_pels - 1)) / tile_height_pels),
1674 metadata_height_multi);
1675}
1676
1677static inline u32 ubwc_metadata_plane_buffer_size(u32 metadata_stride,
1678 u32 metadata_buf_height)
1679{
1680 return ALIGN(metadata_stride * metadata_buf_height, SZ_4K);
1681}
1682
1683static inline u32 hfi_buffer_scratch2_enc(u32 frame_width, u32 frame_height,
1684 u32 num_ref, bool ten_bit)
1685{
1686 u32 aligned_width, aligned_height, chroma_height, ref_buf_height;
1687 u32 metadata_stride, meta_buf_height, meta_size_y, meta_size_c;
1688 u32 ref_luma_stride_bytes, ref_chroma_height_bytes;
1689 u32 ref_buf_size, ref_stride;
1690 u32 luma_size, chroma_size;
1691 u32 size;
1692
1693 if (!ten_bit) {
1694 aligned_height = ALIGN(frame_height, 32);
1695 chroma_height = frame_height >> 1;
1696 chroma_height = ALIGN(chroma_height, 32);
1697 aligned_width = ALIGN(frame_width, 128);
1698 metadata_stride =
1699 ubwc_metadata_plane_stride(frame_width, 64, 32);
1700 meta_buf_height =
1701 ubwc_metadata_plane_bufheight(frame_height, 16, 8);
1702 meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride,
1703 meta_buf_height);
1704 meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride,
1705 meta_buf_height);
1706 size = (aligned_height + chroma_height) * aligned_width +
1707 meta_size_y + meta_size_c;
1708 size = (size * (num_ref + 3)) + 4096;
1709 } else {
1710 ref_buf_height = (frame_height + (32 - 1)) & (~(32 - 1));
1711 ref_luma_stride_bytes = ((frame_width + 192 - 1) / 192) * 192;
1712 ref_stride = 4 * (ref_luma_stride_bytes / 3);
1713 ref_stride = (ref_stride + (128 - 1)) & (~(128 - 1));
1714 luma_size = ref_buf_height * ref_stride;
1715 ref_chroma_height_bytes =
1716 (((frame_height + 1) >> 1) + (32 - 1)) & (~(32 - 1));
1717 chroma_size = ref_stride * ref_chroma_height_bytes;
1718 luma_size = (luma_size + (SZ_4K - 1)) & (~(SZ_4K - 1));
1719 chroma_size = (chroma_size + (SZ_4K - 1)) & (~(SZ_4K - 1));
1720 ref_buf_size = luma_size + chroma_size;
1721 metadata_stride =
1722 ubwc_metadata_plane_stride(frame_width, 64, 48);
1723 meta_buf_height =
1724 ubwc_metadata_plane_bufheight(frame_height, 16, 4);
1725 meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride,
1726 meta_buf_height);
1727 meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride,
1728 meta_buf_height);
1729 size = ref_buf_size + meta_size_y + meta_size_c;
1730 size = (size * (num_ref + 3)) + 4096;
1731 }
1732
1733 return size;
1734}
1735
1736static u32 iris_vpu_enc_scratch2_size(struct iris_inst *inst)
1737{
1738 u32 frame_height = iris_vpu_enc_get_bitstream_height(inst);
1739 u32 frame_width = iris_vpu_enc_get_bitstream_width(inst);
1740 u32 num_ref = hfi_buffer_get_recon_count(inst);
1741
1742 return hfi_buffer_scratch2_enc(frame_width, frame_height, num_ref, false);
1743}
1744
1745static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst)
1746{
1747 u32 ds_enable = is_scaling_enabled(inst);
1748 struct v4l2_format *f = inst->fmt_dst;
1749 u32 height = f->fmt.pix_mp.height;
1750 u32 width = f->fmt.pix_mp.width;
1751
1752 return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0);
1753}
1754
1755static inline u32 size_dpb_opb(u32 height, u32 lcu_size)
1756{
1757 u32 max_tile_height = ((height + lcu_size - 1) / lcu_size) * lcu_size + 8;
1758 u32 dpb_opb = 3 * ((max_tile_height >> 3) * DMA_ALIGNMENT);
1759 u32 num_luma_chrome_plane = 2;
1760
1761 return ALIGN(dpb_opb, DMA_ALIGNMENT) * num_luma_chrome_plane;
1762}
1763
1764static u32 hfi_vpu4x_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
1765{
1766 u32 vp9_top_lb, vp9_fe_left_lb, vp9_se_left_lb, dpb_opb, vp9d_qp, num_lcu_per_pipe;
1767 u32 lcu_size = 64;
1768
1769 vp9_top_lb = ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT);
1770 vp9_top_lb += ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT);
1771 vp9_top_lb += max3(DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_16_BYTES) *
1772 MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE,
1773 DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_32_BYTES) *
1774 MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE,
1775 DIV_ROUND_UP(frame_width, BUFFER_ALIGNMENT_64_BYTES) *
1776 MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE);
1777 vp9_top_lb = ALIGN(vp9_top_lb, DMA_ALIGNMENT);
1778 vp9_top_lb += ALIGN((DMA_ALIGNMENT * DIV_ROUND_UP(frame_width, lcu_size)),
1779 DMA_ALIGNMENT) * FE_TOP_CTRL_LINE_NUMBERS;
1780 vp9_top_lb += ALIGN(DMA_ALIGNMENT * 8 * DIV_ROUND_UP(frame_width, lcu_size),
1781 DMA_ALIGNMENT) * (FE_TOP_DATA_LUMA_LINE_NUMBERS +
1782 FE_TOP_DATA_CHROMA_LINE_NUMBERS);
1783
1784 num_lcu_per_pipe = (DIV_ROUND_UP(frame_height, lcu_size) / num_vpp_pipes) +
1785 (DIV_ROUND_UP(frame_height, lcu_size) % num_vpp_pipes);
1786 vp9_fe_left_lb = ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMENT) *
1787 FE_LFT_CTRL_LINE_NUMBERS;
1788 vp9_fe_left_lb += ((ALIGN((DMA_ALIGNMENT * 8 * num_lcu_per_pipe), DMA_ALIGNMENT) *
1789 FE_LFT_DB_DATA_LINE_NUMBERS) +
1790 ALIGN((DMA_ALIGNMENT * 3 * num_lcu_per_pipe), DMA_ALIGNMENT) +
1791 ALIGN((DMA_ALIGNMENT * 4 * num_lcu_per_pipe), DMA_ALIGNMENT) +
1792 (ALIGN((DMA_ALIGNMENT * 24 * num_lcu_per_pipe), DMA_ALIGNMENT) *
1793 FE_LFT_LR_DATA_LINE_NUMBERS));
1794 vp9_fe_left_lb = vp9_fe_left_lb * num_vpp_pipes;
1795
1796 vp9_se_left_lb = ALIGN(size_vpxd_lb_se_left_ctrl(frame_width, frame_height),
1797 DMA_ALIGNMENT);
1798 dpb_opb = size_dpb_opb(frame_height, lcu_size);
1799 vp9d_qp = ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT);
1800
1801 return vp9_top_lb + vp9_fe_left_lb + (vp9_se_left_lb * num_vpp_pipes) +
1802 (dpb_opb * num_vpp_pipes) + vp9d_qp;
1803}
1804
1805static u32 hfi_vpu4x_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min,
1806 bool is_opb, u32 num_vpp_pipes)
1807{
1808 u32 lb_size = hfi_vpu4x_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes);
1809 u32 dpb_obp_size = 0, lcu_size = 64;
1810
1811 if (is_opb)
1812 dpb_obp_size = size_dpb_opb(frame_height, lcu_size) * num_vpp_pipes;
1813
1814 return lb_size + dpb_obp_size;
1815}
1816
1817static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst)
1818{
1819 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
1820 u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
1821 struct v4l2_format *f = inst->fmt_src;
1822 u32 height = f->fmt.pix_mp.height;
1823 u32 width = f->fmt.pix_mp.width;
1824 bool is_opb = false;
1825
1826 if (iris_split_mode_enabled(inst))
1827 is_opb = true;
1828
1829 if (inst->codec == V4L2_PIX_FMT_H264)
1830 return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes);
1831 else if (inst->codec == V4L2_PIX_FMT_HEVC)
1832 return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes);
1833 else if (inst->codec == V4L2_PIX_FMT_VP9)
1834 return hfi_vpu4x_buffer_line_vp9d(width, height, out_min_count, is_opb,
1835 num_vpp_pipes);
1836
1837 return 0;
1838}
1839
1840static u32 hfi_vpu4x_buffer_persist_h265d(u32 rpu_enabled)
1841{
1842 return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + H265_NUM_FRM_INFO *
1843 H265_DISPLAY_BUF_SIZE + (H265_NUM_TILE * sizeof(u32)) + (NUM_HW_PIC_BUF *
1844 (SIZE_SEI_USERDATA + SIZE_H265D_ARP + SIZE_THREE_DIMENSION_USERDATA)) +
1845 rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), DMA_ALIGNMENT);
1846}
1847
1848static u32 hfi_vpu4x_buffer_persist_vp9d(void)
1849{
1850 return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALIGNMENT) +
1851 (ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) * 2) +
1852 ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT) +
1853 ALIGN(VP9_UDC_HEADER_BUF_SIZE, DMA_ALIGNMENT) +
1854 ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, DMA_ALIGNMENT) +
1855 ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE_VPU4X, DMA_ALIGNMENT) +
1856 HDR10_HIST_EXTRADATA_SIZE;
1857}
1858
1859static u32 iris_vpu4x_dec_persist_size(struct iris_inst *inst)
1860{
1861 if (inst->codec == V4L2_PIX_FMT_H264)
1862 return hfi_buffer_persist_h264d();
1863 else if (inst->codec == V4L2_PIX_FMT_HEVC)
1864 return hfi_vpu4x_buffer_persist_h265d(0);
1865 else if (inst->codec == V4L2_PIX_FMT_VP9)
1866 return hfi_vpu4x_buffer_persist_vp9d();
1867
1868 return 0;
1869}
1870
1871static u32 size_se_lb(u32 standard, u32 num_vpp_pipes_enc,
1872 u32 frame_width_coded, u32 frame_height_coded)
1873{
1874 u32 se_tlb_size = ALIGN(frame_width_coded, DMA_ALIGNMENT);
1875 u32 se_llb_size = (standard == HFI_CODEC_ENCODE_HEVC) ?
1876 ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) /
1877 BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE :
1878 ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) /
1879 BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE;
1880
1881 se_llb_size = ALIGN(se_llb_size, BUFFER_ALIGNMENT_32_BYTES);
1882
1883 if (num_vpp_pipes_enc > 1)
1884 se_llb_size = ALIGN(se_llb_size + BUFFER_ALIGNMENT_512_BYTES,
1885 DMA_ALIGNMENT) * num_vpp_pipes_enc;
1886
1887 return ALIGN(se_tlb_size + se_llb_size, DMA_ALIGNMENT);
1888}
1889
1890static u32 size_te_lb(bool is_ten_bit, u32 num_vpp_pipes_enc, u32 width_in_lcus,
1891 u32 frame_height_coded, u32 frame_width_coded)
1892{
1893 u32 num_pixel_10_bit = 3, num_pixel_8_bit = 2, num_pixel_te_llb = 3;
1894 u32 te_llb_col_rc_size = ALIGN(32 * width_in_lcus / num_vpp_pipes_enc,
1895 DMA_ALIGNMENT) * num_vpp_pipes_enc;
1896 u32 te_tlb_recon_data_size = ALIGN((is_ten_bit ? num_pixel_10_bit : num_pixel_8_bit) *
1897 frame_width_coded, DMA_ALIGNMENT);
1898 u32 te_llb_recon_data_size = ((1 + is_ten_bit) * num_pixel_te_llb * frame_height_coded +
1899 num_vpp_pipes_enc - 1) / num_vpp_pipes_enc;
1900 te_llb_recon_data_size = ALIGN(te_llb_recon_data_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
1901
1902 return ALIGN(te_llb_recon_data_size + te_llb_col_rc_size + te_tlb_recon_data_size,
1903 DMA_ALIGNMENT);
1904}
1905
1906static inline u32 calc_fe_tlb_size(u32 size_per_lcu, bool is_ten_bit)
1907{
1908 u32 num_pixels_fe_tlb_10_bit = 128, num_pixels_fe_tlb_8_bit = 64;
1909
1910 return is_ten_bit ? (num_pixels_fe_tlb_10_bit * (size_per_lcu + 1)) :
1911 (size_per_lcu * num_pixels_fe_tlb_8_bit);
1912}
1913
1914static u32 size_fe_lb(bool is_ten_bit, u32 standard, u32 num_vpp_pipes_enc,
1915 u32 frame_height_coded, u32 frame_width_coded)
1916{
1917 u32 log2_lcu_size, num_cu_in_height_pipe, num_cu_in_width,
1918 fb_llb_db_ctrl_size, fb_llb_db_luma_size, fb_llb_db_chroma_size,
1919 fb_tlb_db_ctrl_size, fb_tlb_db_luma_size, fb_tlb_db_chroma_size,
1920 fb_llb_sao_ctrl_size, fb_llb_sao_luma_size, fb_llb_sao_chroma_size,
1921 fb_tlb_sao_ctrl_size, fb_tlb_sao_luma_size, fb_tlb_sao_chroma_size,
1922 fb_lb_top_sdc_size, fb_lb_se_ctrl_size, fe_tlb_size, size_per_lcu;
1923
1924 log2_lcu_size = (standard == HFI_CODEC_ENCODE_HEVC) ? 5 : 4;
1925 num_cu_in_height_pipe = ((frame_height_coded >> log2_lcu_size) + num_vpp_pipes_enc - 1) /
1926 num_vpp_pipes_enc;
1927 num_cu_in_width = frame_width_coded >> log2_lcu_size;
1928
1929 size_per_lcu = 2;
1930 fe_tlb_size = calc_fe_tlb_size(size_per_lcu, 1);
1931 fb_llb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
1932 fb_llb_db_ctrl_size = ALIGN(fb_llb_db_ctrl_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
1933
1934 size_per_lcu = (1 << (log2_lcu_size - 3));
1935 fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
1936 fb_llb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
1937 fb_llb_db_luma_size = ALIGN(fb_llb_db_luma_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
1938
1939 size_per_lcu = ((1 << (log2_lcu_size - 4)) * 2);
1940 fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
1941 fb_llb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
1942 fb_llb_db_chroma_size = ALIGN(fb_llb_db_chroma_size, DMA_ALIGNMENT) * num_vpp_pipes_enc;
1943
1944 size_per_lcu = 1;
1945 fe_tlb_size = calc_fe_tlb_size(size_per_lcu, 1);
1946 fb_tlb_db_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
1947 fb_llb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_height_pipe;
1948 fb_llb_sao_ctrl_size = fb_llb_sao_ctrl_size * num_vpp_pipes_enc;
1949 fb_tlb_sao_ctrl_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
1950
1951 size_per_lcu = ((1 << (log2_lcu_size - 3)) + 1);
1952 fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
1953 fb_tlb_db_luma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
1954
1955 size_per_lcu = (2 * ((1 << (log2_lcu_size - 4)) + 1));
1956 fe_tlb_size = calc_fe_tlb_size(size_per_lcu, is_ten_bit);
1957 fb_tlb_db_chroma_size = ALIGN(fe_tlb_size, DMA_ALIGNMENT) * num_cu_in_width;
1958
1959 fb_llb_sao_luma_size = BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc;
1960 fb_llb_sao_chroma_size = BUFFER_ALIGNMENT_256_BYTES * num_vpp_pipes_enc;
1961 fb_tlb_sao_luma_size = BUFFER_ALIGNMENT_256_BYTES;
1962 fb_tlb_sao_chroma_size = BUFFER_ALIGNMENT_256_BYTES;
1963 fb_lb_top_sdc_size = ALIGN((FE_SDC_DATA_PER_BLOCK * (frame_width_coded >> 5)),
1964 DMA_ALIGNMENT);
1965 fb_lb_se_ctrl_size = ALIGN((SE_CTRL_DATA_PER_BLOCK * (frame_width_coded >> 5)),
1966 DMA_ALIGNMENT);
1967
1968 return fb_llb_db_ctrl_size + fb_llb_db_luma_size + fb_llb_db_chroma_size +
1969 fb_tlb_db_ctrl_size + fb_tlb_db_luma_size + fb_tlb_db_chroma_size +
1970 fb_llb_sao_ctrl_size + fb_llb_sao_luma_size + fb_llb_sao_chroma_size +
1971 fb_tlb_sao_ctrl_size + fb_tlb_sao_luma_size + fb_tlb_sao_chroma_size +
1972 fb_lb_top_sdc_size + fb_lb_se_ctrl_size;
1973}
1974
1975static u32 size_md_lb(u32 standard, u32 frame_width_coded,
1976 u32 frame_height_coded, u32 num_vpp_pipes_enc)
1977{
1978 u32 md_tlb_size = ALIGN(frame_width_coded, DMA_ALIGNMENT);
1979 u32 md_llb_size = (standard == HFI_CODEC_ENCODE_HEVC) ?
1980 ((frame_height_coded + BUFFER_ALIGNMENT_32_BYTES - 1) /
1981 BUFFER_ALIGNMENT_32_BYTES) * LOG2_16 * LLB_UNIT_SIZE :
1982 ((frame_height_coded + BUFFER_ALIGNMENT_16_BYTES - 1) /
1983 BUFFER_ALIGNMENT_16_BYTES) * LOG2_32 * LLB_UNIT_SIZE;
1984
1985 md_llb_size = ALIGN(md_llb_size, BUFFER_ALIGNMENT_32_BYTES);
1986
1987 if (num_vpp_pipes_enc > 1)
1988 md_llb_size = ALIGN(md_llb_size + BUFFER_ALIGNMENT_512_BYTES,
1989 DMA_ALIGNMENT) * num_vpp_pipes_enc;
1990
1991 md_llb_size = ALIGN(md_llb_size, DMA_ALIGNMENT);
1992
1993 return ALIGN(md_tlb_size + md_llb_size, DMA_ALIGNMENT);
1994}
1995
1996static u32 size_dma_opb_lb(u32 num_vpp_pipes_enc, u32 frame_width_coded,
1997 u32 frame_height_coded)
1998{
1999 u32 opb_packet_bytes = 128, opb_bpp = 128, opb_size_per_row = 6;
2000 u32 dma_opb_wr_tlb_y_size = DIV_ROUND_UP(frame_width_coded, 16) * opb_packet_bytes;
2001 u32 dma_opb_wr_tlb_uv_size = DIV_ROUND_UP(frame_width_coded, 16) * opb_packet_bytes;
2002 u32 dma_opb_wr2_tlb_y_size = ALIGN((opb_bpp * opb_size_per_row * frame_height_coded / 8),
2003 DMA_ALIGNMENT) * num_vpp_pipes_enc;
2004 u32 dma_opb_wr2_tlb_uv_size = ALIGN((opb_bpp * opb_size_per_row * frame_height_coded / 8),
2005 DMA_ALIGNMENT) * num_vpp_pipes_enc;
2006
2007 dma_opb_wr2_tlb_y_size = max(dma_opb_wr2_tlb_y_size, dma_opb_wr_tlb_y_size << 1);
2008 dma_opb_wr2_tlb_uv_size = max(dma_opb_wr2_tlb_uv_size, dma_opb_wr_tlb_uv_size << 1);
2009
2010 return ALIGN(dma_opb_wr_tlb_y_size + dma_opb_wr_tlb_uv_size + dma_opb_wr2_tlb_y_size +
2011 dma_opb_wr2_tlb_uv_size, DMA_ALIGNMENT);
2012}
2013
2014static u32 hfi_vpu4x_buffer_line_enc(u32 frame_width, u32 frame_height,
2015 bool is_ten_bit, u32 num_vpp_pipes_enc,
2016 u32 lcu_size, u32 standard)
2017{
2018 u32 width_in_lcus = (frame_width + lcu_size - 1) / lcu_size;
2019 u32 height_in_lcus = (frame_height + lcu_size - 1) / lcu_size;
2020 u32 frame_width_coded = width_in_lcus * lcu_size;
2021 u32 frame_height_coded = height_in_lcus * lcu_size;
2022
2023 u32 se_lb_size = size_se_lb(standard, num_vpp_pipes_enc, frame_width_coded,
2024 frame_height_coded);
2025 u32 te_lb_size = size_te_lb(is_ten_bit, num_vpp_pipes_enc, width_in_lcus,
2026 frame_height_coded, frame_width_coded);
2027 u32 fe_lb_size = size_fe_lb(is_ten_bit, standard, num_vpp_pipes_enc, frame_height_coded,
2028 frame_width_coded);
2029 u32 md_lb_size = size_md_lb(standard, frame_width_coded, frame_height_coded,
2030 num_vpp_pipes_enc);
2031 u32 dma_opb_lb_size = size_dma_opb_lb(num_vpp_pipes_enc, frame_width_coded,
2032 frame_height_coded);
2033 u32 dse_lb_size = ALIGN((256 + (16 * (frame_width_coded >> 4))), DMA_ALIGNMENT);
2034 u32 size_vpss_lb_enc = size_vpss_line_buf_vpu33(num_vpp_pipes_enc, frame_width_coded,
2035 frame_height_coded);
2036
2037 return se_lb_size + te_lb_size + fe_lb_size + md_lb_size + dma_opb_lb_size +
2038 dse_lb_size + size_vpss_lb_enc;
2039}
2040
2041static u32 iris_vpu4x_enc_line_size(struct iris_inst *inst)
2042{
2043 u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
2044 u32 lcu_size = inst->codec == V4L2_PIX_FMT_HEVC ? 32 : 16;
2045 struct v4l2_format *f = inst->fmt_dst;
2046 u32 height = f->fmt.pix_mp.height;
2047 u32 width = f->fmt.pix_mp.width;
2048
2049 return hfi_vpu4x_buffer_line_enc(width, height, 0, num_vpp_pipes,
2050 lcu_size, inst->codec);
2051}
2052
2053static int output_min_count(struct iris_inst *inst)
2054{
2055 int output_min_count = 4;
2056
2057 /* fw_min_count > 0 indicates reconfig event has already arrived */
2058 if (inst->fw_min_count) {
2059 if (iris_split_mode_enabled(inst) &&
2060 (inst->codec == V4L2_PIX_FMT_VP9 ||
2061 inst->codec == V4L2_PIX_FMT_AV1))
2062 return min_t(u32, 4, inst->fw_min_count);
2063 else
2064 return inst->fw_min_count;
2065 }
2066
2067 if (inst->codec == V4L2_PIX_FMT_VP9)
2068 output_min_count = 9;
2069 else if (inst->codec == V4L2_PIX_FMT_AV1)
2070 output_min_count = 11;
2071
2072 return output_min_count;
2073}
2074
2075struct iris_vpu_buf_type_handle {
2076 enum iris_buffer_type type;
2077 u32 (*handle)(struct iris_inst *inst);
2078};
2079
2080u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
2081{
2082 const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL;
2083 u32 size = 0, buf_type_handle_size = 0, i;
2084
2085 static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = {
2086 {BUF_BIN, iris_vpu_dec_bin_size },
2087 {BUF_COMV, iris_vpu3x_4x_dec_comv_size },
2088 {BUF_NON_COMV, iris_vpu_dec_non_comv_size },
2089 {BUF_LINE, iris_vpu_dec_line_size },
2090 {BUF_PERSIST, iris_vpu_dec_persist_size },
2091 {BUF_DPB, iris_vpu_dec_dpb_size },
2092 {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size },
2093 {BUF_PARTIAL, iris_vpu_dec_partial_size },
2094 };
2095
2096 static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = {
2097 {BUF_BIN, iris_vpu_enc_bin_size },
2098 {BUF_COMV, iris_vpu_enc_comv_size },
2099 {BUF_NON_COMV, iris_vpu_enc_non_comv_size },
2100 {BUF_LINE, iris_vpu_enc_line_size },
2101 {BUF_ARP, iris_vpu_enc_arp_size },
2102 {BUF_VPSS, iris_vpu_enc_vpss_size },
2103 {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size },
2104 {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size },
2105 };
2106
2107 if (inst->domain == DECODER) {
2108 buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle);
2109 buf_type_handle_arr = dec_internal_buf_type_handle;
2110 } else if (inst->domain == ENCODER) {
2111 buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle);
2112 buf_type_handle_arr = enc_internal_buf_type_handle;
2113 }
2114
2115 for (i = 0; i < buf_type_handle_size; i++) {
2116 if (buf_type_handle_arr[i].type == buffer_type) {
2117 size = buf_type_handle_arr[i].handle(inst);
2118 break;
2119 }
2120 }
2121
2122 return size;
2123}
2124
2125u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
2126{
2127 u32 size = 0, i;
2128
2129 static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = {
2130 {BUF_BIN, iris_vpu_enc_bin_size },
2131 {BUF_COMV, iris_vpu_enc_comv_size },
2132 {BUF_NON_COMV, iris_vpu_enc_non_comv_size },
2133 {BUF_LINE, iris_vpu33_enc_line_size },
2134 {BUF_ARP, iris_vpu_enc_arp_size },
2135 {BUF_VPSS, iris_vpu_enc_vpss_size },
2136 {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size },
2137 {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size },
2138 };
2139
2140 if (inst->domain == DECODER)
2141 return iris_vpu_buf_size(inst, buffer_type);
2142
2143 for (i = 0; i < ARRAY_SIZE(enc_internal_buf_type_handle); i++) {
2144 if (enc_internal_buf_type_handle[i].type == buffer_type) {
2145 size = enc_internal_buf_type_handle[i].handle(inst);
2146 break;
2147 }
2148 }
2149
2150 return size;
2151}
2152
2153u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
2154{
2155 const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL;
2156 u32 size = 0, buf_type_handle_size = 0, i;
2157
2158 static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = {
2159 {BUF_BIN, iris_vpu_dec_bin_size },
2160 {BUF_COMV, iris_vpu3x_4x_dec_comv_size },
2161 {BUF_NON_COMV, iris_vpu_dec_non_comv_size },
2162 {BUF_LINE, iris_vpu4x_dec_line_size },
2163 {BUF_PERSIST, iris_vpu4x_dec_persist_size },
2164 {BUF_DPB, iris_vpu_dec_dpb_size },
2165 {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size },
2166 };
2167
2168 static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = {
2169 {BUF_BIN, iris_vpu_enc_bin_size },
2170 {BUF_COMV, iris_vpu_enc_comv_size },
2171 {BUF_NON_COMV, iris_vpu_enc_non_comv_size },
2172 {BUF_LINE, iris_vpu4x_enc_line_size },
2173 {BUF_ARP, iris_vpu_enc_arp_size },
2174 {BUF_VPSS, iris_vpu_enc_vpss_size },
2175 {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size },
2176 {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size },
2177 };
2178
2179 if (inst->domain == DECODER) {
2180 buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle);
2181 buf_type_handle_arr = dec_internal_buf_type_handle;
2182 } else if (inst->domain == ENCODER) {
2183 buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle);
2184 buf_type_handle_arr = enc_internal_buf_type_handle;
2185 }
2186
2187 for (i = 0; i < buf_type_handle_size; i++) {
2188 if (buf_type_handle_arr[i].type == buffer_type) {
2189 size = buf_type_handle_arr[i].handle(inst);
2190 break;
2191 }
2192 }
2193
2194 return size;
2195}
2196
2197static u32 internal_buffer_count(struct iris_inst *inst,
2198 enum iris_buffer_type buffer_type)
2199{
2200 if (buffer_type == BUF_BIN || buffer_type == BUF_LINE ||
2201 buffer_type == BUF_PERSIST) {
2202 return 1;
2203 } else if (buffer_type == BUF_COMV || buffer_type == BUF_NON_COMV) {
2204 if (inst->codec == V4L2_PIX_FMT_H264 ||
2205 inst->codec == V4L2_PIX_FMT_HEVC ||
2206 inst->codec == V4L2_PIX_FMT_AV1)
2207 return 1;
2208 }
2209
2210 return 0;
2211}
2212
2213static inline int iris_vpu_dpb_count(struct iris_inst *inst)
2214{
2215 if (inst->codec == V4L2_PIX_FMT_AV1)
2216 return 11;
2217
2218 if (iris_split_mode_enabled(inst)) {
2219 return inst->fw_min_count ?
2220 inst->fw_min_count : inst->buffers[BUF_OUTPUT].min_count;
2221 }
2222
2223 return 0;
2224}
2225
2226int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type)
2227{
2228 switch (buffer_type) {
2229 case BUF_INPUT:
2230 return MIN_BUFFERS;
2231 case BUF_OUTPUT:
2232 if (inst->domain == ENCODER)
2233 return MIN_BUFFERS;
2234 else
2235 return output_min_count(inst);
2236 case BUF_NON_COMV:
2237 if (inst->codec == V4L2_PIX_FMT_AV1)
2238 return 0;
2239 else
2240 return 1;
2241 case BUF_BIN:
2242 case BUF_COMV:
2243 case BUF_LINE:
2244 case BUF_PERSIST:
2245 return internal_buffer_count(inst, buffer_type);
2246 case BUF_SCRATCH_1:
2247 case BUF_SCRATCH_2:
2248 case BUF_VPSS:
2249 case BUF_ARP:
2250 case BUF_PARTIAL:
2251 return 1; /* internal buffer count needed by firmware is 1 */
2252 case BUF_DPB:
2253 return iris_vpu_dpb_count(inst);
2254 default:
2255 return 0;
2256 }
2257}