| 1 | |
| 2 | |
| 3 | * Copyright (C) 2026, NVIDIA CORPORATION. All rights reserved.
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| 4 |
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| 5 |
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| 6 | #include <soc/tegra/mc.h>
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| 7 |
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| 8 | #include <dt-bindings/memory/tegra234-mc.h>
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| 9 | #include <dt-bindings/memory/nvidia,tegra238-mc.h>
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| 10 | #include <linux/interconnect.h>
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| 11 | #include <linux/tegra-icc.h>
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| 12 |
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| 13 | #include <soc/tegra/bpmp.h>
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| 14 | #include "mc.h"
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| 15 |
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| 16 | static const struct tegra_mc_client tegra238_mc_clients[] = {
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| 17 | {
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| 18 | .id = TEGRA234_MEMORY_CLIENT_HDAR,
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| 19 | .name = "hdar",
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| 20 | .bpmp_id = TEGRA_ICC_BPMP_HDA,
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| 21 | .type = TEGRA_ICC_ISO_AUDIO,
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| 22 | .sid = TEGRA238_SID_HDA,
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| 23 | .regs = {
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| 24 | .sid = {
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| 25 | .override = 0xa8,
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| 26 | .security = 0xac,
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| 27 | },
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| 28 | },
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| 29 | }, {
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| 30 | .id = TEGRA234_MEMORY_CLIENT_HDAW,
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| 31 | .name = "hdaw",
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| 32 | .bpmp_id = TEGRA_ICC_BPMP_HDA,
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| 33 | .type = TEGRA_ICC_ISO_AUDIO,
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| 34 | .sid = TEGRA238_SID_HDA,
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| 35 | .regs = {
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| 36 | .sid = {
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| 37 | .override = 0x1a8,
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| 38 | .security = 0x1ac,
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| 39 | },
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| 40 | },
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| 41 | }, {
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| 42 | .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
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| 43 | .name = "sdmmcrab",
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| 44 | .bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
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| 45 | .type = TEGRA_ICC_NISO,
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| 46 | .sid = TEGRA238_SID_SDMMC4A,
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| 47 | .regs = {
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| 48 | .sid = {
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| 49 | .override = 0x318,
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| 50 | .security = 0x31c,
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| 51 | },
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| 52 | },
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| 53 | }, {
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| 54 | .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
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| 55 | .name = "sdmmcwab",
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| 56 | .bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
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| 57 | .type = TEGRA_ICC_NISO,
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| 58 | .sid = TEGRA238_SID_SDMMC4A,
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| 59 | .regs = {
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| 60 | .sid = {
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| 61 | .override = 0x338,
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| 62 | .security = 0x33c,
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| 63 | },
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| 64 | },
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| 65 | }, {
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| 66 | .id = TEGRA234_MEMORY_CLIENT_APER,
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| 67 | .name = "aper",
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| 68 | .bpmp_id = TEGRA_ICC_BPMP_APE,
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| 69 | .type = TEGRA_ICC_ISO_AUDIO,
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| 70 | .sid = TEGRA238_SID_ISO_APE0,
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| 71 | .regs = {
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| 72 | .sid = {
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| 73 | .override = 0x3d0,
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| 74 | .security = 0x3d4,
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| 75 | },
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| 76 | },
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| 77 | }, {
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| 78 | .id = TEGRA234_MEMORY_CLIENT_APEW,
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| 79 | .name = "apew",
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| 80 | .bpmp_id = TEGRA_ICC_BPMP_APE,
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| 81 | .type = TEGRA_ICC_ISO_AUDIO,
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| 82 | .sid = TEGRA238_SID_ISO_APE0,
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| 83 | .regs = {
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| 84 | .sid = {
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| 85 | .override = 0x3d8,
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| 86 | .security = 0x3dc,
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| 87 | },
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| 88 | },
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| 89 | }, {
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| 90 | .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
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| 91 | .name = "nvdisplayr",
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| 92 | .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
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| 93 | .type = TEGRA_ICC_ISO_DISPLAY,
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| 94 | .sid = TEGRA238_SID_ISO_NVDISPLAY,
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| 95 | .regs = {
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| 96 | .sid = {
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| 97 | .override = 0x490,
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| 98 | .security = 0x494,
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| 99 | },
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| 100 | },
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| 101 | }, {
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| 102 | .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
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| 103 | .name = "nvdisplayr1",
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| 104 | .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
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| 105 | .type = TEGRA_ICC_ISO_DISPLAY,
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| 106 | .sid = TEGRA238_SID_ISO_NVDISPLAY,
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| 107 | .regs = {
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| 108 | .sid = {
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| 109 | .override = 0x508,
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| 110 | .security = 0x50c,
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| 111 | },
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| 112 | },
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| 113 | }, {
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| 114 | .id = TEGRA234_MEMORY_CLIENT_BPMPR,
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| 115 | .name = "bpmpr",
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| 116 | .sid = TEGRA238_SID_BPMP,
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| 117 | .regs = {
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| 118 | .sid = {
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| 119 | .override = 0x498,
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| 120 | .security = 0x49c,
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| 121 | },
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| 122 | },
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| 123 | }, {
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| 124 | .id = TEGRA234_MEMORY_CLIENT_BPMPW,
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| 125 | .name = "bpmpw",
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| 126 | .sid = TEGRA238_SID_BPMP,
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| 127 | .regs = {
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| 128 | .sid = {
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| 129 | .override = 0x4a0,
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| 130 | .security = 0x4a4,
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| 131 | },
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| 132 | },
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| 133 | }, {
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| 134 | .id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
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| 135 | .name = "bpmpdmar",
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| 136 | .sid = TEGRA238_SID_BPMP,
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| 137 | .regs = {
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| 138 | .sid = {
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| 139 | .override = 0x4a8,
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| 140 | .security = 0x4ac,
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| 141 | },
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| 142 | },
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| 143 | }, {
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| 144 | .id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
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| 145 | .name = "bpmpdmaw",
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| 146 | .sid = TEGRA238_SID_BPMP,
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| 147 | .regs = {
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| 148 | .sid = {
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| 149 | .override = 0x4b0,
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| 150 | .security = 0x4b4,
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| 151 | },
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| 152 | },
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| 153 | }, {
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| 154 | .id = TEGRA234_MEMORY_CLIENT_APEDMAR,
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| 155 | .name = "apedmar",
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| 156 | .bpmp_id = TEGRA_ICC_BPMP_APEDMA,
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| 157 | .type = TEGRA_ICC_ISO_AUDIO,
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| 158 | .sid = TEGRA238_SID_ISO_APE1,
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| 159 | .regs = {
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| 160 | .sid = {
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| 161 | .override = 0x4f8,
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| 162 | .security = 0x4fc,
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| 163 | },
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| 164 | },
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| 165 | }, {
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| 166 | .id = TEGRA234_MEMORY_CLIENT_APEDMAW,
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| 167 | .name = "apedmaw",
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| 168 | .bpmp_id = TEGRA_ICC_BPMP_APEDMA,
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| 169 | .type = TEGRA_ICC_ISO_AUDIO,
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| 170 | .sid = TEGRA238_SID_ISO_APE1,
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| 171 | .regs = {
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| 172 | .sid = {
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| 173 | .override = 0x500,
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| 174 | .security = 0x504,
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| 175 | },
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| 176 | },
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| 177 | }, {
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| 178 | .id = TEGRA234_MEMORY_CLIENT_VICSRD,
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| 179 | .name = "vicsrd",
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| 180 | .bpmp_id = TEGRA_ICC_BPMP_VIC,
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| 181 | .type = TEGRA_ICC_NISO,
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| 182 | .sid = TEGRA238_SID_VIC,
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| 183 | .regs = {
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| 184 | .sid = {
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| 185 | .override = 0x360,
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| 186 | .security = 0x364,
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| 187 | },
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| 188 | },
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| 189 | }, {
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| 190 | .id = TEGRA234_MEMORY_CLIENT_VICSWR,
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| 191 | .name = "vicswr",
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| 192 | .bpmp_id = TEGRA_ICC_BPMP_VIC,
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| 193 | .type = TEGRA_ICC_NISO,
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| 194 | .sid = TEGRA238_SID_VIC,
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| 195 | .regs = {
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| 196 | .sid = {
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| 197 | .override = 0x368,
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| 198 | .security = 0x36c,
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| 199 | },
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| 200 | },
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| 201 | }, {
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| 202 | .id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
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| 203 | .name = "nvdecsrd",
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| 204 | .bpmp_id = TEGRA_ICC_BPMP_NVDEC,
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| 205 | .type = TEGRA_ICC_NISO,
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| 206 | .sid = TEGRA238_SID_NVDEC,
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| 207 | .regs = {
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| 208 | .sid = {
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| 209 | .override = 0x3c0,
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| 210 | .security = 0x3c4,
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| 211 | },
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| 212 | },
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| 213 | }, {
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| 214 | .id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
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| 215 | .name = "nvdecswr",
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| 216 | .bpmp_id = TEGRA_ICC_BPMP_NVDEC,
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| 217 | .type = TEGRA_ICC_NISO,
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| 218 | .sid = TEGRA238_SID_NVDEC,
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| 219 | .regs = {
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| 220 | .sid = {
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| 221 | .override = 0x3c8,
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| 222 | .security = 0x3cc,
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| 223 | },
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| 224 | },
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| 225 | }, {
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| 226 | .id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
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| 227 | .name = "nvencsrd",
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| 228 | .bpmp_id = TEGRA_ICC_BPMP_NVENC,
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| 229 | .type = TEGRA_ICC_NISO,
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| 230 | .sid = TEGRA238_SID_NVENC,
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| 231 | .regs = {
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| 232 | .sid = {
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| 233 | .override = 0xe0,
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| 234 | .security = 0xe4,
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| 235 | },
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| 236 | },
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| 237 | }, {
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| 238 | .id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
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| 239 | .name = "nvencswr",
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| 240 | .bpmp_id = TEGRA_ICC_BPMP_NVENC,
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| 241 | .type = TEGRA_ICC_NISO,
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| 242 | .sid = TEGRA238_SID_NVENC,
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| 243 | .regs = {
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| 244 | .sid = {
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| 245 | .override = 0x158,
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| 246 | .security = 0x15c,
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| 247 | },
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| 248 | },
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| 249 | }, {
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| 250 | .id = TEGRA234_MEMORY_CLIENT_PCIE0R,
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| 251 | .name = "pcie0r",
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| 252 | .bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
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| 253 | .type = TEGRA_ICC_NISO,
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| 254 | .sid = TEGRA238_SID_PCIE0,
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| 255 | .regs = {
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| 256 | .sid = {
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| 257 | .override = 0x6c0,
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| 258 | .security = 0x6c4,
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| 259 | },
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| 260 | },
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| 261 | }, {
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| 262 | .id = TEGRA234_MEMORY_CLIENT_PCIE0W,
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| 263 | .name = "pcie0w",
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| 264 | .bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
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| 265 | .type = TEGRA_ICC_NISO,
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| 266 | .sid = TEGRA238_SID_PCIE0,
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| 267 | .regs = {
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| 268 | .sid = {
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| 269 | .override = 0x6c8,
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| 270 | .security = 0x6cc,
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| 271 | },
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| 272 | },
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| 273 | }, {
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| 274 | .id = TEGRA234_MEMORY_CLIENT_PCIE1R,
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| 275 | .name = "pcie1r",
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| 276 | .bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
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| 277 | .type = TEGRA_ICC_NISO,
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| 278 | .sid = TEGRA238_SID_PCIE1,
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| 279 | .regs = {
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| 280 | .sid = {
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| 281 | .override = 0x6d0,
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| 282 | .security = 0x6d4,
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| 283 | },
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| 284 | },
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| 285 | }, {
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| 286 | .id = TEGRA234_MEMORY_CLIENT_PCIE1W,
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| 287 | .name = "pcie1w",
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| 288 | .bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
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| 289 | .type = TEGRA_ICC_NISO,
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| 290 | .sid = TEGRA238_SID_PCIE1,
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| 291 | .regs = {
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| 292 | .sid = {
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| 293 | .override = 0x6d8,
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| 294 | .security = 0x6dc,
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| 295 | },
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| 296 | },
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| 297 | }, {
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| 298 | .id = TEGRA234_MEMORY_CLIENT_PCIE2AR,
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| 299 | .name = "pcie2ar",
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| 300 | .bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
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| 301 | .type = TEGRA_ICC_NISO,
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| 302 | .sid = TEGRA238_SID_PCIE2,
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| 303 | .regs = {
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| 304 | .sid = {
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| 305 | .override = 0x6e0,
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| 306 | .security = 0x6e4,
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| 307 | },
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| 308 | },
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| 309 | }, {
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| 310 | .id = TEGRA234_MEMORY_CLIENT_PCIE2AW,
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| 311 | .name = "pcie2aw",
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| 312 | .bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
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| 313 | .type = TEGRA_ICC_NISO,
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| 314 | .sid = TEGRA238_SID_PCIE2,
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| 315 | .regs = {
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| 316 | .sid = {
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| 317 | .override = 0x6e8,
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| 318 | .security = 0x6ec,
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| 319 | },
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| 320 | },
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| 321 | }, {
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| 322 | .id = TEGRA234_MEMORY_CLIENT_PCIE3R,
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| 323 | .name = "pcie3r",
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| 324 | .bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
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| 325 | .type = TEGRA_ICC_NISO,
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| 326 | .sid = TEGRA238_SID_PCIE3,
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| 327 | .regs = {
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| 328 | .sid = {
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| 329 | .override = 0x6f0,
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| 330 | .security = 0x6f4,
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| 331 | },
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| 332 | },
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| 333 | }, {
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| 334 | .id = TEGRA234_MEMORY_CLIENT_PCIE3W,
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| 335 | .name = "pcie3w",
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| 336 | .bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
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| 337 | .type = TEGRA_ICC_NISO,
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| 338 | .sid = TEGRA238_SID_PCIE3,
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| 339 | .regs = {
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| 340 | .sid = {
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| 341 | .override = 0x6f8,
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| 342 | .security = 0x6fc,
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| 343 | },
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| 344 | },
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| 345 | }, {
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| 346 | .id = TEGRA_ICC_MC_CPU_CLUSTER0,
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| 347 | .name = "sw_cluster0",
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| 348 | .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,
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| 349 | .type = TEGRA_ICC_NISO,
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| 350 | }, {
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| 351 | .id = TEGRA234_MEMORY_CLIENT_NVL1R,
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| 352 | .name = "nvl1r",
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| 353 | .bpmp_id = TEGRA_ICC_BPMP_GPU,
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| 354 | .type = TEGRA_ICC_NISO,
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| 355 | }, {
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| 356 | .id = TEGRA234_MEMORY_CLIENT_NVL1W,
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| 357 | .name = "nvl1w",
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| 358 | .bpmp_id = TEGRA_ICC_BPMP_GPU,
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| 359 | .type = TEGRA_ICC_NISO,
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| 360 | }
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| 361 | };
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| 362 |
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| 363 | static const struct tegra_mc_intmask tegra238_mc_intmasks[] = {
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| 364 | {
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| 365 | .reg = MC_INTMASK,
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| 366 | .mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
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| 367 | MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
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| 368 | MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
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| 369 | },
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| 370 | };
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| 371 |
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| 372 | const struct tegra_mc_soc tegra238_mc_soc = {
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| 373 | .num_clients = ARRAY_SIZE(tegra238_mc_clients),
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| 374 | .clients = tegra238_mc_clients,
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| 375 | .num_address_bits = 40,
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| 376 | .num_channels = 8,
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| 377 | .client_id_mask = 0x1ff,
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| 378 | .intmasks = tegra238_mc_intmasks,
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| 379 | .num_intmasks = ARRAY_SIZE(tegra238_mc_intmasks),
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| 380 | .has_addr_hi_reg = true,
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| 381 | .ops = &tegra186_mc_ops,
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| 382 | .icc_ops = &tegra234_mc_icc_ops,
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| 383 | .ch_intmask = 0x0000ff00,
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| 384 | .global_intstatus_channel_shift = 8,
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| 385 | .num_carveouts = 32,
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| 386 | .regs = &tegra20_mc_regs,
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| 387 | .handle_irq = tegra30_mc_irq_handlers,
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| 388 | .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
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| 389 | .mc_addr_hi_mask = 0x3,
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| 390 | .mc_err_status_type_mask = (0x7 << 28),
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| 391 | };
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