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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * lpc_ich.c - LPC interface for Intel ICH
4 *
5 * LPC bridge function of the Intel ICH contains many other
6 * functional units, such as Interrupt controllers, Timers,
7 * Power Management, System Management, GPIO, RTC, and LPC
8 * Configuration Registers.
9 *
10 * This driver is derived from lpc_sch.
11 *
12 * Copyright (c) 2017, 2021-2022 Intel Corporation
13 * Copyright (c) 2011 Extreme Engineering Solution, Inc.
14 * Author: Aaron Sierra <[email protected]>
15 *
16 * This driver supports the following I/O Controller hubs:
17 * (See the intel documentation on http://developer.intel.com.)
18 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
19 * document number 290687-002, 298242-027: 82801BA (ICH2)
20 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
21 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
22 * document number 290744-001, 290745-025: 82801DB (ICH4)
23 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
24 * document number 273599-001, 273645-002: 82801E (C-ICH)
25 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
26 * document number 300641-004, 300884-013: 6300ESB
27 * document number 301473-002, 301474-026: 82801F (ICH6)
28 * document number 313082-001, 313075-006: 631xESB, 632xESB
29 * document number 307013-003, 307014-024: 82801G (ICH7)
30 * document number 322896-001, 322897-001: NM10
31 * document number 313056-003, 313057-017: 82801H (ICH8)
32 * document number 316972-004, 316973-012: 82801I (ICH9)
33 * document number 319973-002, 319974-002: 82801J (ICH10)
34 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
35 * document number 320066-003, 320257-008: EP80597 (IICH)
36 * document number 324645-001, 324646-001: Cougar Point (CPT)
37 */
38
39#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
40
41#include <linux/align.h>
42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/errno.h>
45#include <linux/acpi.h>
46#include <linux/pci.h>
47#include <linux/pinctrl/pinctrl.h>
48#include <linux/property.h>
49#include <linux/mfd/core.h>
50#include <linux/mfd/lpc_ich.h>
51#include <linux/platform_data/itco_wdt.h>
52#include <linux/platform_data/x86/p2sb.h>
53
54#define ACPIBASE 0x40
55#define ACPIBASE_GPE_OFF 0x28
56#define ACPIBASE_GPE_END 0x2f
57#define ACPIBASE_SMI_OFF 0x30
58#define ACPIBASE_SMI_END 0x33
59#define ACPIBASE_PMC_OFF 0x08
60#define ACPIBASE_PMC_END 0x0c
61#define ACPIBASE_TCO_OFF 0x60
62#define ACPIBASE_TCO_END 0x7f
63#define ACPICTRL_PMCBASE 0x44
64
65#define ACPIBASE_GCS_OFF 0x3410
66#define ACPIBASE_GCS_END 0x3414
67
68#define SPIBASE_BYT 0x54
69#define SPIBASE_BYT_SZ 512
70#define SPIBASE_BYT_EN BIT(1)
71#define BYT_BCR 0xfc
72#define BYT_BCR_WPD BIT(0)
73
74#define SPIBASE_LPT 0x3800
75#define SPIBASE_LPT_SZ 512
76#define BCR 0xdc
77#define BCR_WPD BIT(0)
78
79#define GPIOBASE_ICH0 0x58
80#define GPIOCTRL_ICH0 0x5C
81#define GPIOBASE_ICH6 0x48
82#define GPIOCTRL_ICH6 0x4C
83
84#define RCBABASE 0xf0
85
86#define wdt_io_res(i) wdt_res(0, i)
87#define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
88#define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
89
90static struct resource wdt_ich_res[] = {
91 /* ACPI - TCO */
92 {
93 .flags = IORESOURCE_IO,
94 },
95 /* ACPI - SMI */
96 {
97 .flags = IORESOURCE_IO,
98 },
99 /* GCS or PMC */
100 {
101 .flags = IORESOURCE_MEM,
102 },
103};
104
105static struct resource gpio_ich_res[] = {
106 /* GPIO */
107 {
108 .flags = IORESOURCE_IO,
109 },
110 /* ACPI - GPE0 */
111 {
112 .flags = IORESOURCE_IO,
113 },
114};
115
116static struct resource intel_spi_res[] = {
117 {
118 .flags = IORESOURCE_MEM,
119 }
120};
121
122static struct mfd_cell lpc_ich_wdt_cell = {
123 .name = "iTCO_wdt",
124 .num_resources = ARRAY_SIZE(wdt_ich_res),
125 .resources = wdt_ich_res,
126 .ignore_resource_conflicts = true,
127};
128
129const struct software_node lpc_ich_gpio_swnode = {
130 .name = "gpio_ich",
131};
132EXPORT_SYMBOL_NS(lpc_ich_gpio_swnode, "LPC_ICH");
133
134static struct mfd_cell lpc_ich_gpio_cell = {
135 .name = "gpio_ich",
136 .num_resources = ARRAY_SIZE(gpio_ich_res),
137 .resources = gpio_ich_res,
138 .ignore_resource_conflicts = true,
139 .swnode = &lpc_ich_gpio_swnode,
140};
141
142#define INTEL_GPIO_RESOURCE_SIZE 0x1000
143
144struct lpc_ich_gpio_info {
145 const char *hid;
146 const struct mfd_cell *devices;
147 size_t nr_devices;
148 struct resource **resources;
149 size_t nr_resources;
150 const resource_size_t *offsets;
151};
152
153#define APL_GPIO_NORTH 0
154#define APL_GPIO_NORTHWEST 1
155#define APL_GPIO_WEST 2
156#define APL_GPIO_SOUTHWEST 3
157
158#define APL_GPIO_NR_DEVICES 4
159#define APL_GPIO_NR_RESOURCES 4
160
161/* Offset data for Apollo Lake GPIO controllers */
162static const resource_size_t apl_gpio_offsets[APL_GPIO_NR_RESOURCES] = {
163 [APL_GPIO_NORTH] = 0xc50000,
164 [APL_GPIO_NORTHWEST] = 0xc40000,
165 [APL_GPIO_WEST] = 0xc70000,
166 [APL_GPIO_SOUTHWEST] = 0xc00000,
167};
168
169#define APL_GPIO_IRQ 14
170
171static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = {
172 [APL_GPIO_NORTH] = {
173 DEFINE_RES_MEM(0, 0),
174 DEFINE_RES_IRQ(APL_GPIO_IRQ),
175 },
176 [APL_GPIO_NORTHWEST] = {
177 DEFINE_RES_MEM(0, 0),
178 DEFINE_RES_IRQ(APL_GPIO_IRQ),
179 },
180 [APL_GPIO_WEST] = {
181 DEFINE_RES_MEM(0, 0),
182 DEFINE_RES_IRQ(APL_GPIO_IRQ),
183 },
184 [APL_GPIO_SOUTHWEST] = {
185 DEFINE_RES_MEM(0, 0),
186 DEFINE_RES_IRQ(APL_GPIO_IRQ),
187 },
188};
189
190static struct resource *apl_gpio_mem_resources[APL_GPIO_NR_RESOURCES] = {
191 [APL_GPIO_NORTH] = &apl_gpio_resources[APL_GPIO_NORTH][0],
192 [APL_GPIO_NORTHWEST] = &apl_gpio_resources[APL_GPIO_NORTHWEST][0],
193 [APL_GPIO_WEST] = &apl_gpio_resources[APL_GPIO_WEST][0],
194 [APL_GPIO_SOUTHWEST] = &apl_gpio_resources[APL_GPIO_SOUTHWEST][0],
195};
196
197static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = {
198 [APL_GPIO_NORTH] = {
199 .name = "apollolake-pinctrl",
200 .id = APL_GPIO_NORTH,
201 .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]),
202 .resources = apl_gpio_resources[APL_GPIO_NORTH],
203 .ignore_resource_conflicts = true,
204 },
205 [APL_GPIO_NORTHWEST] = {
206 .name = "apollolake-pinctrl",
207 .id = APL_GPIO_NORTHWEST,
208 .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]),
209 .resources = apl_gpio_resources[APL_GPIO_NORTHWEST],
210 .ignore_resource_conflicts = true,
211 },
212 [APL_GPIO_WEST] = {
213 .name = "apollolake-pinctrl",
214 .id = APL_GPIO_WEST,
215 .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]),
216 .resources = apl_gpio_resources[APL_GPIO_WEST],
217 .ignore_resource_conflicts = true,
218 },
219 [APL_GPIO_SOUTHWEST] = {
220 .name = "apollolake-pinctrl",
221 .id = APL_GPIO_SOUTHWEST,
222 .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]),
223 .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST],
224 .ignore_resource_conflicts = true,
225 },
226};
227
228static const struct lpc_ich_gpio_info apl_gpio_info = {
229 .hid = "INT3452",
230 .devices = apl_gpio_devices,
231 .nr_devices = ARRAY_SIZE(apl_gpio_devices),
232 .resources = apl_gpio_mem_resources,
233 .nr_resources = ARRAY_SIZE(apl_gpio_mem_resources),
234 .offsets = apl_gpio_offsets,
235};
236
237#define DNV_GPIO_NORTH 0
238#define DNV_GPIO_SOUTH 1
239
240#define DNV_GPIO_NR_DEVICES 1
241#define DNV_GPIO_NR_RESOURCES 2
242
243/* Offset data for Denverton GPIO controllers */
244static const resource_size_t dnv_gpio_offsets[DNV_GPIO_NR_RESOURCES] = {
245 [DNV_GPIO_NORTH] = 0xc20000,
246 [DNV_GPIO_SOUTH] = 0xc50000,
247};
248
249#define DNV_GPIO_IRQ 14
250
251static struct resource dnv_gpio_resources[DNV_GPIO_NR_RESOURCES + 1] = {
252 [DNV_GPIO_NORTH] = DEFINE_RES_MEM(0, 0),
253 [DNV_GPIO_SOUTH] = DEFINE_RES_MEM(0, 0),
254 DEFINE_RES_IRQ(DNV_GPIO_IRQ),
255};
256
257static struct resource *dnv_gpio_mem_resources[DNV_GPIO_NR_RESOURCES] = {
258 [DNV_GPIO_NORTH] = &dnv_gpio_resources[DNV_GPIO_NORTH],
259 [DNV_GPIO_SOUTH] = &dnv_gpio_resources[DNV_GPIO_SOUTH],
260};
261
262static const struct mfd_cell dnv_gpio_devices[DNV_GPIO_NR_DEVICES] = {
263 {
264 .name = "denverton-pinctrl",
265 .num_resources = ARRAY_SIZE(dnv_gpio_resources),
266 .resources = dnv_gpio_resources,
267 .ignore_resource_conflicts = true,
268 },
269};
270
271static const struct lpc_ich_gpio_info dnv_gpio_info = {
272 .hid = "INTC3000",
273 .devices = dnv_gpio_devices,
274 .nr_devices = ARRAY_SIZE(dnv_gpio_devices),
275 .resources = dnv_gpio_mem_resources,
276 .nr_resources = ARRAY_SIZE(dnv_gpio_mem_resources),
277 .offsets = dnv_gpio_offsets,
278};
279
280static struct mfd_cell lpc_ich_spi_cell = {
281 .name = "intel-spi",
282 .num_resources = ARRAY_SIZE(intel_spi_res),
283 .resources = intel_spi_res,
284 .ignore_resource_conflicts = true,
285};
286
287/* chipset related info */
288enum lpc_chipsets {
289 LPC_ICH = 0, /* ICH */
290 LPC_ICH0, /* ICH0 */
291 LPC_ICH2, /* ICH2 */
292 LPC_ICH2M, /* ICH2-M */
293 LPC_ICH3, /* ICH3-S */
294 LPC_ICH3M, /* ICH3-M */
295 LPC_ICH4, /* ICH4 */
296 LPC_ICH4M, /* ICH4-M */
297 LPC_CICH, /* C-ICH */
298 LPC_ICH5, /* ICH5 & ICH5R */
299 LPC_6300ESB, /* 6300ESB */
300 LPC_ICH6, /* ICH6 & ICH6R */
301 LPC_ICH6M, /* ICH6-M */
302 LPC_ICH6W, /* ICH6W & ICH6RW */
303 LPC_631XESB, /* 631xESB/632xESB */
304 LPC_ICH7, /* ICH7 & ICH7R */
305 LPC_ICH7DH, /* ICH7DH */
306 LPC_ICH7M, /* ICH7-M & ICH7-U */
307 LPC_ICH7MDH, /* ICH7-M DH */
308 LPC_NM10, /* NM10 */
309 LPC_ICH8, /* ICH8 & ICH8R */
310 LPC_ICH8DH, /* ICH8DH */
311 LPC_ICH8DO, /* ICH8DO */
312 LPC_ICH8M, /* ICH8M */
313 LPC_ICH8ME, /* ICH8M-E */
314 LPC_ICH9, /* ICH9 */
315 LPC_ICH9R, /* ICH9R */
316 LPC_ICH9DH, /* ICH9DH */
317 LPC_ICH9DO, /* ICH9DO */
318 LPC_ICH9M, /* ICH9M */
319 LPC_ICH9ME, /* ICH9M-E */
320 LPC_ICH10, /* ICH10 */
321 LPC_ICH10R, /* ICH10R */
322 LPC_ICH10D, /* ICH10D */
323 LPC_ICH10DO, /* ICH10DO */
324 LPC_PCH, /* PCH Desktop Full Featured */
325 LPC_PCHM, /* PCH Mobile Full Featured */
326 LPC_P55, /* P55 */
327 LPC_PM55, /* PM55 */
328 LPC_H55, /* H55 */
329 LPC_QM57, /* QM57 */
330 LPC_H57, /* H57 */
331 LPC_HM55, /* HM55 */
332 LPC_Q57, /* Q57 */
333 LPC_HM57, /* HM57 */
334 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
335 LPC_QS57, /* QS57 */
336 LPC_3400, /* 3400 */
337 LPC_3420, /* 3420 */
338 LPC_3450, /* 3450 */
339 LPC_EP80579, /* EP80579 */
340 LPC_CPT, /* Cougar Point */
341 LPC_CPTD, /* Cougar Point Desktop */
342 LPC_CPTM, /* Cougar Point Mobile */
343 LPC_PBG, /* Patsburg */
344 LPC_DH89XXCC, /* DH89xxCC */
345 LPC_PPT, /* Panther Point */
346 LPC_LPT, /* Lynx Point */
347 LPC_LPT_LP, /* Lynx Point-LP */
348 LPC_WBG, /* Wellsburg */
349 LPC_AVN, /* Avoton SoC */
350 LPC_BAYTRAIL, /* Bay Trail SoC */
351 LPC_COLETO, /* Coleto Creek */
352 LPC_WPT_LP, /* Wildcat Point-LP */
353 LPC_BRASWELL, /* Braswell SoC */
354 LPC_LEWISBURG, /* Lewisburg */
355 LPC_9S, /* 9 Series */
356 LPC_APL, /* Apollo Lake SoC */
357 LPC_DNV, /* Denverton SoC */
358 LPC_GLK, /* Gemini Lake SoC */
359 LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
360};
361
362struct lpc_ich_priv {
363 enum lpc_chipsets chipset;
364
365 int abase; /* ACPI base */
366 int actrl_pbase; /* ACPI control or PMC base */
367 int gbase; /* GPIO base */
368 int gctrl; /* GPIO control */
369
370 int abase_save; /* Cached ACPI base value */
371 int actrl_pbase_save; /* Cached ACPI control or PMC base value */
372 int gctrl_save; /* Cached GPIO control value */
373};
374
375static struct lpc_ich_info lpc_chipset_info[] = {
376 [LPC_ICH] = {
377 .name = "ICH",
378 .iTCO_version = 1,
379 },
380 [LPC_ICH0] = {
381 .name = "ICH0",
382 .iTCO_version = 1,
383 },
384 [LPC_ICH2] = {
385 .name = "ICH2",
386 .iTCO_version = 1,
387 },
388 [LPC_ICH2M] = {
389 .name = "ICH2-M",
390 .iTCO_version = 1,
391 },
392 [LPC_ICH3] = {
393 .name = "ICH3-S",
394 .iTCO_version = 1,
395 },
396 [LPC_ICH3M] = {
397 .name = "ICH3-M",
398 .iTCO_version = 1,
399 },
400 [LPC_ICH4] = {
401 .name = "ICH4",
402 .iTCO_version = 1,
403 },
404 [LPC_ICH4M] = {
405 .name = "ICH4-M",
406 .iTCO_version = 1,
407 },
408 [LPC_CICH] = {
409 .name = "C-ICH",
410 .iTCO_version = 1,
411 },
412 [LPC_ICH5] = {
413 .name = "ICH5 or ICH5R",
414 .iTCO_version = 1,
415 },
416 [LPC_6300ESB] = {
417 .name = "6300ESB",
418 .iTCO_version = 1,
419 },
420 [LPC_ICH6] = {
421 .name = "ICH6 or ICH6R",
422 .iTCO_version = 2,
423 .gpio_version = ICH_V6_GPIO,
424 },
425 [LPC_ICH6M] = {
426 .name = "ICH6-M",
427 .iTCO_version = 2,
428 .gpio_version = ICH_V6_GPIO,
429 },
430 [LPC_ICH6W] = {
431 .name = "ICH6W or ICH6RW",
432 .iTCO_version = 2,
433 .gpio_version = ICH_V6_GPIO,
434 },
435 [LPC_631XESB] = {
436 .name = "631xESB/632xESB",
437 .iTCO_version = 2,
438 .gpio_version = ICH_V6_GPIO,
439 },
440 [LPC_ICH7] = {
441 .name = "ICH7 or ICH7R",
442 .iTCO_version = 2,
443 .gpio_version = ICH_V7_GPIO,
444 },
445 [LPC_ICH7DH] = {
446 .name = "ICH7DH",
447 .iTCO_version = 2,
448 .gpio_version = ICH_V7_GPIO,
449 },
450 [LPC_ICH7M] = {
451 .name = "ICH7-M or ICH7-U",
452 .iTCO_version = 2,
453 .gpio_version = ICH_V7_GPIO,
454 },
455 [LPC_ICH7MDH] = {
456 .name = "ICH7-M DH",
457 .iTCO_version = 2,
458 .gpio_version = ICH_V7_GPIO,
459 },
460 [LPC_NM10] = {
461 .name = "NM10",
462 .iTCO_version = 2,
463 .gpio_version = ICH_V7_GPIO,
464 },
465 [LPC_ICH8] = {
466 .name = "ICH8 or ICH8R",
467 .iTCO_version = 2,
468 .gpio_version = ICH_V7_GPIO,
469 },
470 [LPC_ICH8DH] = {
471 .name = "ICH8DH",
472 .iTCO_version = 2,
473 .gpio_version = ICH_V7_GPIO,
474 },
475 [LPC_ICH8DO] = {
476 .name = "ICH8DO",
477 .iTCO_version = 2,
478 .gpio_version = ICH_V7_GPIO,
479 },
480 [LPC_ICH8M] = {
481 .name = "ICH8M",
482 .iTCO_version = 2,
483 .gpio_version = ICH_V7_GPIO,
484 },
485 [LPC_ICH8ME] = {
486 .name = "ICH8M-E",
487 .iTCO_version = 2,
488 .gpio_version = ICH_V7_GPIO,
489 },
490 [LPC_ICH9] = {
491 .name = "ICH9",
492 .iTCO_version = 2,
493 .gpio_version = ICH_V9_GPIO,
494 },
495 [LPC_ICH9R] = {
496 .name = "ICH9R",
497 .iTCO_version = 2,
498 .gpio_version = ICH_V9_GPIO,
499 },
500 [LPC_ICH9DH] = {
501 .name = "ICH9DH",
502 .iTCO_version = 2,
503 .gpio_version = ICH_V9_GPIO,
504 },
505 [LPC_ICH9DO] = {
506 .name = "ICH9DO",
507 .iTCO_version = 2,
508 .gpio_version = ICH_V9_GPIO,
509 },
510 [LPC_ICH9M] = {
511 .name = "ICH9M",
512 .iTCO_version = 2,
513 .gpio_version = ICH_V9_GPIO,
514 },
515 [LPC_ICH9ME] = {
516 .name = "ICH9M-E",
517 .iTCO_version = 2,
518 .gpio_version = ICH_V9_GPIO,
519 },
520 [LPC_ICH10] = {
521 .name = "ICH10",
522 .iTCO_version = 2,
523 .gpio_version = ICH_V10CONS_GPIO,
524 },
525 [LPC_ICH10R] = {
526 .name = "ICH10R",
527 .iTCO_version = 2,
528 .gpio_version = ICH_V10CONS_GPIO,
529 },
530 [LPC_ICH10D] = {
531 .name = "ICH10D",
532 .iTCO_version = 2,
533 .gpio_version = ICH_V10CORP_GPIO,
534 },
535 [LPC_ICH10DO] = {
536 .name = "ICH10DO",
537 .iTCO_version = 2,
538 .gpio_version = ICH_V10CORP_GPIO,
539 },
540 [LPC_PCH] = {
541 .name = "PCH Desktop Full Featured",
542 .iTCO_version = 2,
543 .gpio_version = ICH_V5_GPIO,
544 },
545 [LPC_PCHM] = {
546 .name = "PCH Mobile Full Featured",
547 .iTCO_version = 2,
548 .gpio_version = ICH_V5_GPIO,
549 },
550 [LPC_P55] = {
551 .name = "P55",
552 .iTCO_version = 2,
553 .gpio_version = ICH_V5_GPIO,
554 },
555 [LPC_PM55] = {
556 .name = "PM55",
557 .iTCO_version = 2,
558 .gpio_version = ICH_V5_GPIO,
559 },
560 [LPC_H55] = {
561 .name = "H55",
562 .iTCO_version = 2,
563 .gpio_version = ICH_V5_GPIO,
564 },
565 [LPC_QM57] = {
566 .name = "QM57",
567 .iTCO_version = 2,
568 .gpio_version = ICH_V5_GPIO,
569 },
570 [LPC_H57] = {
571 .name = "H57",
572 .iTCO_version = 2,
573 .gpio_version = ICH_V5_GPIO,
574 },
575 [LPC_HM55] = {
576 .name = "HM55",
577 .iTCO_version = 2,
578 .gpio_version = ICH_V5_GPIO,
579 },
580 [LPC_Q57] = {
581 .name = "Q57",
582 .iTCO_version = 2,
583 .gpio_version = ICH_V5_GPIO,
584 },
585 [LPC_HM57] = {
586 .name = "HM57",
587 .iTCO_version = 2,
588 .gpio_version = ICH_V5_GPIO,
589 },
590 [LPC_PCHMSFF] = {
591 .name = "PCH Mobile SFF Full Featured",
592 .iTCO_version = 2,
593 .gpio_version = ICH_V5_GPIO,
594 },
595 [LPC_QS57] = {
596 .name = "QS57",
597 .iTCO_version = 2,
598 .gpio_version = ICH_V5_GPIO,
599 },
600 [LPC_3400] = {
601 .name = "3400",
602 .iTCO_version = 2,
603 .gpio_version = ICH_V5_GPIO,
604 },
605 [LPC_3420] = {
606 .name = "3420",
607 .iTCO_version = 2,
608 .gpio_version = ICH_V5_GPIO,
609 },
610 [LPC_3450] = {
611 .name = "3450",
612 .iTCO_version = 2,
613 .gpio_version = ICH_V5_GPIO,
614 },
615 [LPC_EP80579] = {
616 .name = "EP80579",
617 .iTCO_version = 2,
618 },
619 [LPC_CPT] = {
620 .name = "Cougar Point",
621 .iTCO_version = 2,
622 .gpio_version = ICH_V5_GPIO,
623 },
624 [LPC_CPTD] = {
625 .name = "Cougar Point Desktop",
626 .iTCO_version = 2,
627 .gpio_version = ICH_V5_GPIO,
628 },
629 [LPC_CPTM] = {
630 .name = "Cougar Point Mobile",
631 .iTCO_version = 2,
632 .gpio_version = ICH_V5_GPIO,
633 },
634 [LPC_PBG] = {
635 .name = "Patsburg",
636 .iTCO_version = 2,
637 },
638 [LPC_DH89XXCC] = {
639 .name = "DH89xxCC",
640 .iTCO_version = 2,
641 .gpio_version = ICH_V5_GPIO,
642 },
643 [LPC_PPT] = {
644 .name = "Panther Point",
645 .iTCO_version = 2,
646 .gpio_version = ICH_V5_GPIO,
647 },
648 [LPC_LPT] = {
649 .name = "Lynx Point",
650 .iTCO_version = 2,
651 .gpio_version = ICH_V5_GPIO,
652 .spi_type = INTEL_SPI_LPT,
653 },
654 [LPC_LPT_LP] = {
655 .name = "Lynx Point_LP",
656 .iTCO_version = 2,
657 .spi_type = INTEL_SPI_LPT,
658 },
659 [LPC_WBG] = {
660 .name = "Wellsburg",
661 .iTCO_version = 2,
662 },
663 [LPC_AVN] = {
664 .name = "Avoton SoC",
665 .iTCO_version = 3,
666 .gpio_version = AVOTON_GPIO,
667 .spi_type = INTEL_SPI_BYT,
668 },
669 [LPC_BAYTRAIL] = {
670 .name = "Bay Trail SoC",
671 .iTCO_version = 3,
672 .spi_type = INTEL_SPI_BYT,
673 },
674 [LPC_COLETO] = {
675 .name = "Coleto Creek",
676 .iTCO_version = 2,
677 },
678 [LPC_WPT_LP] = {
679 .name = "Wildcat Point_LP",
680 .iTCO_version = 2,
681 .spi_type = INTEL_SPI_LPT,
682 },
683 [LPC_BRASWELL] = {
684 .name = "Braswell SoC",
685 .iTCO_version = 3,
686 .spi_type = INTEL_SPI_BYT,
687 },
688 [LPC_LEWISBURG] = {
689 .name = "Lewisburg",
690 .iTCO_version = 2,
691 },
692 [LPC_9S] = {
693 .name = "9 Series",
694 .iTCO_version = 2,
695 .gpio_version = ICH_V5_GPIO,
696 },
697 [LPC_APL] = {
698 .name = "Apollo Lake SoC",
699 .iTCO_version = 5,
700 .gpio_info = &apl_gpio_info,
701 .spi_type = INTEL_SPI_BXT,
702 },
703 [LPC_DNV] = {
704 .name = "Denverton SoC",
705 .gpio_info = &dnv_gpio_info,
706 },
707 [LPC_GLK] = {
708 .name = "Gemini Lake SoC",
709 .spi_type = INTEL_SPI_BXT,
710 },
711 [LPC_COUGARMOUNTAIN] = {
712 .name = "Cougar Mountain SoC",
713 .iTCO_version = 3,
714 },
715};
716
717/*
718 * This data only exists for exporting the supported PCI ids
719 * via MODULE_DEVICE_TABLE. We do not actually register a
720 * pci_driver, because the I/O Controller Hub has also other
721 * functions that probably will be registered by other drivers.
722 */
723static const struct pci_device_id lpc_ich_ids[] = {
724 { PCI_VDEVICE(INTEL, 0x0f1c), .driver_data = LPC_BAYTRAIL },
725 { PCI_VDEVICE(INTEL, 0x19dc), .driver_data = LPC_DNV },
726 { PCI_VDEVICE(INTEL, 0x1c41), .driver_data = LPC_CPT },
727 { PCI_VDEVICE(INTEL, 0x1c42), .driver_data = LPC_CPTD },
728 { PCI_VDEVICE(INTEL, 0x1c43), .driver_data = LPC_CPTM },
729 { PCI_VDEVICE(INTEL, 0x1c44), .driver_data = LPC_CPT },
730 { PCI_VDEVICE(INTEL, 0x1c45), .driver_data = LPC_CPT },
731 { PCI_VDEVICE(INTEL, 0x1c46), .driver_data = LPC_CPT },
732 { PCI_VDEVICE(INTEL, 0x1c47), .driver_data = LPC_CPT },
733 { PCI_VDEVICE(INTEL, 0x1c48), .driver_data = LPC_CPT },
734 { PCI_VDEVICE(INTEL, 0x1c49), .driver_data = LPC_CPT },
735 { PCI_VDEVICE(INTEL, 0x1c4a), .driver_data = LPC_CPT },
736 { PCI_VDEVICE(INTEL, 0x1c4b), .driver_data = LPC_CPT },
737 { PCI_VDEVICE(INTEL, 0x1c4c), .driver_data = LPC_CPT },
738 { PCI_VDEVICE(INTEL, 0x1c4d), .driver_data = LPC_CPT },
739 { PCI_VDEVICE(INTEL, 0x1c4e), .driver_data = LPC_CPT },
740 { PCI_VDEVICE(INTEL, 0x1c4f), .driver_data = LPC_CPT },
741 { PCI_VDEVICE(INTEL, 0x1c50), .driver_data = LPC_CPT },
742 { PCI_VDEVICE(INTEL, 0x1c51), .driver_data = LPC_CPT },
743 { PCI_VDEVICE(INTEL, 0x1c52), .driver_data = LPC_CPT },
744 { PCI_VDEVICE(INTEL, 0x1c53), .driver_data = LPC_CPT },
745 { PCI_VDEVICE(INTEL, 0x1c54), .driver_data = LPC_CPT },
746 { PCI_VDEVICE(INTEL, 0x1c55), .driver_data = LPC_CPT },
747 { PCI_VDEVICE(INTEL, 0x1c56), .driver_data = LPC_CPT },
748 { PCI_VDEVICE(INTEL, 0x1c57), .driver_data = LPC_CPT },
749 { PCI_VDEVICE(INTEL, 0x1c58), .driver_data = LPC_CPT },
750 { PCI_VDEVICE(INTEL, 0x1c59), .driver_data = LPC_CPT },
751 { PCI_VDEVICE(INTEL, 0x1c5a), .driver_data = LPC_CPT },
752 { PCI_VDEVICE(INTEL, 0x1c5b), .driver_data = LPC_CPT },
753 { PCI_VDEVICE(INTEL, 0x1c5c), .driver_data = LPC_CPT },
754 { PCI_VDEVICE(INTEL, 0x1c5d), .driver_data = LPC_CPT },
755 { PCI_VDEVICE(INTEL, 0x1c5e), .driver_data = LPC_CPT },
756 { PCI_VDEVICE(INTEL, 0x1c5f), .driver_data = LPC_CPT },
757 { PCI_VDEVICE(INTEL, 0x1d40), .driver_data = LPC_PBG },
758 { PCI_VDEVICE(INTEL, 0x1d41), .driver_data = LPC_PBG },
759 { PCI_VDEVICE(INTEL, 0x1e40), .driver_data = LPC_PPT },
760 { PCI_VDEVICE(INTEL, 0x1e41), .driver_data = LPC_PPT },
761 { PCI_VDEVICE(INTEL, 0x1e42), .driver_data = LPC_PPT },
762 { PCI_VDEVICE(INTEL, 0x1e43), .driver_data = LPC_PPT },
763 { PCI_VDEVICE(INTEL, 0x1e44), .driver_data = LPC_PPT },
764 { PCI_VDEVICE(INTEL, 0x1e45), .driver_data = LPC_PPT },
765 { PCI_VDEVICE(INTEL, 0x1e46), .driver_data = LPC_PPT },
766 { PCI_VDEVICE(INTEL, 0x1e47), .driver_data = LPC_PPT },
767 { PCI_VDEVICE(INTEL, 0x1e48), .driver_data = LPC_PPT },
768 { PCI_VDEVICE(INTEL, 0x1e49), .driver_data = LPC_PPT },
769 { PCI_VDEVICE(INTEL, 0x1e4a), .driver_data = LPC_PPT },
770 { PCI_VDEVICE(INTEL, 0x1e4b), .driver_data = LPC_PPT },
771 { PCI_VDEVICE(INTEL, 0x1e4c), .driver_data = LPC_PPT },
772 { PCI_VDEVICE(INTEL, 0x1e4d), .driver_data = LPC_PPT },
773 { PCI_VDEVICE(INTEL, 0x1e4e), .driver_data = LPC_PPT },
774 { PCI_VDEVICE(INTEL, 0x1e4f), .driver_data = LPC_PPT },
775 { PCI_VDEVICE(INTEL, 0x1e50), .driver_data = LPC_PPT },
776 { PCI_VDEVICE(INTEL, 0x1e51), .driver_data = LPC_PPT },
777 { PCI_VDEVICE(INTEL, 0x1e52), .driver_data = LPC_PPT },
778 { PCI_VDEVICE(INTEL, 0x1e53), .driver_data = LPC_PPT },
779 { PCI_VDEVICE(INTEL, 0x1e54), .driver_data = LPC_PPT },
780 { PCI_VDEVICE(INTEL, 0x1e55), .driver_data = LPC_PPT },
781 { PCI_VDEVICE(INTEL, 0x1e56), .driver_data = LPC_PPT },
782 { PCI_VDEVICE(INTEL, 0x1e57), .driver_data = LPC_PPT },
783 { PCI_VDEVICE(INTEL, 0x1e58), .driver_data = LPC_PPT },
784 { PCI_VDEVICE(INTEL, 0x1e59), .driver_data = LPC_PPT },
785 { PCI_VDEVICE(INTEL, 0x1e5a), .driver_data = LPC_PPT },
786 { PCI_VDEVICE(INTEL, 0x1e5b), .driver_data = LPC_PPT },
787 { PCI_VDEVICE(INTEL, 0x1e5c), .driver_data = LPC_PPT },
788 { PCI_VDEVICE(INTEL, 0x1e5d), .driver_data = LPC_PPT },
789 { PCI_VDEVICE(INTEL, 0x1e5e), .driver_data = LPC_PPT },
790 { PCI_VDEVICE(INTEL, 0x1e5f), .driver_data = LPC_PPT },
791 { PCI_VDEVICE(INTEL, 0x1f38), .driver_data = LPC_AVN },
792 { PCI_VDEVICE(INTEL, 0x1f39), .driver_data = LPC_AVN },
793 { PCI_VDEVICE(INTEL, 0x1f3a), .driver_data = LPC_AVN },
794 { PCI_VDEVICE(INTEL, 0x1f3b), .driver_data = LPC_AVN },
795 { PCI_VDEVICE(INTEL, 0x229c), .driver_data = LPC_BRASWELL },
796 { PCI_VDEVICE(INTEL, 0x2310), .driver_data = LPC_DH89XXCC },
797 { PCI_VDEVICE(INTEL, 0x2390), .driver_data = LPC_COLETO },
798 { PCI_VDEVICE(INTEL, 0x2410), .driver_data = LPC_ICH },
799 { PCI_VDEVICE(INTEL, 0x2420), .driver_data = LPC_ICH0 },
800 { PCI_VDEVICE(INTEL, 0x2440), .driver_data = LPC_ICH2 },
801 { PCI_VDEVICE(INTEL, 0x244c), .driver_data = LPC_ICH2M },
802 { PCI_VDEVICE(INTEL, 0x2450), .driver_data = LPC_CICH },
803 { PCI_VDEVICE(INTEL, 0x2480), .driver_data = LPC_ICH3 },
804 { PCI_VDEVICE(INTEL, 0x248c), .driver_data = LPC_ICH3M },
805 { PCI_VDEVICE(INTEL, 0x24c0), .driver_data = LPC_ICH4 },
806 { PCI_VDEVICE(INTEL, 0x24cc), .driver_data = LPC_ICH4M },
807 { PCI_VDEVICE(INTEL, 0x24d0), .driver_data = LPC_ICH5 },
808 { PCI_VDEVICE(INTEL, 0x25a1), .driver_data = LPC_6300ESB },
809 { PCI_VDEVICE(INTEL, 0x2640), .driver_data = LPC_ICH6 },
810 { PCI_VDEVICE(INTEL, 0x2641), .driver_data = LPC_ICH6M },
811 { PCI_VDEVICE(INTEL, 0x2642), .driver_data = LPC_ICH6W },
812 { PCI_VDEVICE(INTEL, 0x2670), .driver_data = LPC_631XESB },
813 { PCI_VDEVICE(INTEL, 0x2671), .driver_data = LPC_631XESB },
814 { PCI_VDEVICE(INTEL, 0x2672), .driver_data = LPC_631XESB },
815 { PCI_VDEVICE(INTEL, 0x2673), .driver_data = LPC_631XESB },
816 { PCI_VDEVICE(INTEL, 0x2674), .driver_data = LPC_631XESB },
817 { PCI_VDEVICE(INTEL, 0x2675), .driver_data = LPC_631XESB },
818 { PCI_VDEVICE(INTEL, 0x2676), .driver_data = LPC_631XESB },
819 { PCI_VDEVICE(INTEL, 0x2677), .driver_data = LPC_631XESB },
820 { PCI_VDEVICE(INTEL, 0x2678), .driver_data = LPC_631XESB },
821 { PCI_VDEVICE(INTEL, 0x2679), .driver_data = LPC_631XESB },
822 { PCI_VDEVICE(INTEL, 0x267a), .driver_data = LPC_631XESB },
823 { PCI_VDEVICE(INTEL, 0x267b), .driver_data = LPC_631XESB },
824 { PCI_VDEVICE(INTEL, 0x267c), .driver_data = LPC_631XESB },
825 { PCI_VDEVICE(INTEL, 0x267d), .driver_data = LPC_631XESB },
826 { PCI_VDEVICE(INTEL, 0x267e), .driver_data = LPC_631XESB },
827 { PCI_VDEVICE(INTEL, 0x267f), .driver_data = LPC_631XESB },
828 { PCI_VDEVICE(INTEL, 0x27b0), .driver_data = LPC_ICH7DH },
829 { PCI_VDEVICE(INTEL, 0x27b8), .driver_data = LPC_ICH7 },
830 { PCI_VDEVICE(INTEL, 0x27b9), .driver_data = LPC_ICH7M },
831 { PCI_VDEVICE(INTEL, 0x27bc), .driver_data = LPC_NM10 },
832 { PCI_VDEVICE(INTEL, 0x27bd), .driver_data = LPC_ICH7MDH },
833 { PCI_VDEVICE(INTEL, 0x2810), .driver_data = LPC_ICH8 },
834 { PCI_VDEVICE(INTEL, 0x2811), .driver_data = LPC_ICH8ME },
835 { PCI_VDEVICE(INTEL, 0x2812), .driver_data = LPC_ICH8DH },
836 { PCI_VDEVICE(INTEL, 0x2814), .driver_data = LPC_ICH8DO },
837 { PCI_VDEVICE(INTEL, 0x2815), .driver_data = LPC_ICH8M },
838 { PCI_VDEVICE(INTEL, 0x2912), .driver_data = LPC_ICH9DH },
839 { PCI_VDEVICE(INTEL, 0x2914), .driver_data = LPC_ICH9DO },
840 { PCI_VDEVICE(INTEL, 0x2916), .driver_data = LPC_ICH9R },
841 { PCI_VDEVICE(INTEL, 0x2917), .driver_data = LPC_ICH9ME },
842 { PCI_VDEVICE(INTEL, 0x2918), .driver_data = LPC_ICH9 },
843 { PCI_VDEVICE(INTEL, 0x2919), .driver_data = LPC_ICH9M },
844 { PCI_VDEVICE(INTEL, 0x2b9c), .driver_data = LPC_COUGARMOUNTAIN },
845 { PCI_VDEVICE(INTEL, 0x3197), .driver_data = LPC_GLK },
846 { PCI_VDEVICE(INTEL, 0x31e8), .driver_data = LPC_GLK },
847 { PCI_VDEVICE(INTEL, 0x3a14), .driver_data = LPC_ICH10DO },
848 { PCI_VDEVICE(INTEL, 0x3a16), .driver_data = LPC_ICH10R },
849 { PCI_VDEVICE(INTEL, 0x3a18), .driver_data = LPC_ICH10 },
850 { PCI_VDEVICE(INTEL, 0x3a1a), .driver_data = LPC_ICH10D },
851 { PCI_VDEVICE(INTEL, 0x3b00), .driver_data = LPC_PCH },
852 { PCI_VDEVICE(INTEL, 0x3b01), .driver_data = LPC_PCHM },
853 { PCI_VDEVICE(INTEL, 0x3b02), .driver_data = LPC_P55 },
854 { PCI_VDEVICE(INTEL, 0x3b03), .driver_data = LPC_PM55 },
855 { PCI_VDEVICE(INTEL, 0x3b06), .driver_data = LPC_H55 },
856 { PCI_VDEVICE(INTEL, 0x3b07), .driver_data = LPC_QM57 },
857 { PCI_VDEVICE(INTEL, 0x3b08), .driver_data = LPC_H57 },
858 { PCI_VDEVICE(INTEL, 0x3b09), .driver_data = LPC_HM55 },
859 { PCI_VDEVICE(INTEL, 0x3b0a), .driver_data = LPC_Q57 },
860 { PCI_VDEVICE(INTEL, 0x3b0b), .driver_data = LPC_HM57 },
861 { PCI_VDEVICE(INTEL, 0x3b0d), .driver_data = LPC_PCHMSFF },
862 { PCI_VDEVICE(INTEL, 0x3b0f), .driver_data = LPC_QS57 },
863 { PCI_VDEVICE(INTEL, 0x3b12), .driver_data = LPC_3400 },
864 { PCI_VDEVICE(INTEL, 0x3b14), .driver_data = LPC_3420 },
865 { PCI_VDEVICE(INTEL, 0x3b16), .driver_data = LPC_3450 },
866 { PCI_VDEVICE(INTEL, 0x5031), .driver_data = LPC_EP80579 },
867 { PCI_VDEVICE(INTEL, 0x5ae8), .driver_data = LPC_APL },
868 { PCI_VDEVICE(INTEL, 0x8c40), .driver_data = LPC_LPT },
869 { PCI_VDEVICE(INTEL, 0x8c41), .driver_data = LPC_LPT },
870 { PCI_VDEVICE(INTEL, 0x8c42), .driver_data = LPC_LPT },
871 { PCI_VDEVICE(INTEL, 0x8c43), .driver_data = LPC_LPT },
872 { PCI_VDEVICE(INTEL, 0x8c44), .driver_data = LPC_LPT },
873 { PCI_VDEVICE(INTEL, 0x8c45), .driver_data = LPC_LPT },
874 { PCI_VDEVICE(INTEL, 0x8c46), .driver_data = LPC_LPT },
875 { PCI_VDEVICE(INTEL, 0x8c47), .driver_data = LPC_LPT },
876 { PCI_VDEVICE(INTEL, 0x8c48), .driver_data = LPC_LPT },
877 { PCI_VDEVICE(INTEL, 0x8c49), .driver_data = LPC_LPT },
878 { PCI_VDEVICE(INTEL, 0x8c4a), .driver_data = LPC_LPT },
879 { PCI_VDEVICE(INTEL, 0x8c4b), .driver_data = LPC_LPT },
880 { PCI_VDEVICE(INTEL, 0x8c4c), .driver_data = LPC_LPT },
881 { PCI_VDEVICE(INTEL, 0x8c4d), .driver_data = LPC_LPT },
882 { PCI_VDEVICE(INTEL, 0x8c4e), .driver_data = LPC_LPT },
883 { PCI_VDEVICE(INTEL, 0x8c4f), .driver_data = LPC_LPT },
884 { PCI_VDEVICE(INTEL, 0x8c50), .driver_data = LPC_LPT },
885 { PCI_VDEVICE(INTEL, 0x8c51), .driver_data = LPC_LPT },
886 { PCI_VDEVICE(INTEL, 0x8c52), .driver_data = LPC_LPT },
887 { PCI_VDEVICE(INTEL, 0x8c53), .driver_data = LPC_LPT },
888 { PCI_VDEVICE(INTEL, 0x8c54), .driver_data = LPC_LPT },
889 { PCI_VDEVICE(INTEL, 0x8c55), .driver_data = LPC_LPT },
890 { PCI_VDEVICE(INTEL, 0x8c56), .driver_data = LPC_LPT },
891 { PCI_VDEVICE(INTEL, 0x8c57), .driver_data = LPC_LPT },
892 { PCI_VDEVICE(INTEL, 0x8c58), .driver_data = LPC_LPT },
893 { PCI_VDEVICE(INTEL, 0x8c59), .driver_data = LPC_LPT },
894 { PCI_VDEVICE(INTEL, 0x8c5a), .driver_data = LPC_LPT },
895 { PCI_VDEVICE(INTEL, 0x8c5b), .driver_data = LPC_LPT },
896 { PCI_VDEVICE(INTEL, 0x8c5c), .driver_data = LPC_LPT },
897 { PCI_VDEVICE(INTEL, 0x8c5d), .driver_data = LPC_LPT },
898 { PCI_VDEVICE(INTEL, 0x8c5e), .driver_data = LPC_LPT },
899 { PCI_VDEVICE(INTEL, 0x8c5f), .driver_data = LPC_LPT },
900 { PCI_VDEVICE(INTEL, 0x8cc1), .driver_data = LPC_9S },
901 { PCI_VDEVICE(INTEL, 0x8cc2), .driver_data = LPC_9S },
902 { PCI_VDEVICE(INTEL, 0x8cc3), .driver_data = LPC_9S },
903 { PCI_VDEVICE(INTEL, 0x8cc4), .driver_data = LPC_9S },
904 { PCI_VDEVICE(INTEL, 0x8cc6), .driver_data = LPC_9S },
905 { PCI_VDEVICE(INTEL, 0x8d40), .driver_data = LPC_WBG },
906 { PCI_VDEVICE(INTEL, 0x8d41), .driver_data = LPC_WBG },
907 { PCI_VDEVICE(INTEL, 0x8d42), .driver_data = LPC_WBG },
908 { PCI_VDEVICE(INTEL, 0x8d43), .driver_data = LPC_WBG },
909 { PCI_VDEVICE(INTEL, 0x8d44), .driver_data = LPC_WBG },
910 { PCI_VDEVICE(INTEL, 0x8d45), .driver_data = LPC_WBG },
911 { PCI_VDEVICE(INTEL, 0x8d46), .driver_data = LPC_WBG },
912 { PCI_VDEVICE(INTEL, 0x8d47), .driver_data = LPC_WBG },
913 { PCI_VDEVICE(INTEL, 0x8d48), .driver_data = LPC_WBG },
914 { PCI_VDEVICE(INTEL, 0x8d49), .driver_data = LPC_WBG },
915 { PCI_VDEVICE(INTEL, 0x8d4a), .driver_data = LPC_WBG },
916 { PCI_VDEVICE(INTEL, 0x8d4b), .driver_data = LPC_WBG },
917 { PCI_VDEVICE(INTEL, 0x8d4c), .driver_data = LPC_WBG },
918 { PCI_VDEVICE(INTEL, 0x8d4d), .driver_data = LPC_WBG },
919 { PCI_VDEVICE(INTEL, 0x8d4e), .driver_data = LPC_WBG },
920 { PCI_VDEVICE(INTEL, 0x8d4f), .driver_data = LPC_WBG },
921 { PCI_VDEVICE(INTEL, 0x8d50), .driver_data = LPC_WBG },
922 { PCI_VDEVICE(INTEL, 0x8d51), .driver_data = LPC_WBG },
923 { PCI_VDEVICE(INTEL, 0x8d52), .driver_data = LPC_WBG },
924 { PCI_VDEVICE(INTEL, 0x8d53), .driver_data = LPC_WBG },
925 { PCI_VDEVICE(INTEL, 0x8d54), .driver_data = LPC_WBG },
926 { PCI_VDEVICE(INTEL, 0x8d55), .driver_data = LPC_WBG },
927 { PCI_VDEVICE(INTEL, 0x8d56), .driver_data = LPC_WBG },
928 { PCI_VDEVICE(INTEL, 0x8d57), .driver_data = LPC_WBG },
929 { PCI_VDEVICE(INTEL, 0x8d58), .driver_data = LPC_WBG },
930 { PCI_VDEVICE(INTEL, 0x8d59), .driver_data = LPC_WBG },
931 { PCI_VDEVICE(INTEL, 0x8d5a), .driver_data = LPC_WBG },
932 { PCI_VDEVICE(INTEL, 0x8d5b), .driver_data = LPC_WBG },
933 { PCI_VDEVICE(INTEL, 0x8d5c), .driver_data = LPC_WBG },
934 { PCI_VDEVICE(INTEL, 0x8d5d), .driver_data = LPC_WBG },
935 { PCI_VDEVICE(INTEL, 0x8d5e), .driver_data = LPC_WBG },
936 { PCI_VDEVICE(INTEL, 0x8d5f), .driver_data = LPC_WBG },
937 { PCI_VDEVICE(INTEL, 0x9c40), .driver_data = LPC_LPT_LP },
938 { PCI_VDEVICE(INTEL, 0x9c41), .driver_data = LPC_LPT_LP },
939 { PCI_VDEVICE(INTEL, 0x9c42), .driver_data = LPC_LPT_LP },
940 { PCI_VDEVICE(INTEL, 0x9c43), .driver_data = LPC_LPT_LP },
941 { PCI_VDEVICE(INTEL, 0x9c44), .driver_data = LPC_LPT_LP },
942 { PCI_VDEVICE(INTEL, 0x9c45), .driver_data = LPC_LPT_LP },
943 { PCI_VDEVICE(INTEL, 0x9c46), .driver_data = LPC_LPT_LP },
944 { PCI_VDEVICE(INTEL, 0x9c47), .driver_data = LPC_LPT_LP },
945 { PCI_VDEVICE(INTEL, 0x9cc1), .driver_data = LPC_WPT_LP },
946 { PCI_VDEVICE(INTEL, 0x9cc2), .driver_data = LPC_WPT_LP },
947 { PCI_VDEVICE(INTEL, 0x9cc3), .driver_data = LPC_WPT_LP },
948 { PCI_VDEVICE(INTEL, 0x9cc5), .driver_data = LPC_WPT_LP },
949 { PCI_VDEVICE(INTEL, 0x9cc6), .driver_data = LPC_WPT_LP },
950 { PCI_VDEVICE(INTEL, 0x9cc7), .driver_data = LPC_WPT_LP },
951 { PCI_VDEVICE(INTEL, 0x9cc9), .driver_data = LPC_WPT_LP },
952 { PCI_VDEVICE(INTEL, 0xa1c1), .driver_data = LPC_LEWISBURG },
953 { PCI_VDEVICE(INTEL, 0xa1c2), .driver_data = LPC_LEWISBURG },
954 { PCI_VDEVICE(INTEL, 0xa1c3), .driver_data = LPC_LEWISBURG },
955 { PCI_VDEVICE(INTEL, 0xa1c4), .driver_data = LPC_LEWISBURG },
956 { PCI_VDEVICE(INTEL, 0xa1c5), .driver_data = LPC_LEWISBURG },
957 { PCI_VDEVICE(INTEL, 0xa1c6), .driver_data = LPC_LEWISBURG },
958 { PCI_VDEVICE(INTEL, 0xa1c7), .driver_data = LPC_LEWISBURG },
959 { PCI_VDEVICE(INTEL, 0xa242), .driver_data = LPC_LEWISBURG },
960 { PCI_VDEVICE(INTEL, 0xa243), .driver_data = LPC_LEWISBURG },
961 { }, /* End of list */
962};
963MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
964
965static void lpc_ich_restore_config_space(struct pci_dev *dev)
966{
967 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
968
969 if (priv->abase_save >= 0) {
970 pci_write_config_byte(dev, priv->abase, priv->abase_save);
971 priv->abase_save = -1;
972 }
973
974 if (priv->actrl_pbase_save >= 0) {
975 pci_write_config_byte(dev, priv->actrl_pbase,
976 priv->actrl_pbase_save);
977 priv->actrl_pbase_save = -1;
978 }
979
980 if (priv->gctrl_save >= 0) {
981 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
982 priv->gctrl_save = -1;
983 }
984}
985
986static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
987{
988 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
989 u8 reg_save;
990
991 switch (lpc_chipset_info[priv->chipset].iTCO_version) {
992 case 3:
993 /*
994 * Some chipsets (eg Avoton) enable the ACPI space in the
995 * ACPI BASE register.
996 */
997 pci_read_config_byte(dev, priv->abase, &reg_save);
998 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
999 priv->abase_save = reg_save;
1000 break;
1001 default:
1002 /*
1003 * Most chipsets enable the ACPI space in the ACPI control
1004 * register.
1005 */
1006 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
1007 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
1008 priv->actrl_pbase_save = reg_save;
1009 break;
1010 }
1011}
1012
1013static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
1014{
1015 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1016 u8 reg_save;
1017
1018 pci_read_config_byte(dev, priv->gctrl, &reg_save);
1019 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
1020 priv->gctrl_save = reg_save;
1021}
1022
1023static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
1024{
1025 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1026 u8 reg_save;
1027
1028 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
1029 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
1030
1031 priv->actrl_pbase_save = reg_save;
1032}
1033
1034static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
1035{
1036 struct itco_wdt_platform_data *pdata;
1037 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1038 struct lpc_ich_info *info;
1039 struct mfd_cell *cell = &lpc_ich_wdt_cell;
1040
1041 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1042 if (!pdata)
1043 return -ENOMEM;
1044
1045 info = &lpc_chipset_info[priv->chipset];
1046
1047 pdata->version = info->iTCO_version;
1048 strscpy(pdata->name, info->name, sizeof(pdata->name));
1049
1050 cell->platform_data = pdata;
1051 cell->pdata_size = sizeof(*pdata);
1052 return 0;
1053}
1054
1055static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
1056{
1057 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1058 struct mfd_cell *cell = &lpc_ich_gpio_cell;
1059
1060 cell->platform_data = &lpc_chipset_info[priv->chipset];
1061 cell->pdata_size = sizeof(struct lpc_ich_info);
1062}
1063
1064/*
1065 * We don't check for resource conflict globally. There are 2 or 3 independent
1066 * GPIO groups and it's enough to have access to one of these to instantiate
1067 * the device.
1068 */
1069static int lpc_ich_check_conflict_gpio(struct resource *res)
1070{
1071 int ret;
1072 u8 use_gpio = 0;
1073
1074 if (resource_size(res) >= 0x50 &&
1075 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
1076 use_gpio |= 1 << 2;
1077
1078 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
1079 use_gpio |= 1 << 1;
1080
1081 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
1082 if (!ret)
1083 use_gpio |= 1 << 0;
1084
1085 return use_gpio ? use_gpio : ret;
1086}
1087
1088static int lpc_ich_init_gpio(struct pci_dev *dev)
1089{
1090 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1091 u32 base_addr_cfg;
1092 u32 base_addr;
1093 int ret;
1094 bool acpi_conflict = false;
1095 struct resource *res;
1096
1097 /* Setup power management base register */
1098 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1099 base_addr = base_addr_cfg & 0x0000ff80;
1100 if (!base_addr) {
1101 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1102 lpc_ich_gpio_cell.num_resources--;
1103 goto gpe0_done;
1104 }
1105
1106 res = &gpio_ich_res[ICH_RES_GPE0];
1107 res->start = base_addr + ACPIBASE_GPE_OFF;
1108 res->end = base_addr + ACPIBASE_GPE_END;
1109 ret = acpi_check_resource_conflict(res);
1110 if (ret) {
1111 /*
1112 * This isn't fatal for the GPIO, but we have to make sure that
1113 * the platform_device subsystem doesn't see this resource
1114 * or it will register an invalid region.
1115 */
1116 lpc_ich_gpio_cell.num_resources--;
1117 acpi_conflict = true;
1118 } else {
1119 lpc_ich_enable_acpi_space(dev);
1120 }
1121
1122gpe0_done:
1123 /* Setup GPIO base register */
1124 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
1125 base_addr = base_addr_cfg & 0x0000ff80;
1126 if (!base_addr) {
1127 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
1128 ret = -ENODEV;
1129 goto gpio_done;
1130 }
1131
1132 /* Older devices provide fewer GPIO and have a smaller resource size. */
1133 res = &gpio_ich_res[ICH_RES_GPIO];
1134 res->start = base_addr;
1135 switch (lpc_chipset_info[priv->chipset].gpio_version) {
1136 case ICH_V5_GPIO:
1137 case ICH_V10CORP_GPIO:
1138 res->end = res->start + 128 - 1;
1139 break;
1140 default:
1141 res->end = res->start + 64 - 1;
1142 break;
1143 }
1144
1145 ret = lpc_ich_check_conflict_gpio(res);
1146 if (ret < 0) {
1147 /* this isn't necessarily fatal for the GPIO */
1148 acpi_conflict = true;
1149 goto gpio_done;
1150 }
1151 lpc_chipset_info[priv->chipset].use_gpio = ret;
1152 lpc_ich_enable_gpio_space(dev);
1153
1154 lpc_ich_finalize_gpio_cell(dev);
1155 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1156 &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
1157
1158gpio_done:
1159 if (acpi_conflict)
1160 pr_warn("Resource conflict(s) found affecting %s\n",
1161 lpc_ich_gpio_cell.name);
1162 return ret;
1163}
1164
1165static int lpc_ich_init_wdt(struct pci_dev *dev)
1166{
1167 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1168 u32 base_addr_cfg;
1169 u32 base_addr;
1170 int ret;
1171 struct resource *res;
1172
1173 /* If we have ACPI based watchdog use that instead */
1174 if (acpi_has_watchdog())
1175 return -ENODEV;
1176
1177 /* Setup power management base register */
1178 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1179 base_addr = base_addr_cfg & 0x0000ff80;
1180 if (!base_addr) {
1181 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1182 ret = -ENODEV;
1183 goto wdt_done;
1184 }
1185
1186 res = wdt_io_res(ICH_RES_IO_TCO);
1187 res->start = base_addr + ACPIBASE_TCO_OFF;
1188 res->end = base_addr + ACPIBASE_TCO_END;
1189
1190 res = wdt_io_res(ICH_RES_IO_SMI);
1191 res->start = base_addr + ACPIBASE_SMI_OFF;
1192 res->end = base_addr + ACPIBASE_SMI_END;
1193
1194 lpc_ich_enable_acpi_space(dev);
1195
1196 /*
1197 * iTCO v2:
1198 * Get the Memory-Mapped GCS register. To get access to it
1199 * we have to read RCBA from PCI Config space 0xf0 and use
1200 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1201 *
1202 * iTCO v3:
1203 * Get the Power Management Configuration register. To get access
1204 * to it we have to read the PMC BASE from config space and address
1205 * the register at offset 0x8.
1206 */
1207 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1208 /* Don't register iomem for TCO ver 1 */
1209 lpc_ich_wdt_cell.num_resources--;
1210 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1211 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1212 base_addr = base_addr_cfg & 0xffffc000;
1213 if (!(base_addr_cfg & 1)) {
1214 dev_notice(&dev->dev, "RCBA is disabled by "
1215 "hardware/BIOS, device disabled\n");
1216 ret = -ENODEV;
1217 goto wdt_done;
1218 }
1219 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1220 res->start = base_addr + ACPIBASE_GCS_OFF;
1221 res->end = base_addr + ACPIBASE_GCS_END;
1222 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1223 lpc_ich_enable_pmc_space(dev);
1224 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1225 base_addr = base_addr_cfg & 0xfffffe00;
1226
1227 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1228 res->start = base_addr + ACPIBASE_PMC_OFF;
1229 res->end = base_addr + ACPIBASE_PMC_END;
1230 }
1231
1232 ret = lpc_ich_finalize_wdt_cell(dev);
1233 if (ret)
1234 goto wdt_done;
1235
1236 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1237 &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1238
1239wdt_done:
1240 return ret;
1241}
1242
1243static int lpc_ich_init_pinctrl(struct pci_dev *dev)
1244{
1245 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1246 const struct lpc_ich_gpio_info *info = lpc_chipset_info[priv->chipset].gpio_info;
1247 struct resource base;
1248 unsigned int i;
1249 int ret;
1250
1251 /* Check, if GPIO has been exported as an ACPI device */
1252 if (acpi_dev_present(info->hid, NULL, -1))
1253 return -EEXIST;
1254
1255 ret = p2sb_bar(dev->bus, 0, &base);
1256 if (ret)
1257 return ret;
1258
1259 for (i = 0; i < info->nr_resources; i++) {
1260 struct resource *mem = info->resources[i];
1261 resource_size_t offset = info->offsets[i];
1262
1263 /* Fill MEM resource */
1264 mem->start = base.start + offset;
1265 mem->end = base.start + offset + INTEL_GPIO_RESOURCE_SIZE - 1;
1266 mem->flags = base.flags;
1267 }
1268
1269 return mfd_add_devices(&dev->dev, 0, info->devices, info->nr_devices,
1270 NULL, 0, NULL);
1271}
1272
1273static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data)
1274{
1275 u32 val;
1276
1277 val = readl(base + BYT_BCR);
1278 if (!(val & BYT_BCR_WPD)) {
1279 val |= BYT_BCR_WPD;
1280 writel(val, base + BYT_BCR);
1281 val = readl(base + BYT_BCR);
1282 }
1283
1284 return val & BYT_BCR_WPD;
1285}
1286
1287static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn)
1288{
1289 u32 bcr;
1290
1291 pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
1292 if (!(bcr & BCR_WPD)) {
1293 bcr |= BCR_WPD;
1294 pci_bus_write_config_dword(bus, devfn, BCR, bcr);
1295 pci_bus_read_config_dword(bus, devfn, BCR, &bcr);
1296 }
1297
1298 return bcr & BCR_WPD;
1299}
1300
1301static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data)
1302{
1303 struct pci_dev *pdev = data;
1304
1305 return lpc_ich_set_writeable(pdev->bus, pdev->devfn);
1306}
1307
1308static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data)
1309{
1310 struct pci_dev *pdev = data;
1311
1312 return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2));
1313}
1314
1315static int lpc_ich_init_spi(struct pci_dev *dev)
1316{
1317 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1318 struct resource *res = &intel_spi_res[0];
1319 struct intel_spi_boardinfo *info;
1320 u32 spi_base, rcba;
1321 int ret;
1322
1323 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1324 if (!info)
1325 return -ENOMEM;
1326
1327 info->type = lpc_chipset_info[priv->chipset].spi_type;
1328
1329 switch (info->type) {
1330 case INTEL_SPI_BYT:
1331 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1332 if (spi_base & SPIBASE_BYT_EN) {
1333 res->start = ALIGN_DOWN(spi_base, SPIBASE_BYT_SZ);
1334 res->end = res->start + SPIBASE_BYT_SZ - 1;
1335
1336 info->set_writeable = lpc_ich_byt_set_writeable;
1337 }
1338 break;
1339
1340 case INTEL_SPI_LPT:
1341 pci_read_config_dword(dev, RCBABASE, &rcba);
1342 if (rcba & 1) {
1343 spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1344 res->start = spi_base + SPIBASE_LPT;
1345 res->end = res->start + SPIBASE_LPT_SZ - 1;
1346
1347 info->set_writeable = lpc_ich_lpt_set_writeable;
1348 info->data = dev;
1349 }
1350 break;
1351
1352 case INTEL_SPI_BXT:
1353 /*
1354 * The P2SB is hidden by BIOS and we need to unhide it in
1355 * order to read BAR of the SPI flash device. Once that is
1356 * done we hide it again.
1357 */
1358 ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res);
1359 if (ret)
1360 return ret;
1361
1362 info->set_writeable = lpc_ich_bxt_set_writeable;
1363 info->data = dev;
1364 break;
1365
1366 default:
1367 return -EINVAL;
1368 }
1369
1370 if (!res->start)
1371 return -ENODEV;
1372
1373 lpc_ich_spi_cell.platform_data = info;
1374 lpc_ich_spi_cell.pdata_size = sizeof(*info);
1375
1376 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1377 &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1378}
1379
1380static int lpc_ich_probe(struct pci_dev *dev,
1381 const struct pci_device_id *id)
1382{
1383 struct lpc_ich_priv *priv;
1384 int ret;
1385 bool cell_added = false;
1386
1387 priv = devm_kzalloc(&dev->dev,
1388 sizeof(struct lpc_ich_priv), GFP_KERNEL);
1389 if (!priv)
1390 return -ENOMEM;
1391
1392 priv->chipset = id->driver_data;
1393
1394 priv->actrl_pbase_save = -1;
1395 priv->abase_save = -1;
1396
1397 priv->abase = ACPIBASE;
1398 priv->actrl_pbase = ACPICTRL_PMCBASE;
1399
1400 priv->gctrl_save = -1;
1401 if (priv->chipset <= LPC_ICH5) {
1402 priv->gbase = GPIOBASE_ICH0;
1403 priv->gctrl = GPIOCTRL_ICH0;
1404 } else {
1405 priv->gbase = GPIOBASE_ICH6;
1406 priv->gctrl = GPIOCTRL_ICH6;
1407 }
1408
1409 pci_set_drvdata(dev, priv);
1410
1411 if (lpc_chipset_info[priv->chipset].iTCO_version) {
1412 ret = lpc_ich_init_wdt(dev);
1413 if (!ret)
1414 cell_added = true;
1415 }
1416
1417 if (lpc_chipset_info[priv->chipset].gpio_version) {
1418 ret = lpc_ich_init_gpio(dev);
1419 if (!ret)
1420 cell_added = true;
1421 }
1422
1423 if (lpc_chipset_info[priv->chipset].gpio_info) {
1424 ret = lpc_ich_init_pinctrl(dev);
1425 if (!ret)
1426 cell_added = true;
1427 }
1428
1429 if (lpc_chipset_info[priv->chipset].spi_type) {
1430 ret = lpc_ich_init_spi(dev);
1431 if (!ret)
1432 cell_added = true;
1433 }
1434
1435 /*
1436 * We only care if at least one or none of the cells registered
1437 * successfully.
1438 */
1439 if (!cell_added) {
1440 dev_warn(&dev->dev, "No MFD cells added\n");
1441 lpc_ich_restore_config_space(dev);
1442 return -ENODEV;
1443 }
1444
1445 return 0;
1446}
1447
1448static void lpc_ich_remove(struct pci_dev *dev)
1449{
1450 mfd_remove_devices(&dev->dev);
1451 lpc_ich_restore_config_space(dev);
1452}
1453
1454static struct pci_driver lpc_ich_driver = {
1455 .name = "lpc_ich",
1456 .id_table = lpc_ich_ids,
1457 .probe = lpc_ich_probe,
1458 .remove = lpc_ich_remove,
1459};
1460
1461module_pci_driver(lpc_ich_driver);
1462
1463MODULE_AUTHOR("Aaron Sierra <[email protected]>");
1464MODULE_DESCRIPTION("LPC interface for Intel ICH");
1465MODULE_LICENSE("GPL");