| 1 |
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| 2 | |
| 3 | * Copyright (C) ST-Ericsson SA 2010
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| 4 | *
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| 5 | * Author: Rabin Vincent <[email protected]> for ST-Ericsson
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| 6 |
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| 7 |
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| 8 | #ifndef __STMPE_H
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| 9 | #define __STMPE_H
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| 10 |
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| 11 | #include <linux/device.h>
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| 12 | #include <linux/mfd/core.h>
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| 13 | #include <linux/mfd/stmpe.h>
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| 14 | #include <linux/printk.h>
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| 15 | #include <linux/types.h>
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| 16 |
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| 17 | extern const struct dev_pm_ops stmpe_dev_pm_ops;
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| 18 |
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| 19 | #ifdef STMPE_DUMP_BYTES
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| 20 | static inline void stmpe_dump_bytes(const char *str, const void *buf,
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| 21 | size_t len)
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| 22 | {
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| 23 | print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len);
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| 24 | }
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| 25 | #else
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| 26 | static inline void stmpe_dump_bytes(const char *str, const void *buf,
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| 27 | size_t len)
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| 28 | {
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| 29 | }
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| 30 | #endif
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| 31 |
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| 32 | |
| 33 | * struct stmpe_variant_block - information about block
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| 34 | * @cell: base mfd cell
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| 35 | * @irq: interrupt number to be added to each IORESOURCE_IRQ
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| 36 | * in the cell
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| 37 | * @block: block id; used for identification with platform data and for
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| 38 | * enable and altfunc callbacks
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| 39 |
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| 40 | struct stmpe_variant_block {
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| 41 | const struct mfd_cell *cell;
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| 42 | int irq;
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| 43 | enum stmpe_block block;
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| 44 | };
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| 45 |
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| 46 | |
| 47 | * struct stmpe_variant_info - variant-specific information
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| 48 | * @name: part name
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| 49 | * @id_val: content of CHIPID register
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| 50 | * @id_mask: bits valid in CHIPID register for comparison with id_val
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| 51 | * @num_gpios: number of GPIOS
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| 52 | * @af_bits: number of bits used to specify the alternate function
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| 53 | * @regs: variant specific registers.
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| 54 | * @blocks: list of blocks present on this device
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| 55 | * @num_blocks: number of blocks present on this device
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| 56 | * @num_irqs: number of internal IRQs available on this device
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| 57 | * @enable: callback to enable the specified blocks.
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| 58 | * Called with the I/O lock held.
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| 59 | * @get_altfunc: callback to get the alternate function number for the
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| 60 | * specific block
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| 61 | * @enable_autosleep: callback to configure autosleep with specified timeout
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| 62 |
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| 63 | struct stmpe_variant_info {
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| 64 | const char *name;
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| 65 | u16 id_val;
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| 66 | u16 id_mask;
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| 67 | int num_gpios;
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| 68 | int af_bits;
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| 69 | const u8 *regs;
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| 70 | struct stmpe_variant_block *blocks;
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| 71 | int num_blocks;
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| 72 | int num_irqs;
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| 73 | int (*enable)(struct stmpe *stmpe, unsigned int blocks, bool enable);
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| 74 | int (*get_altfunc)(struct stmpe *stmpe, enum stmpe_block block);
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| 75 | int (*enable_autosleep)(struct stmpe *stmpe, int autosleep_timeout);
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| 76 | };
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| 77 |
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| 78 | |
| 79 | * struct stmpe_client_info - i2c or spi specific routines/info
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| 80 | * @data: client specific data
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| 81 | * @read_byte: read single byte
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| 82 | * @write_byte: write single byte
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| 83 | * @read_block: read block or multiple bytes
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| 84 | * @write_block: write block or multiple bytes
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| 85 | * @init: client init routine, called during probe
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| 86 |
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| 87 | struct stmpe_client_info {
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| 88 | void *data;
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| 89 | int irq;
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| 90 | void *client;
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| 91 | struct device *dev;
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| 92 | int (*read_byte)(struct stmpe *stmpe, u8 reg);
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| 93 | int (*write_byte)(struct stmpe *stmpe, u8 reg, u8 val);
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| 94 | int (*read_block)(struct stmpe *stmpe, u8 reg, u8 len, u8 *values);
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| 95 | int (*write_block)(struct stmpe *stmpe, u8 reg, u8 len,
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| 96 | const u8 *values);
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| 97 | void (*init)(struct stmpe *stmpe);
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| 98 | };
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| 99 |
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| 100 | int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum);
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| 101 | void stmpe_remove(struct stmpe *stmpe);
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| 102 |
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| 103 | #define STMPE_ICR_LSB_HIGH (1 << 2)
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| 104 | #define STMPE_ICR_LSB_EDGE (1 << 1)
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| 105 | #define STMPE_ICR_LSB_GIM (1 << 0)
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| 106 |
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| 107 | #define STMPE_SYS_CTRL_RESET (1 << 7)
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| 108 | #define STMPE_SYS_CTRL_INT_EN (1 << 2)
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| 109 | #define STMPE_SYS_CTRL_INT_HI (1 << 0)
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| 110 |
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| 111 | |
| 112 | * STMPE801
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| 113 |
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| 114 | #define STMPE801_ID 0x0108
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| 115 | #define STMPE801_NR_INTERNAL_IRQS 1
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| 116 |
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| 117 | #define STMPE801_REG_CHIP_ID 0x00
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| 118 | #define STMPE801_REG_VERSION_ID 0x02
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| 119 | #define STMPE801_REG_SYS_CTRL 0x04
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| 120 | #define STMPE801_REG_GPIO_INT_EN 0x08
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| 121 | #define STMPE801_REG_GPIO_INT_STA 0x09
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| 122 | #define STMPE801_REG_GPIO_MP_STA 0x10
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| 123 | #define STMPE801_REG_GPIO_SET_PIN 0x11
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| 124 | #define STMPE801_REG_GPIO_DIR 0x12
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| 125 |
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| 126 | |
| 127 | * STMPE811
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| 128 |
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| 129 | #define STMPE811_ID 0x0811
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| 130 |
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| 131 | #define STMPE811_IRQ_TOUCH_DET 0
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| 132 | #define STMPE811_IRQ_FIFO_TH 1
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| 133 | #define STMPE811_IRQ_FIFO_OFLOW 2
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| 134 | #define STMPE811_IRQ_FIFO_FULL 3
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| 135 | #define STMPE811_IRQ_FIFO_EMPTY 4
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| 136 | #define STMPE811_IRQ_TEMP_SENS 5
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| 137 | #define STMPE811_IRQ_ADC 6
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| 138 | #define STMPE811_IRQ_GPIOC 7
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| 139 | #define STMPE811_NR_INTERNAL_IRQS 8
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| 140 |
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| 141 | #define STMPE811_REG_CHIP_ID 0x00
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| 142 | #define STMPE811_REG_SYS_CTRL 0x03
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| 143 | #define STMPE811_REG_SYS_CTRL2 0x04
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| 144 | #define STMPE811_REG_SPI_CFG 0x08
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| 145 | #define STMPE811_REG_INT_CTRL 0x09
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| 146 | #define STMPE811_REG_INT_EN 0x0A
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| 147 | #define STMPE811_REG_INT_STA 0x0B
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| 148 | #define STMPE811_REG_GPIO_INT_EN 0x0C
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| 149 | #define STMPE811_REG_GPIO_INT_STA 0x0D
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| 150 | #define STMPE811_REG_GPIO_SET_PIN 0x10
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| 151 | #define STMPE811_REG_GPIO_CLR_PIN 0x11
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| 152 | #define STMPE811_REG_GPIO_MP_STA 0x12
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| 153 | #define STMPE811_REG_GPIO_DIR 0x13
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| 154 | #define STMPE811_REG_GPIO_ED 0x14
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| 155 | #define STMPE811_REG_GPIO_RE 0x15
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| 156 | #define STMPE811_REG_GPIO_FE 0x16
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| 157 | #define STMPE811_REG_GPIO_AF 0x17
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| 158 |
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| 159 | #define STMPE811_SYS_CTRL_RESET (1 << 1)
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| 160 |
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| 161 | #define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
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| 162 | #define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)
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| 163 | #define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)
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| 164 | #define STMPE811_SYS_CTRL2_TS_OFF (1 << 3)
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| 165 |
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| 166 | |
| 167 | * STMPE1600
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| 168 |
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| 169 | #define STMPE1600_ID 0x0016
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| 170 | #define STMPE1600_NR_INTERNAL_IRQS 16
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| 171 |
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| 172 | #define STMPE1600_REG_CHIP_ID 0x00
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| 173 | #define STMPE1600_REG_SYS_CTRL 0x03
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| 174 | #define STMPE1600_REG_IEGPIOR_LSB 0x08
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| 175 | #define STMPE1600_REG_IEGPIOR_MSB 0x09
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| 176 | #define STMPE1600_REG_ISGPIOR_LSB 0x0A
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| 177 | #define STMPE1600_REG_ISGPIOR_MSB 0x0B
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| 178 | #define STMPE1600_REG_GPMR_LSB 0x10
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| 179 | #define STMPE1600_REG_GPMR_MSB 0x11
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| 180 | #define STMPE1600_REG_GPSR_LSB 0x12
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| 181 | #define STMPE1600_REG_GPSR_MSB 0x13
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| 182 | #define STMPE1600_REG_GPDR_LSB 0x14
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| 183 | #define STMPE1600_REG_GPDR_MSB 0x15
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| 184 | #define STMPE1600_REG_GPPIR_LSB 0x16
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| 185 | #define STMPE1600_REG_GPPIR_MSB 0x17
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| 186 |
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| 187 | |
| 188 | * STMPE1601
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| 189 |
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| 190 |
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| 191 | #define STMPE1601_IRQ_GPIOC 8
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| 192 | #define STMPE1601_IRQ_PWM3 7
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| 193 | #define STMPE1601_IRQ_PWM2 6
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| 194 | #define STMPE1601_IRQ_PWM1 5
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| 195 | #define STMPE1601_IRQ_PWM0 4
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| 196 | #define STMPE1601_IRQ_KEYPAD_OVER 2
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| 197 | #define STMPE1601_IRQ_KEYPAD 1
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| 198 | #define STMPE1601_IRQ_WAKEUP 0
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| 199 | #define STMPE1601_NR_INTERNAL_IRQS 9
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| 200 |
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| 201 | #define STMPE1601_REG_SYS_CTRL 0x02
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| 202 | #define STMPE1601_REG_SYS_CTRL2 0x03
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| 203 | #define STMPE1601_REG_ICR_MSB 0x10
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| 204 | #define STMPE1601_REG_ICR_LSB 0x11
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| 205 | #define STMPE1601_REG_IER_MSB 0x12
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| 206 | #define STMPE1601_REG_IER_LSB 0x13
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| 207 | #define STMPE1601_REG_ISR_MSB 0x14
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| 208 | #define STMPE1601_REG_ISR_LSB 0x15
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| 209 | #define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16
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| 210 | #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17
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| 211 | #define STMPE1601_REG_INT_STA_GPIO_MSB 0x18
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| 212 | #define STMPE1601_REG_INT_STA_GPIO_LSB 0x19
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| 213 | #define STMPE1601_REG_CHIP_ID 0x80
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| 214 | #define STMPE1601_REG_GPIO_SET_MSB 0x82
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| 215 | #define STMPE1601_REG_GPIO_SET_LSB 0x83
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| 216 | #define STMPE1601_REG_GPIO_CLR_MSB 0x84
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| 217 | #define STMPE1601_REG_GPIO_CLR_LSB 0x85
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| 218 | #define STMPE1601_REG_GPIO_MP_MSB 0x86
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| 219 | #define STMPE1601_REG_GPIO_MP_LSB 0x87
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| 220 | #define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88
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| 221 | #define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89
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| 222 | #define STMPE1601_REG_GPIO_ED_MSB 0x8A
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| 223 | #define STMPE1601_REG_GPIO_ED_LSB 0x8B
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| 224 | #define STMPE1601_REG_GPIO_RE_MSB 0x8C
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| 225 | #define STMPE1601_REG_GPIO_RE_LSB 0x8D
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| 226 | #define STMPE1601_REG_GPIO_FE_MSB 0x8E
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| 227 | #define STMPE1601_REG_GPIO_FE_LSB 0x8F
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| 228 | #define STMPE1601_REG_GPIO_PU_MSB 0x90
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| 229 | #define STMPE1601_REG_GPIO_PU_LSB 0x91
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| 230 | #define STMPE1601_REG_GPIO_AF_U_MSB 0x92
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| 231 |
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| 232 | #define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3)
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| 233 | #define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1)
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| 234 | #define STMPE1601_SYS_CTRL_ENABLE_SPWM (1 << 0)
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| 235 |
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| 236 |
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| 237 | #define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)
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| 238 | #define STPME1601_AUTOSLEEP_ENABLE (1 << 3)
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| 239 |
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| 240 | |
| 241 | * STMPE1801
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| 242 |
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| 243 | #define STMPE1801_ID 0xc110
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| 244 | #define STMPE1801_NR_INTERNAL_IRQS 5
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| 245 | #define STMPE1801_IRQ_KEYPAD_COMBI 4
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| 246 | #define STMPE1801_IRQ_GPIOC 3
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| 247 | #define STMPE1801_IRQ_KEYPAD_OVER 2
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| 248 | #define STMPE1801_IRQ_KEYPAD 1
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| 249 | #define STMPE1801_IRQ_WAKEUP 0
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| 250 |
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| 251 | #define STMPE1801_REG_CHIP_ID 0x00
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| 252 | #define STMPE1801_REG_SYS_CTRL 0x02
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| 253 | #define STMPE1801_REG_INT_CTRL_LOW 0x04
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| 254 | #define STMPE1801_REG_INT_EN_MASK_LOW 0x06
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| 255 | #define STMPE1801_REG_INT_STA_LOW 0x08
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| 256 | #define STMPE1801_REG_INT_EN_GPIO_MASK_LOW 0x0A
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| 257 | #define STMPE1801_REG_INT_EN_GPIO_MASK_MID 0x0B
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| 258 | #define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH 0x0C
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| 259 | #define STMPE1801_REG_INT_STA_GPIO_LOW 0x0D
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| 260 | #define STMPE1801_REG_INT_STA_GPIO_MID 0x0E
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| 261 | #define STMPE1801_REG_INT_STA_GPIO_HIGH 0x0F
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| 262 | #define STMPE1801_REG_GPIO_SET_LOW 0x10
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| 263 | #define STMPE1801_REG_GPIO_SET_MID 0x11
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| 264 | #define STMPE1801_REG_GPIO_SET_HIGH 0x12
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| 265 | #define STMPE1801_REG_GPIO_CLR_LOW 0x13
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| 266 | #define STMPE1801_REG_GPIO_CLR_MID 0x14
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| 267 | #define STMPE1801_REG_GPIO_CLR_HIGH 0x15
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| 268 | #define STMPE1801_REG_GPIO_MP_LOW 0x16
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| 269 | #define STMPE1801_REG_GPIO_MP_MID 0x17
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| 270 | #define STMPE1801_REG_GPIO_MP_HIGH 0x18
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| 271 | #define STMPE1801_REG_GPIO_SET_DIR_LOW 0x19
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| 272 | #define STMPE1801_REG_GPIO_SET_DIR_MID 0x1A
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| 273 | #define STMPE1801_REG_GPIO_SET_DIR_HIGH 0x1B
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| 274 | #define STMPE1801_REG_GPIO_RE_LOW 0x1C
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| 275 | #define STMPE1801_REG_GPIO_RE_MID 0x1D
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| 276 | #define STMPE1801_REG_GPIO_RE_HIGH 0x1E
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| 277 | #define STMPE1801_REG_GPIO_FE_LOW 0x1F
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| 278 | #define STMPE1801_REG_GPIO_FE_MID 0x20
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| 279 | #define STMPE1801_REG_GPIO_FE_HIGH 0x21
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| 280 | #define STMPE1801_REG_GPIO_PULL_UP_LOW 0x22
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| 281 | #define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
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| 282 | #define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
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| 283 |
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| 284 | #define STMPE1801_MSK_INT_EN_KPC (1 << 1)
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| 285 | #define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
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| 286 |
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| 287 | |
| 288 | * STMPE24xx
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| 289 |
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| 290 |
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| 291 | #define STMPE24XX_IRQ_GPIOC 8
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| 292 | #define STMPE24XX_IRQ_PWM2 7
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| 293 | #define STMPE24XX_IRQ_PWM1 6
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| 294 | #define STMPE24XX_IRQ_PWM0 5
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| 295 | #define STMPE24XX_IRQ_ROT_OVER 4
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| 296 | #define STMPE24XX_IRQ_ROT 3
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| 297 | #define STMPE24XX_IRQ_KEYPAD_OVER 2
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| 298 | #define STMPE24XX_IRQ_KEYPAD 1
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| 299 | #define STMPE24XX_IRQ_WAKEUP 0
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| 300 | #define STMPE24XX_NR_INTERNAL_IRQS 9
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| 301 |
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| 302 | #define STMPE24XX_REG_SYS_CTRL 0x02
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| 303 | #define STMPE24XX_REG_SYS_CTRL2 0x03
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| 304 | #define STMPE24XX_REG_ICR_MSB 0x10
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| 305 | #define STMPE24XX_REG_ICR_LSB 0x11
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| 306 | #define STMPE24XX_REG_IER_MSB 0x12
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| 307 | #define STMPE24XX_REG_IER_LSB 0x13
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| 308 | #define STMPE24XX_REG_ISR_MSB 0x14
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| 309 | #define STMPE24XX_REG_ISR_LSB 0x15
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| 310 | #define STMPE24XX_REG_IEGPIOR_MSB 0x16
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| 311 | #define STMPE24XX_REG_IEGPIOR_CSB 0x17
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| 312 | #define STMPE24XX_REG_IEGPIOR_LSB 0x18
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| 313 | #define STMPE24XX_REG_ISGPIOR_MSB 0x19
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| 314 | #define STMPE24XX_REG_ISGPIOR_CSB 0x1A
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| 315 | #define STMPE24XX_REG_ISGPIOR_LSB 0x1B
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| 316 | #define STMPE24XX_REG_CHIP_ID 0x80
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| 317 | #define STMPE24XX_REG_GPSR_MSB 0x83
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| 318 | #define STMPE24XX_REG_GPSR_CSB 0x84
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| 319 | #define STMPE24XX_REG_GPSR_LSB 0x85
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| 320 | #define STMPE24XX_REG_GPCR_MSB 0x86
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| 321 | #define STMPE24XX_REG_GPCR_CSB 0x87
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| 322 | #define STMPE24XX_REG_GPCR_LSB 0x88
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| 323 | #define STMPE24XX_REG_GPDR_MSB 0x89
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| 324 | #define STMPE24XX_REG_GPDR_CSB 0x8A
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| 325 | #define STMPE24XX_REG_GPDR_LSB 0x8B
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| 326 | #define STMPE24XX_REG_GPEDR_MSB 0x8C
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| 327 | #define STMPE24XX_REG_GPEDR_CSB 0x8D
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| 328 | #define STMPE24XX_REG_GPEDR_LSB 0x8E
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| 329 | #define STMPE24XX_REG_GPRER_MSB 0x8F
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| 330 | #define STMPE24XX_REG_GPRER_CSB 0x90
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| 331 | #define STMPE24XX_REG_GPRER_LSB 0x91
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| 332 | #define STMPE24XX_REG_GPFER_MSB 0x92
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| 333 | #define STMPE24XX_REG_GPFER_CSB 0x93
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| 334 | #define STMPE24XX_REG_GPFER_LSB 0x94
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| 335 | #define STMPE24XX_REG_GPPUR_MSB 0x95
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| 336 | #define STMPE24XX_REG_GPPUR_CSB 0x96
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| 337 | #define STMPE24XX_REG_GPPUR_LSB 0x97
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| 338 | #define STMPE24XX_REG_GPPDR_MSB 0x98
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| 339 | #define STMPE24XX_REG_GPPDR_CSB 0x99
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| 340 | #define STMPE24XX_REG_GPPDR_LSB 0x9A
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| 341 | #define STMPE24XX_REG_GPAFR_U_MSB 0x9B
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| 342 | #define STMPE24XX_REG_GPMR_MSB 0xA2
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| 343 | #define STMPE24XX_REG_GPMR_CSB 0xA3
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| 344 | #define STMPE24XX_REG_GPMR_LSB 0xA4
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| 345 | #define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3)
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| 346 | #define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2)
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| 347 | #define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)
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| 348 | #define STMPE24XX_SYSCON_ENABLE_ROT (1 << 0)
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| 349 |
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| 350 | #endif
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