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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5
6#include <linux/module.h>
7#include <linux/kernel.h>
8#include <linux/types.h>
9#include <linux/fs.h>
10#include <linux/hex.h>
11#include <linux/uaccess.h>
12#include <linux/string.h>
13#include <linux/pci.h>
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/mutex.h>
17#include <linux/if_ether.h>
18#include <linux/ctype.h>
19#include <linux/dmi.h>
20#include <linux/of.h>
21
22#define PHUB_STATUS 0x00 /* Status Register offset */
23#define PHUB_CONTROL 0x04 /* Control Register offset */
24#define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */
25#define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */
26#define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
27#define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address
28 offset */
29#define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address
30 offset */
31#define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
32 (Intel EG20T PCH)*/
33#define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
34 offset(LAPIS Semicon ML7213)
35 */
36#define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
37 offset(LAPIS Semicon ML7223)
38 */
39
40/* MAX number of INT_REDUCE_CONTROL registers */
41#define MAX_NUM_INT_REDUCE_CONTROL_REG 128
42#define PCI_DEVICE_ID_PCH1_PHUB 0x8801
43#define PCH_MINOR_NOS 1
44#define CLKCFG_CAN_50MHZ 0x12000000
45#define CLKCFG_CANCLK_MASK 0xFF000000
46#define CLKCFG_UART_MASK 0xFFFFFF
47
48/* CM-iTC */
49#define CLKCFG_UART_48MHZ (1 << 16)
50#define CLKCFG_UART_25MHZ (2 << 16)
51#define CLKCFG_BAUDDIV (2 << 20)
52#define CLKCFG_PLL2VCO (8 << 9)
53#define CLKCFG_UARTCLKSEL (1 << 18)
54
55/* Macros for ML7213 */
56#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
57
58/* Macros for ML7223 */
59#define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
60#define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
61
62/* Macros for ML7831 */
63#define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801
64
65/* SROM ACCESS Macro */
66#define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
67
68/* Registers address offset */
69#define PCH_PHUB_ID_REG 0x0000
70#define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004
71#define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008
72#define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C
73#define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010
74#define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014
75#define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018
76#define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020
77#define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024
78#define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028
79#define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C
80#define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040
81#define CLKCFG_REG_OFFSET 0x500
82#define FUNCSEL_REG_OFFSET 0x508
83
84#define PCH_PHUB_OROM_SIZE 15360
85
86enum pch_phub_type {
87 PCH_EG20T,
88 PCH_ML7213,
89 PCH_ML7223M,
90 PCH_ML7223N,
91 PCH_ML7831,
92};
93
94/**
95 * struct pch_phub_reg - PHUB register structure
96 * @pch_phub_base_address: Register base address
97 * @pch_phub_extrom_base_address: external rom base address
98 * @pch_mac_start_address: MAC address area start address
99 * @pch_opt_rom_start_address: Option ROM start address
100 * @ioh_type: Save IOH type
101 * @pdev: pointer to pci device struct
102 */
103struct pch_phub_reg {
104 void __iomem *pch_phub_base_address;
105 void __iomem *pch_phub_extrom_base_address;
106 u32 pch_mac_start_address;
107 u32 pch_opt_rom_start_address;
108 enum pch_phub_type ioh_type;
109 struct pci_dev *pdev;
110};
111
112/* SROM SPEC for MAC address assignment offset */
113static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
114
115static DEFINE_MUTEX(pch_phub_mutex);
116
117/**
118 * pch_phub_read_modify_write_reg() - Reading modifying and writing register
119 * @chip: Pointer to the PHUB register structure
120 * @reg_addr_offset: Register offset address value.
121 * @data: Writing value.
122 * @mask: Mask value.
123 */
124static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
125 unsigned int reg_addr_offset,
126 unsigned int data, unsigned int mask)
127{
128 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
129 iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
130}
131
132/**
133 * pch_phub_read_serial_rom() - Reading Serial ROM
134 * @chip: Pointer to the PHUB register structure
135 * @offset_address: Serial ROM offset address to read.
136 * @data: Read buffer for specified Serial ROM value.
137 */
138static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
139 unsigned int offset_address, u8 *data)
140{
141 void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
142 offset_address;
143
144 *data = ioread8(mem_addr);
145}
146
147/**
148 * pch_phub_write_serial_rom() - Writing Serial ROM
149 * @chip: Pointer to the PHUB register structure
150 * @offset_address: Serial ROM offset address.
151 * @data: Serial ROM value to write.
152 */
153static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
154 unsigned int offset_address, u8 data)
155{
156 void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
157 (offset_address & PCH_WORD_ADDR_MASK);
158 int i;
159 unsigned int word_data;
160 unsigned int pos;
161 unsigned int mask;
162 pos = (offset_address % 4) * 8;
163 mask = ~(0xFF << pos);
164
165 iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
166 chip->pch_phub_extrom_base_address + PHUB_CONTROL);
167
168 word_data = ioread32(mem_addr);
169 iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
170
171 i = 0;
172 while (ioread8(chip->pch_phub_extrom_base_address +
173 PHUB_STATUS) != 0x00) {
174 msleep(1);
175 if (i == PHUB_TIMEOUT)
176 return -ETIMEDOUT;
177 i++;
178 }
179
180 iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
181 chip->pch_phub_extrom_base_address + PHUB_CONTROL);
182
183 return 0;
184}
185
186/**
187 * pch_phub_read_serial_rom_val() - Read Serial ROM value
188 * @chip: Pointer to the PHUB register structure
189 * @offset_address: Serial ROM address offset value.
190 * @data: Serial ROM value to read.
191 */
192static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
193 unsigned int offset_address, u8 *data)
194{
195 unsigned int mem_addr;
196
197 mem_addr = chip->pch_mac_start_address +
198 pch_phub_mac_offset[offset_address];
199
200 pch_phub_read_serial_rom(chip, mem_addr, data);
201}
202
203/**
204 * pch_phub_write_serial_rom_val() - writing Serial ROM value
205 * @chip: Pointer to the PHUB register structure
206 * @offset_address: Serial ROM address offset value.
207 * @data: Serial ROM value.
208 */
209static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
210 unsigned int offset_address, u8 data)
211{
212 int retval;
213 unsigned int mem_addr;
214
215 mem_addr = chip->pch_mac_start_address +
216 pch_phub_mac_offset[offset_address];
217
218 retval = pch_phub_write_serial_rom(chip, mem_addr, data);
219
220 return retval;
221}
222
223/* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
224 * for Gigabit Ethernet MAC address
225 */
226static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
227{
228 int retval;
229
230 retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
231 retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
232 retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
233 retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
234
235 retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
236 retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
237 retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
238 retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
239
240 retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
241 retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
242 retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
243 retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
244
245 retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
246 retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
247 retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
248 retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
249
250 retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
251 retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
252 retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
253 retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
254
255 retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
256 retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
257 retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
258 retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
259
260 return retval;
261}
262
263/* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
264 * for Gigabit Ethernet MAC address
265 */
266static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
267{
268 int retval;
269 u32 offset_addr;
270
271 offset_addr = 0x200;
272 retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
273 retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
274 retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
275 retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
276
277 retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
278 retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
279 retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
280 retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
281
282 retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
283 retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
284 retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
285 retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
286
287 retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
288 retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
289 retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
290 retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
291
292 retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
293 retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
294 retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
295 retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
296
297 retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
298 retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
299 retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
300 retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
301
302 return retval;
303}
304
305/**
306 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
307 * @chip: Pointer to the PHUB register structure
308 * @data: Buffer of the Gigabit Ethernet MAC address value.
309 */
310static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
311{
312 int i;
313 for (i = 0; i < ETH_ALEN; i++)
314 pch_phub_read_serial_rom_val(chip, i, &data[i]);
315}
316
317/**
318 * pch_phub_write_gbe_mac_addr() - Write MAC address
319 * @chip: Pointer to the PHUB register structure
320 * @data: Gigabit Ethernet MAC address value.
321 */
322static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
323{
324 int retval;
325 int i;
326
327 switch (chip->ioh_type) {
328 case PCH_EG20T:
329 case PCH_ML7831:
330 retval = pch_phub_gbe_serial_rom_conf(chip);
331 break;
332
333 case PCH_ML7213:
334 case PCH_ML7223M:
335 case PCH_ML7223N:
336 retval = pch_phub_gbe_serial_rom_conf_mp(chip);
337 break;
338 }
339
340 if (retval)
341 return retval;
342
343 for (i = 0; i < ETH_ALEN; i++) {
344 retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
345 if (retval)
346 return retval;
347 }
348
349 return retval;
350}
351
352static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
353 const struct bin_attribute *attr, char *buf,
354 loff_t off, size_t count)
355{
356 unsigned int rom_signature;
357 unsigned char rom_length;
358 unsigned int tmp;
359 unsigned int addr_offset;
360 unsigned int orom_size;
361 int ret;
362 int err;
363 ssize_t rom_size;
364
365 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
366
367 ret = mutex_lock_interruptible(&pch_phub_mutex);
368 if (ret) {
369 err = -ERESTARTSYS;
370 goto return_err_nomutex;
371 }
372
373 /* Get Rom signature */
374 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
375 if (!chip->pch_phub_extrom_base_address) {
376 err = -ENODATA;
377 goto exrom_map_err;
378 }
379
380 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
381 (unsigned char *)&rom_signature);
382 rom_signature &= 0xff;
383 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
384 (unsigned char *)&tmp);
385 rom_signature |= (tmp & 0xff) << 8;
386 if (rom_signature == 0xAA55) {
387 pch_phub_read_serial_rom(chip,
388 chip->pch_opt_rom_start_address + 2,
389 &rom_length);
390 orom_size = rom_length * 512;
391 if (orom_size < off) {
392 addr_offset = 0;
393 goto return_ok;
394 }
395 if (orom_size < count) {
396 addr_offset = 0;
397 goto return_ok;
398 }
399
400 for (addr_offset = 0; addr_offset < count; addr_offset++) {
401 pch_phub_read_serial_rom(chip,
402 chip->pch_opt_rom_start_address + addr_offset + off,
403 &buf[addr_offset]);
404 }
405 } else {
406 err = -ENODATA;
407 goto return_err;
408 }
409return_ok:
410 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
411 mutex_unlock(&pch_phub_mutex);
412 return addr_offset;
413
414return_err:
415 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
416exrom_map_err:
417 mutex_unlock(&pch_phub_mutex);
418return_err_nomutex:
419 return err;
420}
421
422static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
423 const struct bin_attribute *attr,
424 char *buf, loff_t off, size_t count)
425{
426 int err;
427 unsigned int addr_offset;
428 int ret;
429 ssize_t rom_size;
430 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj));
431
432 ret = mutex_lock_interruptible(&pch_phub_mutex);
433 if (ret)
434 return -ERESTARTSYS;
435
436 if (off > PCH_PHUB_OROM_SIZE) {
437 addr_offset = 0;
438 goto return_ok;
439 }
440 if (count > PCH_PHUB_OROM_SIZE) {
441 addr_offset = 0;
442 goto return_ok;
443 }
444
445 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
446 if (!chip->pch_phub_extrom_base_address) {
447 err = -ENOMEM;
448 goto exrom_map_err;
449 }
450
451 for (addr_offset = 0; addr_offset < count; addr_offset++) {
452 if (PCH_PHUB_OROM_SIZE < off + addr_offset)
453 goto return_ok;
454
455 ret = pch_phub_write_serial_rom(chip,
456 chip->pch_opt_rom_start_address + addr_offset + off,
457 buf[addr_offset]);
458 if (ret) {
459 err = ret;
460 goto return_err;
461 }
462 }
463
464return_ok:
465 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
466 mutex_unlock(&pch_phub_mutex);
467 return addr_offset;
468
469return_err:
470 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
471
472exrom_map_err:
473 mutex_unlock(&pch_phub_mutex);
474 return err;
475}
476
477static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
478 char *buf)
479{
480 u8 mac[8];
481 struct pch_phub_reg *chip = dev_get_drvdata(dev);
482 ssize_t rom_size;
483
484 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
485 if (!chip->pch_phub_extrom_base_address)
486 return -ENOMEM;
487
488 pch_phub_read_gbe_mac_addr(chip, mac);
489 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
490
491 return sprintf(buf, "%pM\n", mac);
492}
493
494static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
495 const char *buf, size_t count)
496{
497 u8 mac[ETH_ALEN];
498 ssize_t rom_size;
499 struct pch_phub_reg *chip = dev_get_drvdata(dev);
500 int ret;
501
502 if (!mac_pton(buf, mac))
503 return -EINVAL;
504
505 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
506 if (!chip->pch_phub_extrom_base_address)
507 return -ENOMEM;
508
509 ret = pch_phub_write_gbe_mac_addr(chip, mac);
510 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
511 if (ret)
512 return ret;
513
514 return count;
515}
516
517static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
518
519static const struct bin_attribute pch_bin_attr = {
520 .attr = {
521 .name = "pch_firmware",
522 .mode = S_IRUGO | S_IWUSR,
523 },
524 .size = PCH_PHUB_OROM_SIZE + 1,
525 .read = pch_phub_bin_read,
526 .write = pch_phub_bin_write,
527};
528
529static int pch_phub_probe(struct pci_dev *pdev,
530 const struct pci_device_id *id)
531{
532 int ret;
533 struct pch_phub_reg *chip;
534
535 chip = kzalloc_obj(struct pch_phub_reg);
536 if (chip == NULL)
537 return -ENOMEM;
538
539 ret = pci_enable_device(pdev);
540 if (ret) {
541 dev_err(&pdev->dev,
542 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
543 goto err_pci_enable_dev;
544 }
545 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
546 ret);
547
548 ret = pci_request_regions(pdev, KBUILD_MODNAME);
549 if (ret) {
550 dev_err(&pdev->dev,
551 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
552 goto err_req_regions;
553 }
554 dev_dbg(&pdev->dev, "%s : "
555 "pci_request_regions returns %d\n", __func__, ret);
556
557 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
558
559
560 if (chip->pch_phub_base_address == NULL) {
561 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
562 ret = -ENOMEM;
563 goto err_pci_iomap;
564 }
565 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
566 "in pch_phub_base_address variable is %p\n", __func__,
567 chip->pch_phub_base_address);
568
569 chip->pdev = pdev; /* Save pci device struct */
570
571 if (id->driver_data == PCH_EG20T) { /* EG20T PCH */
572 const char *board_name;
573 unsigned int prefetch = 0x000affaa;
574
575 if (pdev->dev.of_node)
576 of_property_read_u32(pdev->dev.of_node,
577 "intel,eg20t-prefetch",
578 &prefetch);
579
580 ret = sysfs_create_file(&pdev->dev.kobj,
581 &dev_attr_pch_mac.attr);
582 if (ret)
583 goto err_sysfs_create;
584
585 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
586 if (ret)
587 goto exit_bin_attr;
588
589 pch_phub_read_modify_write_reg(chip,
590 (unsigned int)CLKCFG_REG_OFFSET,
591 CLKCFG_CAN_50MHZ,
592 CLKCFG_CANCLK_MASK);
593
594 /* quirk for CM-iTC board */
595 board_name = dmi_get_system_info(DMI_BOARD_NAME);
596 if (board_name && strstr(board_name, "CM-iTC"))
597 pch_phub_read_modify_write_reg(chip,
598 (unsigned int)CLKCFG_REG_OFFSET,
599 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
600 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
601 CLKCFG_UART_MASK);
602
603 /* set the prefech value */
604 iowrite32(prefetch, chip->pch_phub_base_address + 0x14);
605 /* set the interrupt delay value */
606 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
607 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
608 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
609
610 /* quirk for MIPS Boston platform */
611 if (pdev->dev.of_node) {
612 if (of_machine_is_compatible("img,boston")) {
613 pch_phub_read_modify_write_reg(chip,
614 (unsigned int)CLKCFG_REG_OFFSET,
615 CLKCFG_UART_25MHZ,
616 CLKCFG_UART_MASK);
617 }
618 }
619 } else if (id->driver_data == PCH_ML7213) { /* ML7213 IOH */
620 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
621 if (ret)
622 goto err_sysfs_create;
623 /* set the prefech value
624 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
625 * Device4(SDIO #0,1,2):f
626 * Device6(SATA 2):f
627 * Device8(USB OHCI #0/ USB EHCI #0):a
628 */
629 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
630 chip->pch_opt_rom_start_address =\
631 PCH_PHUB_ROM_START_ADDR_ML7213;
632 } else if (id->driver_data == PCH_ML7223M) { /* ML7223 IOH Bus-m*/
633 /* set the prefech value
634 * Device8(GbE)
635 */
636 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
637 /* set the interrupt delay value */
638 iowrite32(0x25, chip->pch_phub_base_address + 0x140);
639 chip->pch_opt_rom_start_address =\
640 PCH_PHUB_ROM_START_ADDR_ML7223;
641 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
642 } else if (id->driver_data == PCH_ML7223N) { /* ML7223 IOH Bus-n*/
643 ret = sysfs_create_file(&pdev->dev.kobj,
644 &dev_attr_pch_mac.attr);
645 if (ret)
646 goto err_sysfs_create;
647 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
648 if (ret)
649 goto exit_bin_attr;
650 /* set the prefech value
651 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
652 * Device4(SDIO #0,1):f
653 * Device6(SATA 2):f
654 */
655 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
656 chip->pch_opt_rom_start_address =\
657 PCH_PHUB_ROM_START_ADDR_ML7223;
658 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
659 } else if (id->driver_data == PCH_ML7831) { /* ML7831 */
660 ret = sysfs_create_file(&pdev->dev.kobj,
661 &dev_attr_pch_mac.attr);
662 if (ret)
663 goto err_sysfs_create;
664
665 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
666 if (ret)
667 goto exit_bin_attr;
668
669 /* set the prefech value */
670 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
671 /* set the interrupt delay value */
672 iowrite32(0x25, chip->pch_phub_base_address + 0x44);
673 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
674 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
675 }
676
677 chip->ioh_type = id->driver_data;
678 pci_set_drvdata(pdev, chip);
679
680 return 0;
681exit_bin_attr:
682 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
683
684err_sysfs_create:
685 pci_iounmap(pdev, chip->pch_phub_base_address);
686err_pci_iomap:
687 pci_release_regions(pdev);
688err_req_regions:
689 pci_disable_device(pdev);
690err_pci_enable_dev:
691 kfree(chip);
692 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
693 return ret;
694}
695
696static void pch_phub_remove(struct pci_dev *pdev)
697{
698 struct pch_phub_reg *chip = pci_get_drvdata(pdev);
699
700 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
701 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
702 pci_iounmap(pdev, chip->pch_phub_base_address);
703 pci_release_regions(pdev);
704 pci_disable_device(pdev);
705 kfree(chip);
706}
707
708static int __maybe_unused pch_phub_suspend(struct device *dev_d)
709{
710 device_wakeup_disable(dev_d);
711
712 return 0;
713}
714
715static int __maybe_unused pch_phub_resume(struct device *dev_d)
716{
717 device_wakeup_disable(dev_d);
718
719 return 0;
720}
721
722static const struct pci_device_id pch_phub_pcidev_id[] = {
723 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), .driver_data = PCH_EG20T },
724 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), .driver_data = PCH_ML7213 },
725 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), .driver_data = PCH_ML7223M },
726 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), .driver_data = PCH_ML7223N },
727 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), .driver_data = PCH_ML7831 },
728 { }
729};
730MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
731
732static SIMPLE_DEV_PM_OPS(pch_phub_pm_ops, pch_phub_suspend, pch_phub_resume);
733
734static struct pci_driver pch_phub_driver = {
735 .name = "pch_phub",
736 .id_table = pch_phub_pcidev_id,
737 .probe = pch_phub_probe,
738 .remove = pch_phub_remove,
739 .driver.pm = &pch_phub_pm_ops,
740};
741
742module_pci_driver(pch_phub_driver);
743
744MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB");
745MODULE_LICENSE("GPL");