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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MMIO register bitfield-controlled multiplexer driver
4 *
5 * Copyright (C) 2017 Pengutronix, Philipp Zabel <[email protected]>
6 */
7
8#include <linux/bitops.h>
9#include <linux/err.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/mux/driver.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/property.h>
16#include <linux/regmap.h>
17
18struct mux_mmio {
19 struct regmap_field **fields;
20 unsigned int *hardware_states;
21};
22
23static int mux_mmio_get(struct mux_control *mux, int *state)
24{
25 struct mux_mmio *mux_mmio = mux_chip_priv(mux->chip);
26 unsigned int index = mux_control_get_index(mux);
27
28 return regmap_field_read(mux_mmio->fields[index], state);
29}
30
31static int mux_mmio_set(struct mux_control *mux, int state)
32{
33 struct mux_mmio *mux_mmio = mux_chip_priv(mux->chip);
34 unsigned int index = mux_control_get_index(mux);
35
36 return regmap_field_write(mux_mmio->fields[index], state);
37}
38
39static const struct mux_control_ops mux_mmio_ops = {
40 .set = mux_mmio_set,
41};
42
43static const struct of_device_id mux_mmio_dt_ids[] = {
44 { .compatible = "mmio-mux", },
45 { .compatible = "reg-mux", },
46 { /* sentinel */ }
47};
48MODULE_DEVICE_TABLE(of, mux_mmio_dt_ids);
49
50static const struct regmap_config mux_mmio_regmap_cfg = {
51 .reg_bits = 32,
52 .val_bits = 32,
53 .reg_stride = 4,
54};
55
56static int mux_mmio_probe(struct platform_device *pdev)
57{
58 struct device *dev = &pdev->dev;
59 struct device_node *np = dev->of_node;
60 struct mux_chip *mux_chip;
61 struct mux_mmio *mux_mmio;
62 struct regmap *regmap;
63 void __iomem *base;
64 int num_fields;
65 int ret;
66 int i;
67
68 if (of_device_is_compatible(np, "mmio-mux")) {
69 regmap = syscon_node_to_regmap(np->parent);
70 } else {
71 base = devm_platform_ioremap_resource(pdev, 0);
72 if (IS_ERR(base))
73 regmap = ERR_PTR(-ENODEV);
74 else
75 regmap = devm_regmap_init_mmio(dev, base, &mux_mmio_regmap_cfg);
76 /* Fallback to checking the parent node on "real" errors. */
77 if (IS_ERR(regmap) && regmap != ERR_PTR(-EPROBE_DEFER)) {
78 regmap = dev_get_regmap(dev->parent, NULL);
79 if (!regmap)
80 regmap = ERR_PTR(-ENODEV);
81 }
82 }
83 if (IS_ERR(regmap))
84 return dev_err_probe(dev, PTR_ERR(regmap),
85 "failed to get regmap\n");
86
87 ret = of_property_count_u32_elems(np, "mux-reg-masks");
88 if (ret == 0 || ret % 2)
89 ret = -EINVAL;
90 if (ret < 0) {
91 dev_err(dev, "mux-reg-masks property missing or invalid: %d\n",
92 ret);
93 return ret;
94 }
95 num_fields = ret / 2;
96
97 mux_chip = devm_mux_chip_alloc(dev, num_fields, sizeof(struct mux_mmio));
98 if (IS_ERR(mux_chip))
99 return PTR_ERR(mux_chip);
100
101 mux_mmio = mux_chip_priv(mux_chip);
102
103 mux_mmio->fields = devm_kcalloc(dev, num_fields, sizeof(*mux_mmio->fields),
104 GFP_KERNEL);
105 if (!mux_mmio->fields)
106 return -ENOMEM;
107
108 mux_mmio->hardware_states = devm_kcalloc(dev, num_fields,
109 sizeof(*mux_mmio->hardware_states),
110 GFP_KERNEL);
111 if (!mux_mmio->hardware_states)
112 return -ENOMEM;
113
114 for (i = 0; i < num_fields; i++) {
115 struct mux_control *mux = &mux_chip->mux[i];
116 struct reg_field field;
117 s32 idle_state = MUX_IDLE_AS_IS;
118 u32 reg, mask;
119 int bits;
120
121 ret = of_property_read_u32_index(np, "mux-reg-masks",
122 2 * i, &reg);
123 if (!ret)
124 ret = of_property_read_u32_index(np, "mux-reg-masks",
125 2 * i + 1, &mask);
126 if (ret < 0) {
127 dev_err(dev, "bitfield %d: failed to read mux-reg-masks property: %d\n",
128 i, ret);
129 return ret;
130 }
131
132 field.reg = reg;
133 field.msb = fls(mask) - 1;
134 field.lsb = ffs(mask) - 1;
135
136 if (mask != GENMASK(field.msb, field.lsb)) {
137 dev_err(dev, "bitfield %d: invalid mask 0x%x\n",
138 i, mask);
139 return -EINVAL;
140 }
141
142 mux_mmio->fields[i] = devm_regmap_field_alloc(dev, regmap, field);
143 if (IS_ERR(mux_mmio->fields[i])) {
144 ret = PTR_ERR(mux_mmio->fields[i]);
145 dev_err(dev, "bitfield %d: failed to allocate: %d\n",
146 i, ret);
147 return ret;
148 }
149
150 bits = 1 + field.msb - field.lsb;
151 mux->states = 1 << bits;
152
153 of_property_read_u32_index(np, "idle-states", i,
154 (u32 *)&idle_state);
155 if (idle_state != MUX_IDLE_AS_IS) {
156 if (idle_state < 0 || idle_state >= mux->states) {
157 dev_err(dev, "bitfield: %d: out of range idle state %d\n",
158 i, idle_state);
159 return -EINVAL;
160 }
161
162 mux->idle_state = idle_state;
163 }
164 }
165
166 mux_chip->ops = &mux_mmio_ops;
167
168 dev_set_drvdata(dev, mux_chip);
169
170 return devm_mux_chip_register(dev, mux_chip);
171}
172
173static int mux_mmio_suspend_noirq(struct device *dev)
174{
175 struct mux_chip *mux_chip = dev_get_drvdata(dev);
176 struct mux_mmio *mux_mmio = mux_chip_priv(mux_chip);
177 unsigned int state;
178 int ret, i;
179
180 for (i = 0; i < mux_chip->controllers; i++) {
181 ret = mux_mmio_get(&mux_chip->mux[i], &state);
182 if (ret) {
183 dev_err(dev, "control %u: error saving mux: %d\n", i, ret);
184 return ret;
185 }
186
187 mux_mmio->hardware_states[i] = state;
188 }
189
190 return 0;
191}
192
193static int mux_mmio_resume_noirq(struct device *dev)
194{
195 struct mux_chip *mux_chip = dev_get_drvdata(dev);
196 struct mux_mmio *mux_mmio = mux_chip_priv(mux_chip);
197 int ret, i;
198
199 for (i = 0; i < mux_chip->controllers; i++) {
200 ret = mux_mmio_set(&mux_chip->mux[i], mux_mmio->hardware_states[i]);
201 if (ret) {
202 dev_err(dev, "control %u: error restoring mux: %d\n", i, ret);
203 return ret;
204 }
205 }
206
207 return 0;
208}
209
210static DEFINE_NOIRQ_DEV_PM_OPS(mux_mmio_pm_ops, mux_mmio_suspend_noirq, mux_mmio_resume_noirq);
211
212static struct platform_driver mux_mmio_driver = {
213 .driver = {
214 .name = "mmio-mux",
215 .of_match_table = mux_mmio_dt_ids,
216 .pm = pm_sleep_ptr(&mux_mmio_pm_ops),
217 },
218 .probe = mux_mmio_probe,
219};
220module_platform_driver(mux_mmio_driver);
221
222MODULE_DESCRIPTION("MMIO register bitfield-controlled multiplexer driver");
223MODULE_AUTHOR("Philipp Zabel <[email protected]>");
224MODULE_LICENSE("GPL v2");